1135446Strhodes[
2135446Strhodes    {
3135446Strhodes        "ArchStdEvent": "LD_RETIRED"
4135446Strhodes    },
5135446Strhodes    {
6135446Strhodes        "ArchStdEvent": "MEM_ACCESS_RD"
7135446Strhodes    },
8135446Strhodes    {
9135446Strhodes        "ArchStdEvent": "MEM_ACCESS_WR"
10135446Strhodes    },
11135446Strhodes    {
12135446Strhodes        "ArchStdEvent": "UNALIGNED_LD_SPEC"
13135446Strhodes    },
14135446Strhodes    {
15135446Strhodes        "ArchStdEvent": "UNALIGNED_ST_SPEC"
16135446Strhodes    },
17135446Strhodes    {
18135446Strhodes        "ArchStdEvent": "UNALIGNED_LDST_SPEC"
19135446Strhodes    },
20135446Strhodes    {
21135446Strhodes        "ArchStdEvent": "LD_ALIGN_LAT"
22135446Strhodes    },
23135446Strhodes    {
24135446Strhodes        "ArchStdEvent": "ST_ALIGN_LAT"
25135446Strhodes    },
26135446Strhodes    {
27135446Strhodes        "ArchStdEvent": "MEM_ACCESS"
28135446Strhodes    },
29135446Strhodes    {
30135446Strhodes        "ArchStdEvent": "MEMORY_ERROR"
31135446Strhodes    },
32135446Strhodes    {
33135446Strhodes        "ArchStdEvent": "LDST_ALIGN_LAT"
34135446Strhodes    },
35135446Strhodes    {
36135446Strhodes        "ArchStdEvent": "MEM_ACCESS_CHECKED"
37135446Strhodes    },
38135446Strhodes    {
39135446Strhodes        "ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
40135446Strhodes    },
41135446Strhodes    {
42135446Strhodes        "ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
43135446Strhodes    }
44135446Strhodes]
45135446Strhodes