1[
2    {
3        "ArchStdEvent": "LD_RETIRED"
4    },
5    {
6        "ArchStdEvent": "MEM_ACCESS_RD"
7    },
8    {
9        "ArchStdEvent": "MEM_ACCESS_WR"
10    },
11    {
12        "ArchStdEvent": "UNALIGNED_LD_SPEC"
13    },
14    {
15        "ArchStdEvent": "UNALIGNED_ST_SPEC"
16    },
17    {
18        "ArchStdEvent": "UNALIGNED_LDST_SPEC"
19    },
20    {
21        "ArchStdEvent": "LD_ALIGN_LAT"
22    },
23    {
24        "ArchStdEvent": "ST_ALIGN_LAT"
25    },
26    {
27        "ArchStdEvent": "MEM_ACCESS"
28    },
29    {
30        "ArchStdEvent": "MEMORY_ERROR"
31    },
32    {
33        "ArchStdEvent": "LDST_ALIGN_LAT"
34    },
35    {
36        "ArchStdEvent": "MEM_ACCESS_CHECKED"
37    },
38    {
39        "ArchStdEvent": "MEM_ACCESS_CHECKED_RD"
40    },
41    {
42        "ArchStdEvent": "MEM_ACCESS_CHECKED_WR"
43    }
44]
45