1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2/* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/uapi/asm/kvm.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#ifndef __ARM_KVM_H__ 24#define __ARM_KVM_H__ 25 26#define KVM_SPSR_EL1 0 27#define KVM_SPSR_SVC KVM_SPSR_EL1 28#define KVM_SPSR_ABT 1 29#define KVM_SPSR_UND 2 30#define KVM_SPSR_IRQ 3 31#define KVM_SPSR_FIQ 4 32#define KVM_NR_SPSR 5 33 34#ifndef __ASSEMBLY__ 35#include <linux/psci.h> 36#include <linux/types.h> 37#include <asm/ptrace.h> 38#include <asm/sve_context.h> 39 40#define __KVM_HAVE_IRQ_LINE 41#define __KVM_HAVE_VCPU_EVENTS 42 43#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 44#define KVM_DIRTY_LOG_PAGE_OFFSET 64 45 46#define KVM_REG_SIZE(id) \ 47 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 48 49struct kvm_regs { 50 struct user_pt_regs regs; /* sp = sp_el0 */ 51 52 __u64 sp_el1; 53 __u64 elr_el1; 54 55 __u64 spsr[KVM_NR_SPSR]; 56 57 struct user_fpsimd_state fp_regs; 58}; 59 60/* 61 * Supported CPU Targets - Adding a new target type is not recommended, 62 * unless there are some special registers not supported by the 63 * genericv8 syreg table. 64 */ 65#define KVM_ARM_TARGET_AEM_V8 0 66#define KVM_ARM_TARGET_FOUNDATION_V8 1 67#define KVM_ARM_TARGET_CORTEX_A57 2 68#define KVM_ARM_TARGET_XGENE_POTENZA 3 69#define KVM_ARM_TARGET_CORTEX_A53 4 70/* Generic ARM v8 target */ 71#define KVM_ARM_TARGET_GENERIC_V8 5 72 73#define KVM_ARM_NUM_TARGETS 6 74 75/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 76#define KVM_ARM_DEVICE_TYPE_SHIFT 0 77#define KVM_ARM_DEVICE_TYPE_MASK __GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \ 78 KVM_ARM_DEVICE_TYPE_SHIFT) 79#define KVM_ARM_DEVICE_ID_SHIFT 16 80#define KVM_ARM_DEVICE_ID_MASK __GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \ 81 KVM_ARM_DEVICE_ID_SHIFT) 82 83/* Supported device IDs */ 84#define KVM_ARM_DEVICE_VGIC_V2 0 85 86/* Supported VGIC address types */ 87#define KVM_VGIC_V2_ADDR_TYPE_DIST 0 88#define KVM_VGIC_V2_ADDR_TYPE_CPU 1 89 90#define KVM_VGIC_V2_DIST_SIZE 0x1000 91#define KVM_VGIC_V2_CPU_SIZE 0x2000 92 93/* Supported VGICv3 address types */ 94#define KVM_VGIC_V3_ADDR_TYPE_DIST 2 95#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 96#define KVM_VGIC_ITS_ADDR_TYPE 4 97#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 98 99#define KVM_VGIC_V3_DIST_SIZE SZ_64K 100#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 101#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 102 103#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 104#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 105#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 106#define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 107#define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ 108#define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ 109#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ 110#define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */ 111 112struct kvm_vcpu_init { 113 __u32 target; 114 __u32 features[7]; 115}; 116 117struct kvm_sregs { 118}; 119 120struct kvm_fpu { 121}; 122 123/* 124 * See v8 ARM ARM D7.3: Debug Registers 125 * 126 * The architectural limit is 16 debug registers of each type although 127 * in practice there are usually less (see ID_AA64DFR0_EL1). 128 * 129 * Although the control registers are architecturally defined as 32 130 * bits wide we use a 64 bit structure here to keep parity with 131 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 132 * 64 bit values. It also allows for the possibility of the 133 * architecture expanding the control registers without having to 134 * change the userspace ABI. 135 */ 136#define KVM_ARM_MAX_DBG_REGS 16 137struct kvm_guest_debug_arch { 138 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 139 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 140 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 141 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 142}; 143 144#define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0) 145struct kvm_debug_exit_arch { 146 __u32 hsr; 147 __u32 hsr_high; /* ESR_EL2[61:32] */ 148 __u64 far; /* used for watchpoints */ 149}; 150 151/* 152 * Architecture specific defines for kvm_guest_debug->control 153 */ 154 155#define KVM_GUESTDBG_USE_SW_BP (1 << 16) 156#define KVM_GUESTDBG_USE_HW (1 << 17) 157 158struct kvm_sync_regs { 159 /* Used with KVM_CAP_ARM_USER_IRQ */ 160 __u64 device_irq_level; 161}; 162 163/* Bits for run->s.regs.device_irq_level */ 164#define KVM_ARM_DEV_EL1_VTIMER (1 << 0) 165#define KVM_ARM_DEV_EL1_PTIMER (1 << 1) 166#define KVM_ARM_DEV_PMU (1 << 2) 167 168/* 169 * PMU filter structure. Describe a range of events with a particular 170 * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER. 171 */ 172struct kvm_pmu_event_filter { 173 __u16 base_event; 174 __u16 nevents; 175 176#define KVM_PMU_EVENT_ALLOW 0 177#define KVM_PMU_EVENT_DENY 1 178 179 __u8 action; 180 __u8 pad[3]; 181}; 182 183/* for KVM_GET/SET_VCPU_EVENTS */ 184struct kvm_vcpu_events { 185 struct { 186 __u8 serror_pending; 187 __u8 serror_has_esr; 188 __u8 ext_dabt_pending; 189 /* Align it to 8 bytes */ 190 __u8 pad[5]; 191 __u64 serror_esr; 192 } exception; 193 __u32 reserved[12]; 194}; 195 196struct kvm_arm_copy_mte_tags { 197 __u64 guest_ipa; 198 __u64 length; 199 void __user *addr; 200 __u64 flags; 201 __u64 reserved[2]; 202}; 203 204/* 205 * Counter/Timer offset structure. Describe the virtual/physical offset. 206 * To be used with KVM_ARM_SET_COUNTER_OFFSET. 207 */ 208struct kvm_arm_counter_offset { 209 __u64 counter_offset; 210 __u64 reserved; 211}; 212 213#define KVM_ARM_TAGS_TO_GUEST 0 214#define KVM_ARM_TAGS_FROM_GUEST 1 215 216/* If you need to interpret the index values, here is the key: */ 217#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 218#define KVM_REG_ARM_COPROC_SHIFT 16 219 220/* Normal registers are mapped as coprocessor 16. */ 221#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 222#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 223 224/* Some registers need more space to represent values. */ 225#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 226#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 227#define KVM_REG_ARM_DEMUX_ID_SHIFT 8 228#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 229#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 230#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 231 232/* AArch64 system registers */ 233#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 234#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 235#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 236#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 237#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 238#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 239#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 240#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 241#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 242#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 243#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 244 245#define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 246 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 247 KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 248 249#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 250 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 251 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 252 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 253 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 254 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 255 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 256 257#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 258 259/* Physical Timer EL0 Registers */ 260#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 261#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 262#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 263 264/* 265 * EL0 Virtual Timer Registers 266 * 267 * WARNING: 268 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined 269 * with the appropriate register encodings. Their values have been 270 * accidentally swapped. As this is set API, the definitions here 271 * must be used, rather than ones derived from the encodings. 272 */ 273#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 274#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 275#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 276 277/* KVM-as-firmware specific pseudo-registers */ 278#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 279#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 280 KVM_REG_ARM_FW | ((r) & 0xffff)) 281#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 282#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) 283#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 284#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 285#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 286 287/* 288 * Only two states can be presented by the host kernel: 289 * - NOT_REQUIRED: the guest doesn't need to do anything 290 * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available) 291 * 292 * All the other values are deprecated. The host still accepts all 293 * values (they are ABI), but will narrow them to the above two. 294 */ 295#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) 296#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 297#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 298#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 299#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 300#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) 301 302#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3) 303#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0 304#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1 305#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2 306 307/* SVE registers */ 308#define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) 309 310/* Z- and P-regs occupy blocks at the following offsets within this range: */ 311#define KVM_REG_ARM64_SVE_ZREG_BASE 0 312#define KVM_REG_ARM64_SVE_PREG_BASE 0x400 313#define KVM_REG_ARM64_SVE_FFR_BASE 0x600 314 315#define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS 316#define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS 317 318#define KVM_ARM64_SVE_MAX_SLICES 32 319 320#define KVM_REG_ARM64_SVE_ZREG(n, i) \ 321 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \ 322 KVM_REG_SIZE_U2048 | \ 323 (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \ 324 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 325 326#define KVM_REG_ARM64_SVE_PREG(n, i) \ 327 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \ 328 KVM_REG_SIZE_U256 | \ 329 (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \ 330 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 331 332#define KVM_REG_ARM64_SVE_FFR(i) \ 333 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \ 334 KVM_REG_SIZE_U256 | \ 335 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 336 337/* 338 * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and 339 * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness- 340 * invariant layout which differs from the layout used for the FPSIMD 341 * V-registers on big-endian systems: see sigcontext.h for more explanation. 342 */ 343 344#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN 345#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX 346 347/* Vector lengths pseudo-register: */ 348#define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \ 349 KVM_REG_SIZE_U512 | 0xffff) 350#define KVM_ARM64_SVE_VLS_WORDS \ 351 ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) 352 353/* Bitmap feature firmware registers */ 354#define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT) 355#define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 356 KVM_REG_ARM_FW_FEAT_BMAP | \ 357 ((r) & 0xffff)) 358 359#define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0) 360 361enum { 362 KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0, 363#ifdef __KERNEL__ 364 KVM_REG_ARM_STD_BMAP_BIT_COUNT, 365#endif 366}; 367 368#define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1) 369 370enum { 371 KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0, 372#ifdef __KERNEL__ 373 KVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT, 374#endif 375}; 376 377#define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2) 378 379enum { 380 KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0, 381 KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1, 382#ifdef __KERNEL__ 383 KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT, 384#endif 385}; 386 387/* Device Control API on vm fd */ 388#define KVM_ARM_VM_SMCCC_CTRL 0 389#define KVM_ARM_VM_SMCCC_FILTER 0 390 391/* Device Control API: ARM VGIC */ 392#define KVM_DEV_ARM_VGIC_GRP_ADDR 0 393#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 394#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 395#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 396#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 397#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 398#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 399 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 400#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 401#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 402#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 403#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 404#define KVM_DEV_ARM_VGIC_GRP_CTRL 4 405#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 406#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 407#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 408#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 409#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 410#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 411 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 412#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 413#define VGIC_LEVEL_INFO_LINE_LEVEL 0 414 415#define KVM_DEV_ARM_VGIC_CTRL_INIT 0 416#define KVM_DEV_ARM_ITS_SAVE_TABLES 1 417#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 418#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 419#define KVM_DEV_ARM_ITS_CTRL_RESET 4 420 421/* Device Control API on vcpu fd */ 422#define KVM_ARM_VCPU_PMU_V3_CTRL 0 423#define KVM_ARM_VCPU_PMU_V3_IRQ 0 424#define KVM_ARM_VCPU_PMU_V3_INIT 1 425#define KVM_ARM_VCPU_PMU_V3_FILTER 2 426#define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 427#define KVM_ARM_VCPU_TIMER_CTRL 1 428#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 429#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 430#define KVM_ARM_VCPU_TIMER_IRQ_HVTIMER 2 431#define KVM_ARM_VCPU_TIMER_IRQ_HPTIMER 3 432#define KVM_ARM_VCPU_PVTIME_CTRL 2 433#define KVM_ARM_VCPU_PVTIME_IPA 0 434 435/* KVM_IRQ_LINE irq field index values */ 436#define KVM_ARM_IRQ_VCPU2_SHIFT 28 437#define KVM_ARM_IRQ_VCPU2_MASK 0xf 438#define KVM_ARM_IRQ_TYPE_SHIFT 24 439#define KVM_ARM_IRQ_TYPE_MASK 0xf 440#define KVM_ARM_IRQ_VCPU_SHIFT 16 441#define KVM_ARM_IRQ_VCPU_MASK 0xff 442#define KVM_ARM_IRQ_NUM_SHIFT 0 443#define KVM_ARM_IRQ_NUM_MASK 0xffff 444 445/* irq_type field */ 446#define KVM_ARM_IRQ_TYPE_CPU 0 447#define KVM_ARM_IRQ_TYPE_SPI 1 448#define KVM_ARM_IRQ_TYPE_PPI 2 449 450/* out-of-kernel GIC cpu interrupt injection irq_number field */ 451#define KVM_ARM_IRQ_CPU_IRQ 0 452#define KVM_ARM_IRQ_CPU_FIQ 1 453 454/* 455 * This used to hold the highest supported SPI, but it is now obsolete 456 * and only here to provide source code level compatibility with older 457 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 458 */ 459#ifndef __KERNEL__ 460#define KVM_ARM_IRQ_GIC_MAX 127 461#endif 462 463/* One single KVM irqchip, ie. the VGIC */ 464#define KVM_NR_IRQCHIPS 1 465 466/* PSCI interface */ 467#define KVM_PSCI_FN_BASE 0x95c1ba5e 468#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 469 470#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 471#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 472#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 473#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 474 475#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 476#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 477#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 478#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 479 480/* arm64-specific kvm_run::system_event flags */ 481/* 482 * Reset caused by a PSCI v1.1 SYSTEM_RESET2 call. 483 * Valid only when the system event has a type of KVM_SYSTEM_EVENT_RESET. 484 */ 485#define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0) 486 487/* run->fail_entry.hardware_entry_failure_reason codes. */ 488#define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0) 489 490enum kvm_smccc_filter_action { 491 KVM_SMCCC_FILTER_HANDLE = 0, 492 KVM_SMCCC_FILTER_DENY, 493 KVM_SMCCC_FILTER_FWD_TO_USER, 494 495#ifdef __KERNEL__ 496 NR_SMCCC_FILTER_ACTIONS 497#endif 498}; 499 500struct kvm_smccc_filter { 501 __u32 base; 502 __u32 nr_functions; 503 __u8 action; 504 __u8 pad[15]; 505}; 506 507/* arm64-specific KVM_EXIT_HYPERCALL flags */ 508#define KVM_HYPERCALL_EXIT_SMC (1U << 0) 509#define KVM_HYPERCALL_EXIT_16BIT (1U << 1) 510 511/* 512 * Get feature ID registers userspace writable mask. 513 * 514 * From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model 515 * Feature Register 2"): 516 * 517 * "The Feature ID space is defined as the System register space in 518 * AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, 519 * op2=={0-7}." 520 * 521 * This covers all currently known R/O registers that indicate 522 * anything useful feature wise, including the ID registers. 523 * 524 * If we ever need to introduce a new range, it will be described as 525 * such in the range field. 526 */ 527#define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \ 528 ({ \ 529 __u64 __op1 = (op1) & 3; \ 530 __op1 -= (__op1 == 3); \ 531 (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ 532 }) 533 534#define KVM_ARM_FEATURE_ID_RANGE 0 535#define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8) 536 537struct reg_mask_range { 538 __u64 addr; /* Pointer to mask array */ 539 __u32 range; /* Requested range */ 540 __u32 reserved[13]; 541}; 542 543#endif 544 545#endif /* __ARM_KVM_H__ */ 546