1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2// 3// Copyright(c) 2020 Intel Corporation. All rights reserved. 4// 5// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 6// 7 8/* 9 * Hardware interface for audio DSP on Tigerlake. 10 */ 11 12#include <sound/sof/ext_manifest4.h> 13#include "../ipc4-priv.h" 14#include "../ops.h" 15#include "hda.h" 16#include "hda-ipc.h" 17#include "../sof-audio.h" 18 19static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { 20 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, 21 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, 22 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, 23}; 24 25static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) 26{ 27 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 28 29 /* power up primary core if not already powered up and return */ 30 if (core == SOF_DSP_PRIMARY_CORE) 31 return hda_dsp_enable_core(sdev, BIT(core)); 32 33 if (pm_ops->set_core_state) 34 return pm_ops->set_core_state(sdev, core, true); 35 36 return 0; 37} 38 39static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) 40{ 41 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 42 int ret; 43 44 if (pm_ops->set_core_state) { 45 ret = pm_ops->set_core_state(sdev, core, false); 46 if (ret < 0) 47 return ret; 48 } 49 50 /* power down primary core and return */ 51 if (core == SOF_DSP_PRIMARY_CORE) 52 return hda_dsp_core_reset_power_down(sdev, BIT(core)); 53 54 return 0; 55} 56 57/* Tigerlake ops */ 58struct snd_sof_dsp_ops sof_tgl_ops; 59EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); 60 61int sof_tgl_ops_init(struct snd_sof_dev *sdev) 62{ 63 /* common defaults */ 64 memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); 65 66 /* probe/remove/shutdown */ 67 sof_tgl_ops.shutdown = hda_dsp_shutdown_dma_flush; 68 69 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_3) { 70 /* doorbell */ 71 sof_tgl_ops.irq_thread = cnl_ipc_irq_thread; 72 73 /* ipc */ 74 sof_tgl_ops.send_msg = cnl_ipc_send_msg; 75 76 /* debug */ 77 sof_tgl_ops.ipc_dump = cnl_ipc_dump; 78 79 sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc3; 80 } 81 82 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) { 83 struct sof_ipc4_fw_data *ipc4_data; 84 85 sdev->private = kzalloc(sizeof(*ipc4_data), GFP_KERNEL); 86 if (!sdev->private) 87 return -ENOMEM; 88 89 ipc4_data = sdev->private; 90 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; 91 92 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2; 93 94 ipc4_data->fw_context_save = true; 95 96 /* External library loading support */ 97 ipc4_data->load_library = hda_dsp_ipc4_load_library; 98 99 /* doorbell */ 100 sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread; 101 102 /* ipc */ 103 sof_tgl_ops.send_msg = cnl_ipc4_send_msg; 104 105 /* debug */ 106 sof_tgl_ops.ipc_dump = cnl_ipc4_dump; 107 sof_tgl_ops.dbg_dump = hda_ipc4_dsp_dump; 108 109 sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc4; 110 } 111 112 /* set DAI driver ops */ 113 hda_set_dai_drv_ops(sdev, &sof_tgl_ops); 114 115 /* debug */ 116 sof_tgl_ops.debug_map = tgl_dsp_debugfs; 117 sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs); 118 119 /* pre/post fw run */ 120 sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run; 121 122 /* firmware run */ 123 sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax; 124 125 /* dsp core get/put */ 126 sof_tgl_ops.core_get = tgl_dsp_core_get; 127 sof_tgl_ops.core_put = tgl_dsp_core_put; 128 129 return 0; 130}; 131EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); 132 133const struct sof_intel_dsp_desc tgl_chip_info = { 134 /* Tigerlake , Alderlake */ 135 .cores_num = 4, 136 .init_core_mask = 1, 137 .host_managed_cores_mask = BIT(0), 138 .ipc_req = CNL_DSP_REG_HIPCIDR, 139 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 140 .ipc_ack = CNL_DSP_REG_HIPCIDA, 141 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 142 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 143 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 144 .rom_init_timeout = 300, 145 .ssp_count = TGL_SSP_COUNT, 146 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 147 .sdw_shim_base = SDW_SHIM_BASE, 148 .sdw_alh_base = SDW_ALH_BASE, 149 .d0i3_offset = SOF_HDA_VS_D0I3C, 150 .read_sdw_lcount = hda_sdw_check_lcount_common, 151 .enable_sdw_irq = hda_common_enable_sdw_irq, 152 .check_sdw_irq = hda_common_check_sdw_irq, 153 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, 154 .check_ipc_irq = hda_dsp_check_ipc_irq, 155 .cl_init = cl_dsp_init, 156 .power_down_dsp = hda_power_down_dsp, 157 .disable_interrupts = hda_dsp_disable_interrupts, 158 .hw_ip_version = SOF_INTEL_CAVS_2_5, 159}; 160EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 161 162const struct sof_intel_dsp_desc tglh_chip_info = { 163 /* Tigerlake-H */ 164 .cores_num = 2, 165 .init_core_mask = 1, 166 .host_managed_cores_mask = BIT(0), 167 .ipc_req = CNL_DSP_REG_HIPCIDR, 168 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 169 .ipc_ack = CNL_DSP_REG_HIPCIDA, 170 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 171 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 172 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 173 .rom_init_timeout = 300, 174 .ssp_count = TGL_SSP_COUNT, 175 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 176 .sdw_shim_base = SDW_SHIM_BASE, 177 .sdw_alh_base = SDW_ALH_BASE, 178 .d0i3_offset = SOF_HDA_VS_D0I3C, 179 .read_sdw_lcount = hda_sdw_check_lcount_common, 180 .enable_sdw_irq = hda_common_enable_sdw_irq, 181 .check_sdw_irq = hda_common_check_sdw_irq, 182 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, 183 .check_ipc_irq = hda_dsp_check_ipc_irq, 184 .cl_init = cl_dsp_init, 185 .power_down_dsp = hda_power_down_dsp, 186 .disable_interrupts = hda_dsp_disable_interrupts, 187 .hw_ip_version = SOF_INTEL_CAVS_2_5, 188}; 189EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 190 191const struct sof_intel_dsp_desc ehl_chip_info = { 192 /* Elkhartlake */ 193 .cores_num = 4, 194 .init_core_mask = 1, 195 .host_managed_cores_mask = BIT(0), 196 .ipc_req = CNL_DSP_REG_HIPCIDR, 197 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 198 .ipc_ack = CNL_DSP_REG_HIPCIDA, 199 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 200 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 201 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 202 .rom_init_timeout = 300, 203 .ssp_count = TGL_SSP_COUNT, 204 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 205 .sdw_shim_base = SDW_SHIM_BASE, 206 .sdw_alh_base = SDW_ALH_BASE, 207 .d0i3_offset = SOF_HDA_VS_D0I3C, 208 .read_sdw_lcount = hda_sdw_check_lcount_common, 209 .enable_sdw_irq = hda_common_enable_sdw_irq, 210 .check_sdw_irq = hda_common_check_sdw_irq, 211 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, 212 .check_ipc_irq = hda_dsp_check_ipc_irq, 213 .cl_init = cl_dsp_init, 214 .power_down_dsp = hda_power_down_dsp, 215 .disable_interrupts = hda_dsp_disable_interrupts, 216 .hw_ip_version = SOF_INTEL_CAVS_2_5, 217}; 218EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 219 220const struct sof_intel_dsp_desc adls_chip_info = { 221 /* Alderlake-S */ 222 .cores_num = 2, 223 .init_core_mask = BIT(0), 224 .host_managed_cores_mask = BIT(0), 225 .ipc_req = CNL_DSP_REG_HIPCIDR, 226 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, 227 .ipc_ack = CNL_DSP_REG_HIPCIDA, 228 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, 229 .ipc_ctl = CNL_DSP_REG_HIPCCTL, 230 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, 231 .rom_init_timeout = 300, 232 .ssp_count = TGL_SSP_COUNT, 233 .ssp_base_offset = CNL_SSP_BASE_OFFSET, 234 .sdw_shim_base = SDW_SHIM_BASE, 235 .sdw_alh_base = SDW_ALH_BASE, 236 .d0i3_offset = SOF_HDA_VS_D0I3C, 237 .read_sdw_lcount = hda_sdw_check_lcount_common, 238 .enable_sdw_irq = hda_common_enable_sdw_irq, 239 .check_sdw_irq = hda_common_check_sdw_irq, 240 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common, 241 .check_ipc_irq = hda_dsp_check_ipc_irq, 242 .cl_init = cl_dsp_init, 243 .power_down_dsp = hda_power_down_dsp, 244 .disable_interrupts = hda_dsp_disable_interrupts, 245 .hw_ip_version = SOF_INTEL_CAVS_2_5, 246}; 247EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); 248