1// SPDX-License-Identifier: GPL-2.0 2// 3// Fifo-attached Serial Interface (FSI) support for SH7724 4// 5// Copyright (C) 2009 Renesas Solutions Corp. 6// Kuninori Morimoto <morimoto.kuninori@renesas.com> 7// 8// Based on ssi.c 9// Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> 10 11#include <linux/delay.h> 12#include <linux/dma-mapping.h> 13#include <linux/pm_runtime.h> 14#include <linux/io.h> 15#include <linux/of.h> 16#include <linux/scatterlist.h> 17#include <linux/sh_dma.h> 18#include <linux/slab.h> 19#include <linux/module.h> 20#include <linux/workqueue.h> 21#include <sound/soc.h> 22#include <sound/pcm_params.h> 23#include <sound/sh_fsi.h> 24 25/* PortA/PortB register */ 26#define REG_DO_FMT 0x0000 27#define REG_DOFF_CTL 0x0004 28#define REG_DOFF_ST 0x0008 29#define REG_DI_FMT 0x000C 30#define REG_DIFF_CTL 0x0010 31#define REG_DIFF_ST 0x0014 32#define REG_CKG1 0x0018 33#define REG_CKG2 0x001C 34#define REG_DIDT 0x0020 35#define REG_DODT 0x0024 36#define REG_MUTE_ST 0x0028 37#define REG_OUT_DMAC 0x002C 38#define REG_OUT_SEL 0x0030 39#define REG_IN_DMAC 0x0038 40 41/* master register */ 42#define MST_CLK_RST 0x0210 43#define MST_SOFT_RST 0x0214 44#define MST_FIFO_SZ 0x0218 45 46/* core register (depend on FSI version) */ 47#define A_MST_CTLR 0x0180 48#define B_MST_CTLR 0x01A0 49#define CPU_INT_ST 0x01F4 50#define CPU_IEMSK 0x01F8 51#define CPU_IMSK 0x01FC 52#define INT_ST 0x0200 53#define IEMSK 0x0204 54#define IMSK 0x0208 55 56/* DO_FMT */ 57/* DI_FMT */ 58#define CR_BWS_MASK (0x3 << 20) /* FSI2 */ 59#define CR_BWS_24 (0x0 << 20) /* FSI2 */ 60#define CR_BWS_16 (0x1 << 20) /* FSI2 */ 61#define CR_BWS_20 (0x2 << 20) /* FSI2 */ 62 63#define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ 64#define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ 65#define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ 66 67#define CR_MONO (0x0 << 4) 68#define CR_MONO_D (0x1 << 4) 69#define CR_PCM (0x2 << 4) 70#define CR_I2S (0x3 << 4) 71#define CR_TDM (0x4 << 4) 72#define CR_TDM_D (0x5 << 4) 73 74/* OUT_DMAC */ 75/* IN_DMAC */ 76#define VDMD_MASK (0x3 << 4) 77#define VDMD_FRONT (0x0 << 4) /* Package in front */ 78#define VDMD_BACK (0x1 << 4) /* Package in back */ 79#define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ 80 81#define DMA_ON (0x1 << 0) 82 83/* DOFF_CTL */ 84/* DIFF_CTL */ 85#define IRQ_HALF 0x00100000 86#define FIFO_CLR 0x00000001 87 88/* DOFF_ST */ 89#define ERR_OVER 0x00000010 90#define ERR_UNDER 0x00000001 91#define ST_ERR (ERR_OVER | ERR_UNDER) 92 93/* CKG1 */ 94#define ACKMD_MASK 0x00007000 95#define BPFMD_MASK 0x00000700 96#define DIMD (1 << 4) 97#define DOMD (1 << 0) 98 99/* A/B MST_CTLR */ 100#define BP (1 << 4) /* Fix the signal of Biphase output */ 101#define SE (1 << 0) /* Fix the master clock */ 102 103/* CLK_RST */ 104#define CRB (1 << 4) 105#define CRA (1 << 0) 106 107/* IO SHIFT / MACRO */ 108#define BI_SHIFT 12 109#define BO_SHIFT 8 110#define AI_SHIFT 4 111#define AO_SHIFT 0 112#define AB_IO(param, shift) (param << shift) 113 114/* SOFT_RST */ 115#define PBSR (1 << 12) /* Port B Software Reset */ 116#define PASR (1 << 8) /* Port A Software Reset */ 117#define IR (1 << 4) /* Interrupt Reset */ 118#define FSISR (1 << 0) /* Software Reset */ 119 120/* OUT_SEL (FSI2) */ 121#define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ 122 /* 1: Biphase and serial */ 123 124/* FIFO_SZ */ 125#define FIFO_SZ_MASK 0x7 126 127#define FSI_RATES SNDRV_PCM_RATE_8000_96000 128 129#define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) 130 131/* 132 * bus options 133 * 134 * 0x000000BA 135 * 136 * A : sample widtht 16bit setting 137 * B : sample widtht 24bit setting 138 */ 139 140#define SHIFT_16DATA 0 141#define SHIFT_24DATA 4 142 143#define PACKAGE_24BITBUS_BACK 0 144#define PACKAGE_24BITBUS_FRONT 1 145#define PACKAGE_16BITBUS_STREAM 2 146 147#define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) 148#define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) 149 150/* 151 * FSI driver use below type name for variable 152 * 153 * xxx_num : number of data 154 * xxx_pos : position of data 155 * xxx_capa : capacity of data 156 */ 157 158/* 159 * period/frame/sample image 160 * 161 * ex) PCM (2ch) 162 * 163 * period pos period pos 164 * [n] [n + 1] 165 * |<-------------------- period--------------------->| 166 * ==|============================================ ... =|== 167 * | | 168 * ||<----- frame ----->|<------ frame ----->| ... | 169 * |+--------------------+--------------------+- ... | 170 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | 171 * |+--------------------+--------------------+- ... | 172 * ==|============================================ ... =|== 173 */ 174 175/* 176 * FSI FIFO image 177 * 178 * | | 179 * | | 180 * | [ sample ] | 181 * | [ sample ] | 182 * | [ sample ] | 183 * | [ sample ] | 184 * --> go to codecs 185 */ 186 187/* 188 * FSI clock 189 * 190 * FSIxCLK [CPG] (ick) -------> | 191 * |-> FSI_DIV (div)-> FSI2 192 * FSIxCK [external] (xck) ---> | 193 */ 194 195/* 196 * struct 197 */ 198 199struct fsi_stream_handler; 200struct fsi_stream { 201 202 /* 203 * these are initialized by fsi_stream_init() 204 */ 205 struct snd_pcm_substream *substream; 206 int fifo_sample_capa; /* sample capacity of FSI FIFO */ 207 int buff_sample_capa; /* sample capacity of ALSA buffer */ 208 int buff_sample_pos; /* sample position of ALSA buffer */ 209 int period_samples; /* sample number / 1 period */ 210 int period_pos; /* current period position */ 211 int sample_width; /* sample width */ 212 int uerr_num; 213 int oerr_num; 214 215 /* 216 * bus options 217 */ 218 u32 bus_option; 219 220 /* 221 * these are initialized by fsi_handler_init() 222 */ 223 struct fsi_stream_handler *handler; 224 struct fsi_priv *priv; 225 226 /* 227 * these are for DMAEngine 228 */ 229 struct dma_chan *chan; 230 int dma_id; 231}; 232 233struct fsi_clk { 234 /* see [FSI clock] */ 235 struct clk *own; 236 struct clk *xck; 237 struct clk *ick; 238 struct clk *div; 239 int (*set_rate)(struct device *dev, 240 struct fsi_priv *fsi); 241 242 unsigned long rate; 243 unsigned int count; 244}; 245 246struct fsi_priv { 247 void __iomem *base; 248 phys_addr_t phys; 249 struct fsi_master *master; 250 251 struct fsi_stream playback; 252 struct fsi_stream capture; 253 254 struct fsi_clk clock; 255 256 u32 fmt; 257 258 int chan_num:16; 259 unsigned int clk_master:1; 260 unsigned int clk_cpg:1; 261 unsigned int spdif:1; 262 unsigned int enable_stream:1; 263 unsigned int bit_clk_inv:1; 264 unsigned int lr_clk_inv:1; 265}; 266 267struct fsi_stream_handler { 268 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); 269 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); 270 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); 271 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); 272 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); 273 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, 274 int enable); 275}; 276#define fsi_stream_handler_call(io, func, args...) \ 277 (!(io) ? -ENODEV : \ 278 !((io)->handler->func) ? 0 : \ 279 (io)->handler->func(args)) 280 281struct fsi_core { 282 int ver; 283 284 u32 int_st; 285 u32 iemsk; 286 u32 imsk; 287 u32 a_mclk; 288 u32 b_mclk; 289}; 290 291struct fsi_master { 292 void __iomem *base; 293 struct fsi_priv fsia; 294 struct fsi_priv fsib; 295 const struct fsi_core *core; 296 spinlock_t lock; 297}; 298 299static inline int fsi_stream_is_play(struct fsi_priv *fsi, 300 struct fsi_stream *io) 301{ 302 return &fsi->playback == io; 303} 304 305 306/* 307 * basic read write function 308 */ 309 310static void __fsi_reg_write(u32 __iomem *reg, u32 data) 311{ 312 /* valid data area is 24bit */ 313 data &= 0x00ffffff; 314 315 __raw_writel(data, reg); 316} 317 318static u32 __fsi_reg_read(u32 __iomem *reg) 319{ 320 return __raw_readl(reg); 321} 322 323static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) 324{ 325 u32 val = __fsi_reg_read(reg); 326 327 val &= ~mask; 328 val |= data & mask; 329 330 __fsi_reg_write(reg, val); 331} 332 333#define fsi_reg_write(p, r, d)\ 334 __fsi_reg_write((p->base + REG_##r), d) 335 336#define fsi_reg_read(p, r)\ 337 __fsi_reg_read((p->base + REG_##r)) 338 339#define fsi_reg_mask_set(p, r, m, d)\ 340 __fsi_reg_mask_set((p->base + REG_##r), m, d) 341 342#define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) 343#define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) 344static u32 _fsi_master_read(struct fsi_master *master, u32 reg) 345{ 346 u32 ret; 347 unsigned long flags; 348 349 spin_lock_irqsave(&master->lock, flags); 350 ret = __fsi_reg_read(master->base + reg); 351 spin_unlock_irqrestore(&master->lock, flags); 352 353 return ret; 354} 355 356#define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) 357#define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) 358static void _fsi_master_mask_set(struct fsi_master *master, 359 u32 reg, u32 mask, u32 data) 360{ 361 unsigned long flags; 362 363 spin_lock_irqsave(&master->lock, flags); 364 __fsi_reg_mask_set(master->base + reg, mask, data); 365 spin_unlock_irqrestore(&master->lock, flags); 366} 367 368/* 369 * basic function 370 */ 371static int fsi_version(struct fsi_master *master) 372{ 373 return master->core->ver; 374} 375 376static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) 377{ 378 return fsi->master; 379} 380 381static int fsi_is_clk_master(struct fsi_priv *fsi) 382{ 383 return fsi->clk_master; 384} 385 386static int fsi_is_port_a(struct fsi_priv *fsi) 387{ 388 return fsi->master->base == fsi->base; 389} 390 391static int fsi_is_spdif(struct fsi_priv *fsi) 392{ 393 return fsi->spdif; 394} 395 396static int fsi_is_enable_stream(struct fsi_priv *fsi) 397{ 398 return fsi->enable_stream; 399} 400 401static int fsi_is_play(struct snd_pcm_substream *substream) 402{ 403 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 404} 405 406static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) 407{ 408 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 409 410 return snd_soc_rtd_to_cpu(rtd, 0); 411} 412 413static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) 414{ 415 struct fsi_master *master = snd_soc_dai_get_drvdata(dai); 416 417 if (dai->id == 0) 418 return &master->fsia; 419 else 420 return &master->fsib; 421} 422 423static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) 424{ 425 return fsi_get_priv_frm_dai(fsi_get_dai(substream)); 426} 427 428static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) 429{ 430 int is_play = fsi_stream_is_play(fsi, io); 431 int is_porta = fsi_is_port_a(fsi); 432 u32 shift; 433 434 if (is_porta) 435 shift = is_play ? AO_SHIFT : AI_SHIFT; 436 else 437 shift = is_play ? BO_SHIFT : BI_SHIFT; 438 439 return shift; 440} 441 442static int fsi_frame2sample(struct fsi_priv *fsi, int frames) 443{ 444 return frames * fsi->chan_num; 445} 446 447static int fsi_sample2frame(struct fsi_priv *fsi, int samples) 448{ 449 return samples / fsi->chan_num; 450} 451 452static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, 453 struct fsi_stream *io) 454{ 455 int is_play = fsi_stream_is_play(fsi, io); 456 u32 status; 457 int frames; 458 459 status = is_play ? 460 fsi_reg_read(fsi, DOFF_ST) : 461 fsi_reg_read(fsi, DIFF_ST); 462 463 frames = 0x1ff & (status >> 8); 464 465 return fsi_frame2sample(fsi, frames); 466} 467 468static void fsi_count_fifo_err(struct fsi_priv *fsi) 469{ 470 u32 ostatus = fsi_reg_read(fsi, DOFF_ST); 471 u32 istatus = fsi_reg_read(fsi, DIFF_ST); 472 473 if (ostatus & ERR_OVER) 474 fsi->playback.oerr_num++; 475 476 if (ostatus & ERR_UNDER) 477 fsi->playback.uerr_num++; 478 479 if (istatus & ERR_OVER) 480 fsi->capture.oerr_num++; 481 482 if (istatus & ERR_UNDER) 483 fsi->capture.uerr_num++; 484 485 fsi_reg_write(fsi, DOFF_ST, 0); 486 fsi_reg_write(fsi, DIFF_ST, 0); 487} 488 489/* 490 * fsi_stream_xx() function 491 */ 492static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, 493 struct snd_pcm_substream *substream) 494{ 495 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; 496} 497 498static int fsi_stream_is_working(struct fsi_priv *fsi, 499 struct fsi_stream *io) 500{ 501 struct fsi_master *master = fsi_get_master(fsi); 502 unsigned long flags; 503 int ret; 504 505 spin_lock_irqsave(&master->lock, flags); 506 ret = !!(io->substream && io->substream->runtime); 507 spin_unlock_irqrestore(&master->lock, flags); 508 509 return ret; 510} 511 512static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) 513{ 514 return io->priv; 515} 516 517static void fsi_stream_init(struct fsi_priv *fsi, 518 struct fsi_stream *io, 519 struct snd_pcm_substream *substream) 520{ 521 struct snd_pcm_runtime *runtime = substream->runtime; 522 struct fsi_master *master = fsi_get_master(fsi); 523 unsigned long flags; 524 525 spin_lock_irqsave(&master->lock, flags); 526 io->substream = substream; 527 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); 528 io->buff_sample_pos = 0; 529 io->period_samples = fsi_frame2sample(fsi, runtime->period_size); 530 io->period_pos = 0; 531 io->sample_width = samples_to_bytes(runtime, 1); 532 io->bus_option = 0; 533 io->oerr_num = -1; /* ignore 1st err */ 534 io->uerr_num = -1; /* ignore 1st err */ 535 fsi_stream_handler_call(io, init, fsi, io); 536 spin_unlock_irqrestore(&master->lock, flags); 537} 538 539static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) 540{ 541 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 542 struct fsi_master *master = fsi_get_master(fsi); 543 unsigned long flags; 544 545 spin_lock_irqsave(&master->lock, flags); 546 547 if (io->oerr_num > 0) 548 dev_err(dai->dev, "over_run = %d\n", io->oerr_num); 549 550 if (io->uerr_num > 0) 551 dev_err(dai->dev, "under_run = %d\n", io->uerr_num); 552 553 fsi_stream_handler_call(io, quit, fsi, io); 554 io->substream = NULL; 555 io->buff_sample_capa = 0; 556 io->buff_sample_pos = 0; 557 io->period_samples = 0; 558 io->period_pos = 0; 559 io->sample_width = 0; 560 io->bus_option = 0; 561 io->oerr_num = 0; 562 io->uerr_num = 0; 563 spin_unlock_irqrestore(&master->lock, flags); 564} 565 566static int fsi_stream_transfer(struct fsi_stream *io) 567{ 568 struct fsi_priv *fsi = fsi_stream_to_priv(io); 569 if (!fsi) 570 return -EIO; 571 572 return fsi_stream_handler_call(io, transfer, fsi, io); 573} 574 575#define fsi_stream_start(fsi, io)\ 576 fsi_stream_handler_call(io, start_stop, fsi, io, 1) 577 578#define fsi_stream_stop(fsi, io)\ 579 fsi_stream_handler_call(io, start_stop, fsi, io, 0) 580 581static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) 582{ 583 struct fsi_stream *io; 584 int ret1, ret2; 585 586 io = &fsi->playback; 587 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); 588 589 io = &fsi->capture; 590 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); 591 592 if (ret1 < 0) 593 return ret1; 594 if (ret2 < 0) 595 return ret2; 596 597 return 0; 598} 599 600static int fsi_stream_remove(struct fsi_priv *fsi) 601{ 602 struct fsi_stream *io; 603 int ret1, ret2; 604 605 io = &fsi->playback; 606 ret1 = fsi_stream_handler_call(io, remove, fsi, io); 607 608 io = &fsi->capture; 609 ret2 = fsi_stream_handler_call(io, remove, fsi, io); 610 611 if (ret1 < 0) 612 return ret1; 613 if (ret2 < 0) 614 return ret2; 615 616 return 0; 617} 618 619/* 620 * format/bus/dma setting 621 */ 622static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, 623 u32 bus, struct device *dev) 624{ 625 struct fsi_master *master = fsi_get_master(fsi); 626 int is_play = fsi_stream_is_play(fsi, io); 627 u32 fmt = fsi->fmt; 628 629 if (fsi_version(master) >= 2) { 630 u32 dma = 0; 631 632 /* 633 * FSI2 needs DMA/Bus setting 634 */ 635 switch (bus) { 636 case PACKAGE_24BITBUS_FRONT: 637 fmt |= CR_BWS_24; 638 dma |= VDMD_FRONT; 639 dev_dbg(dev, "24bit bus / package in front\n"); 640 break; 641 case PACKAGE_16BITBUS_STREAM: 642 fmt |= CR_BWS_16; 643 dma |= VDMD_STREAM; 644 dev_dbg(dev, "16bit bus / stream mode\n"); 645 break; 646 case PACKAGE_24BITBUS_BACK: 647 default: 648 fmt |= CR_BWS_24; 649 dma |= VDMD_BACK; 650 dev_dbg(dev, "24bit bus / package in back\n"); 651 break; 652 } 653 654 if (is_play) 655 fsi_reg_write(fsi, OUT_DMAC, dma); 656 else 657 fsi_reg_write(fsi, IN_DMAC, dma); 658 } 659 660 if (is_play) 661 fsi_reg_write(fsi, DO_FMT, fmt); 662 else 663 fsi_reg_write(fsi, DI_FMT, fmt); 664} 665 666/* 667 * irq function 668 */ 669 670static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) 671{ 672 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 673 struct fsi_master *master = fsi_get_master(fsi); 674 675 fsi_core_mask_set(master, imsk, data, data); 676 fsi_core_mask_set(master, iemsk, data, data); 677} 678 679static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) 680{ 681 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 682 struct fsi_master *master = fsi_get_master(fsi); 683 684 fsi_core_mask_set(master, imsk, data, 0); 685 fsi_core_mask_set(master, iemsk, data, 0); 686} 687 688static u32 fsi_irq_get_status(struct fsi_master *master) 689{ 690 return fsi_core_read(master, int_st); 691} 692 693static void fsi_irq_clear_status(struct fsi_priv *fsi) 694{ 695 u32 data = 0; 696 struct fsi_master *master = fsi_get_master(fsi); 697 698 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); 699 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); 700 701 /* clear interrupt factor */ 702 fsi_core_mask_set(master, int_st, data, 0); 703} 704 705/* 706 * SPDIF master clock function 707 * 708 * These functions are used later FSI2 709 */ 710static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) 711{ 712 struct fsi_master *master = fsi_get_master(fsi); 713 u32 mask, val; 714 715 mask = BP | SE; 716 val = enable ? mask : 0; 717 718 fsi_is_port_a(fsi) ? 719 fsi_core_mask_set(master, a_mclk, mask, val) : 720 fsi_core_mask_set(master, b_mclk, mask, val); 721} 722 723/* 724 * clock function 725 */ 726static int fsi_clk_init(struct device *dev, 727 struct fsi_priv *fsi, 728 int xck, 729 int ick, 730 int div, 731 int (*set_rate)(struct device *dev, 732 struct fsi_priv *fsi)) 733{ 734 struct fsi_clk *clock = &fsi->clock; 735 int is_porta = fsi_is_port_a(fsi); 736 737 clock->xck = NULL; 738 clock->ick = NULL; 739 clock->div = NULL; 740 clock->rate = 0; 741 clock->count = 0; 742 clock->set_rate = set_rate; 743 744 clock->own = devm_clk_get(dev, NULL); 745 if (IS_ERR(clock->own)) 746 return -EINVAL; 747 748 /* external clock */ 749 if (xck) { 750 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb"); 751 if (IS_ERR(clock->xck)) { 752 dev_err(dev, "can't get xck clock\n"); 753 return -EINVAL; 754 } 755 if (clock->xck == clock->own) { 756 dev_err(dev, "cpu doesn't support xck clock\n"); 757 return -EINVAL; 758 } 759 } 760 761 /* FSIACLK/FSIBCLK */ 762 if (ick) { 763 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb"); 764 if (IS_ERR(clock->ick)) { 765 dev_err(dev, "can't get ick clock\n"); 766 return -EINVAL; 767 } 768 if (clock->ick == clock->own) { 769 dev_err(dev, "cpu doesn't support ick clock\n"); 770 return -EINVAL; 771 } 772 } 773 774 /* FSI-DIV */ 775 if (div) { 776 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb"); 777 if (IS_ERR(clock->div)) { 778 dev_err(dev, "can't get div clock\n"); 779 return -EINVAL; 780 } 781 if (clock->div == clock->own) { 782 dev_err(dev, "cpu doesn't support div clock\n"); 783 return -EINVAL; 784 } 785 } 786 787 return 0; 788} 789 790#define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) 791static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) 792{ 793 fsi->clock.rate = rate; 794} 795 796static int fsi_clk_is_valid(struct fsi_priv *fsi) 797{ 798 return fsi->clock.set_rate && 799 fsi->clock.rate; 800} 801 802static int fsi_clk_enable(struct device *dev, 803 struct fsi_priv *fsi) 804{ 805 struct fsi_clk *clock = &fsi->clock; 806 int ret = -EINVAL; 807 808 if (!fsi_clk_is_valid(fsi)) 809 return ret; 810 811 if (0 == clock->count) { 812 ret = clock->set_rate(dev, fsi); 813 if (ret < 0) { 814 fsi_clk_invalid(fsi); 815 return ret; 816 } 817 818 ret = clk_enable(clock->xck); 819 if (ret) 820 goto err; 821 ret = clk_enable(clock->ick); 822 if (ret) 823 goto disable_xck; 824 ret = clk_enable(clock->div); 825 if (ret) 826 goto disable_ick; 827 828 clock->count++; 829 } 830 831 return ret; 832 833disable_ick: 834 clk_disable(clock->ick); 835disable_xck: 836 clk_disable(clock->xck); 837err: 838 return ret; 839} 840 841static int fsi_clk_disable(struct device *dev, 842 struct fsi_priv *fsi) 843{ 844 struct fsi_clk *clock = &fsi->clock; 845 846 if (!fsi_clk_is_valid(fsi)) 847 return -EINVAL; 848 849 if (1 == clock->count--) { 850 clk_disable(clock->xck); 851 clk_disable(clock->ick); 852 clk_disable(clock->div); 853 } 854 855 return 0; 856} 857 858static int fsi_clk_set_ackbpf(struct device *dev, 859 struct fsi_priv *fsi, 860 int ackmd, int bpfmd) 861{ 862 u32 data = 0; 863 864 /* check ackmd/bpfmd relationship */ 865 if (bpfmd > ackmd) { 866 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd); 867 return -EINVAL; 868 } 869 870 /* ACKMD */ 871 switch (ackmd) { 872 case 512: 873 data |= (0x0 << 12); 874 break; 875 case 256: 876 data |= (0x1 << 12); 877 break; 878 case 128: 879 data |= (0x2 << 12); 880 break; 881 case 64: 882 data |= (0x3 << 12); 883 break; 884 case 32: 885 data |= (0x4 << 12); 886 break; 887 default: 888 dev_err(dev, "unsupported ackmd (%d)\n", ackmd); 889 return -EINVAL; 890 } 891 892 /* BPFMD */ 893 switch (bpfmd) { 894 case 32: 895 data |= (0x0 << 8); 896 break; 897 case 64: 898 data |= (0x1 << 8); 899 break; 900 case 128: 901 data |= (0x2 << 8); 902 break; 903 case 256: 904 data |= (0x3 << 8); 905 break; 906 case 512: 907 data |= (0x4 << 8); 908 break; 909 case 16: 910 data |= (0x7 << 8); 911 break; 912 default: 913 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd); 914 return -EINVAL; 915 } 916 917 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd); 918 919 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); 920 udelay(10); 921 922 return 0; 923} 924 925static int fsi_clk_set_rate_external(struct device *dev, 926 struct fsi_priv *fsi) 927{ 928 struct clk *xck = fsi->clock.xck; 929 struct clk *ick = fsi->clock.ick; 930 unsigned long rate = fsi->clock.rate; 931 unsigned long xrate; 932 int ackmd, bpfmd; 933 int ret = 0; 934 935 /* check clock rate */ 936 xrate = clk_get_rate(xck); 937 if (xrate % rate) { 938 dev_err(dev, "unsupported clock rate\n"); 939 return -EINVAL; 940 } 941 942 clk_set_parent(ick, xck); 943 clk_set_rate(ick, xrate); 944 945 bpfmd = fsi->chan_num * 32; 946 ackmd = xrate / rate; 947 948 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate); 949 950 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 951 if (ret < 0) 952 dev_err(dev, "%s failed", __func__); 953 954 return ret; 955} 956 957static int fsi_clk_set_rate_cpg(struct device *dev, 958 struct fsi_priv *fsi) 959{ 960 struct clk *ick = fsi->clock.ick; 961 struct clk *div = fsi->clock.div; 962 unsigned long rate = fsi->clock.rate; 963 unsigned long target = 0; /* 12288000 or 11289600 */ 964 unsigned long actual, cout; 965 unsigned long diff, min; 966 unsigned long best_cout, best_act; 967 int adj; 968 int ackmd, bpfmd; 969 int ret = -EINVAL; 970 971 if (!(12288000 % rate)) 972 target = 12288000; 973 if (!(11289600 % rate)) 974 target = 11289600; 975 if (!target) { 976 dev_err(dev, "unsupported rate\n"); 977 return ret; 978 } 979 980 bpfmd = fsi->chan_num * 32; 981 ackmd = target / rate; 982 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 983 if (ret < 0) { 984 dev_err(dev, "%s failed", __func__); 985 return ret; 986 } 987 988 /* 989 * The clock flow is 990 * 991 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec] 992 * 993 * But, it needs to find best match of CPG and FSI_DIV 994 * combination, since it is difficult to generate correct 995 * frequency of audio clock from ick clock only. 996 * Because ick is created from its parent clock. 997 * 998 * target = rate x [512/256/128/64]fs 999 * cout = round(target x adjustment) 1000 * actual = cout / adjustment (by FSI-DIV) ~= target 1001 * audio = actual 1002 */ 1003 min = ~0; 1004 best_cout = 0; 1005 best_act = 0; 1006 for (adj = 1; adj < 0xffff; adj++) { 1007 1008 cout = target * adj; 1009 if (cout > 100000000) /* max clock = 100MHz */ 1010 break; 1011 1012 /* cout/actual audio clock */ 1013 cout = clk_round_rate(ick, cout); 1014 actual = cout / adj; 1015 1016 /* find best frequency */ 1017 diff = abs(actual - target); 1018 if (diff < min) { 1019 min = diff; 1020 best_cout = cout; 1021 best_act = actual; 1022 } 1023 } 1024 1025 ret = clk_set_rate(ick, best_cout); 1026 if (ret < 0) { 1027 dev_err(dev, "ick clock failed\n"); 1028 return -EIO; 1029 } 1030 1031 ret = clk_set_rate(div, clk_round_rate(div, best_act)); 1032 if (ret < 0) { 1033 dev_err(dev, "div clock failed\n"); 1034 return -EIO; 1035 } 1036 1037 dev_dbg(dev, "ick/div = %ld/%ld\n", 1038 clk_get_rate(ick), clk_get_rate(div)); 1039 1040 return ret; 1041} 1042 1043static void fsi_pointer_update(struct fsi_stream *io, int size) 1044{ 1045 io->buff_sample_pos += size; 1046 1047 if (io->buff_sample_pos >= 1048 io->period_samples * (io->period_pos + 1)) { 1049 struct snd_pcm_substream *substream = io->substream; 1050 struct snd_pcm_runtime *runtime = substream->runtime; 1051 1052 io->period_pos++; 1053 1054 if (io->period_pos >= runtime->periods) { 1055 io->buff_sample_pos = 0; 1056 io->period_pos = 0; 1057 } 1058 1059 snd_pcm_period_elapsed(substream); 1060 } 1061} 1062 1063/* 1064 * pio data transfer handler 1065 */ 1066static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) 1067{ 1068 int i; 1069 1070 if (fsi_is_enable_stream(fsi)) { 1071 /* 1072 * stream mode 1073 * see 1074 * fsi_pio_push_init() 1075 */ 1076 u32 *buf = (u32 *)_buf; 1077 1078 for (i = 0; i < samples / 2; i++) 1079 fsi_reg_write(fsi, DODT, buf[i]); 1080 } else { 1081 /* normal mode */ 1082 u16 *buf = (u16 *)_buf; 1083 1084 for (i = 0; i < samples; i++) 1085 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); 1086 } 1087} 1088 1089static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) 1090{ 1091 u16 *buf = (u16 *)_buf; 1092 int i; 1093 1094 for (i = 0; i < samples; i++) 1095 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); 1096} 1097 1098static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) 1099{ 1100 u32 *buf = (u32 *)_buf; 1101 int i; 1102 1103 for (i = 0; i < samples; i++) 1104 fsi_reg_write(fsi, DODT, *(buf + i)); 1105} 1106 1107static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) 1108{ 1109 u32 *buf = (u32 *)_buf; 1110 int i; 1111 1112 for (i = 0; i < samples; i++) 1113 *(buf + i) = fsi_reg_read(fsi, DIDT); 1114} 1115 1116static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) 1117{ 1118 struct snd_pcm_runtime *runtime = io->substream->runtime; 1119 1120 return runtime->dma_area + 1121 samples_to_bytes(runtime, io->buff_sample_pos); 1122} 1123 1124static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, 1125 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), 1126 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), 1127 int samples) 1128{ 1129 u8 *buf; 1130 1131 if (!fsi_stream_is_working(fsi, io)) 1132 return -EINVAL; 1133 1134 buf = fsi_pio_get_area(fsi, io); 1135 1136 switch (io->sample_width) { 1137 case 2: 1138 run16(fsi, buf, samples); 1139 break; 1140 case 4: 1141 run32(fsi, buf, samples); 1142 break; 1143 default: 1144 return -EINVAL; 1145 } 1146 1147 fsi_pointer_update(io, samples); 1148 1149 return 0; 1150} 1151 1152static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) 1153{ 1154 int sample_residues; /* samples in FSI fifo */ 1155 int sample_space; /* ALSA free samples space */ 1156 int samples; 1157 1158 sample_residues = fsi_get_current_fifo_samples(fsi, io); 1159 sample_space = io->buff_sample_capa - io->buff_sample_pos; 1160 1161 samples = min(sample_residues, sample_space); 1162 1163 return fsi_pio_transfer(fsi, io, 1164 fsi_pio_pop16, 1165 fsi_pio_pop32, 1166 samples); 1167} 1168 1169static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) 1170{ 1171 int sample_residues; /* ALSA residue samples */ 1172 int sample_space; /* FSI fifo free samples space */ 1173 int samples; 1174 1175 sample_residues = io->buff_sample_capa - io->buff_sample_pos; 1176 sample_space = io->fifo_sample_capa - 1177 fsi_get_current_fifo_samples(fsi, io); 1178 1179 samples = min(sample_residues, sample_space); 1180 1181 return fsi_pio_transfer(fsi, io, 1182 fsi_pio_push16, 1183 fsi_pio_push32, 1184 samples); 1185} 1186 1187static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1188 int enable) 1189{ 1190 struct fsi_master *master = fsi_get_master(fsi); 1191 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1192 1193 if (enable) 1194 fsi_irq_enable(fsi, io); 1195 else 1196 fsi_irq_disable(fsi, io); 1197 1198 if (fsi_is_clk_master(fsi)) 1199 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1200 1201 return 0; 1202} 1203 1204static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) 1205{ 1206 /* 1207 * we can use 16bit stream mode 1208 * when "playback" and "16bit data" 1209 * and platform allows "stream mode" 1210 * see 1211 * fsi_pio_push16() 1212 */ 1213 if (fsi_is_enable_stream(fsi)) 1214 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1215 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1216 else 1217 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1218 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1219 return 0; 1220} 1221 1222static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) 1223{ 1224 /* 1225 * always 24bit bus, package back when "capture" 1226 */ 1227 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1228 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1229 return 0; 1230} 1231 1232static struct fsi_stream_handler fsi_pio_push_handler = { 1233 .init = fsi_pio_push_init, 1234 .transfer = fsi_pio_push, 1235 .start_stop = fsi_pio_start_stop, 1236}; 1237 1238static struct fsi_stream_handler fsi_pio_pop_handler = { 1239 .init = fsi_pio_pop_init, 1240 .transfer = fsi_pio_pop, 1241 .start_stop = fsi_pio_start_stop, 1242}; 1243 1244static irqreturn_t fsi_interrupt(int irq, void *data) 1245{ 1246 struct fsi_master *master = data; 1247 u32 int_st = fsi_irq_get_status(master); 1248 1249 /* clear irq status */ 1250 fsi_master_mask_set(master, SOFT_RST, IR, 0); 1251 fsi_master_mask_set(master, SOFT_RST, IR, IR); 1252 1253 if (int_st & AB_IO(1, AO_SHIFT)) 1254 fsi_stream_transfer(&master->fsia.playback); 1255 if (int_st & AB_IO(1, BO_SHIFT)) 1256 fsi_stream_transfer(&master->fsib.playback); 1257 if (int_st & AB_IO(1, AI_SHIFT)) 1258 fsi_stream_transfer(&master->fsia.capture); 1259 if (int_st & AB_IO(1, BI_SHIFT)) 1260 fsi_stream_transfer(&master->fsib.capture); 1261 1262 fsi_count_fifo_err(&master->fsia); 1263 fsi_count_fifo_err(&master->fsib); 1264 1265 fsi_irq_clear_status(&master->fsia); 1266 fsi_irq_clear_status(&master->fsib); 1267 1268 return IRQ_HANDLED; 1269} 1270 1271/* 1272 * dma data transfer handler 1273 */ 1274static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) 1275{ 1276 /* 1277 * 24bit data : 24bit bus / package in back 1278 * 16bit data : 16bit bus / stream mode 1279 */ 1280 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1281 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1282 1283 return 0; 1284} 1285 1286static void fsi_dma_complete(void *data) 1287{ 1288 struct fsi_stream *io = (struct fsi_stream *)data; 1289 struct fsi_priv *fsi = fsi_stream_to_priv(io); 1290 1291 fsi_pointer_update(io, io->period_samples); 1292 1293 fsi_count_fifo_err(fsi); 1294} 1295 1296static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) 1297{ 1298 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1299 struct snd_pcm_substream *substream = io->substream; 1300 struct dma_async_tx_descriptor *desc; 1301 int is_play = fsi_stream_is_play(fsi, io); 1302 enum dma_transfer_direction dir; 1303 int ret = -EIO; 1304 1305 if (is_play) 1306 dir = DMA_MEM_TO_DEV; 1307 else 1308 dir = DMA_DEV_TO_MEM; 1309 1310 desc = dmaengine_prep_dma_cyclic(io->chan, 1311 substream->runtime->dma_addr, 1312 snd_pcm_lib_buffer_bytes(substream), 1313 snd_pcm_lib_period_bytes(substream), 1314 dir, 1315 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1316 if (!desc) { 1317 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n"); 1318 goto fsi_dma_transfer_err; 1319 } 1320 1321 desc->callback = fsi_dma_complete; 1322 desc->callback_param = io; 1323 1324 if (dmaengine_submit(desc) < 0) { 1325 dev_err(dai->dev, "tx_submit() fail\n"); 1326 goto fsi_dma_transfer_err; 1327 } 1328 1329 dma_async_issue_pending(io->chan); 1330 1331 /* 1332 * FIXME 1333 * 1334 * In DMAEngine case, codec and FSI cannot be started simultaneously 1335 * since FSI is using the scheduler work queue. 1336 * Therefore, in capture case, probably FSI FIFO will have got 1337 * overflow error in this point. 1338 * in that case, DMA cannot start transfer until error was cleared. 1339 */ 1340 if (!is_play) { 1341 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { 1342 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1343 fsi_reg_write(fsi, DIFF_ST, 0); 1344 } 1345 } 1346 1347 ret = 0; 1348 1349fsi_dma_transfer_err: 1350 return ret; 1351} 1352 1353static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1354 int start) 1355{ 1356 struct fsi_master *master = fsi_get_master(fsi); 1357 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1358 u32 enable = start ? DMA_ON : 0; 1359 1360 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); 1361 1362 dmaengine_terminate_all(io->chan); 1363 1364 if (fsi_is_clk_master(fsi)) 1365 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1366 1367 return 0; 1368} 1369 1370static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) 1371{ 1372 int is_play = fsi_stream_is_play(fsi, io); 1373 1374#ifdef CONFIG_SUPERH 1375 dma_cap_mask_t mask; 1376 dma_cap_zero(mask); 1377 dma_cap_set(DMA_SLAVE, mask); 1378 1379 io->chan = dma_request_channel(mask, shdma_chan_filter, 1380 (void *)io->dma_id); 1381#else 1382 io->chan = dma_request_chan(dev, is_play ? "tx" : "rx"); 1383 if (IS_ERR(io->chan)) 1384 io->chan = NULL; 1385#endif 1386 if (io->chan) { 1387 struct dma_slave_config cfg = {}; 1388 int ret; 1389 1390 if (is_play) { 1391 cfg.dst_addr = fsi->phys + REG_DODT; 1392 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1393 cfg.direction = DMA_MEM_TO_DEV; 1394 } else { 1395 cfg.src_addr = fsi->phys + REG_DIDT; 1396 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1397 cfg.direction = DMA_DEV_TO_MEM; 1398 } 1399 1400 ret = dmaengine_slave_config(io->chan, &cfg); 1401 if (ret < 0) { 1402 dma_release_channel(io->chan); 1403 io->chan = NULL; 1404 } 1405 } 1406 1407 if (!io->chan) { 1408 1409 /* switch to PIO handler */ 1410 if (is_play) 1411 fsi->playback.handler = &fsi_pio_push_handler; 1412 else 1413 fsi->capture.handler = &fsi_pio_pop_handler; 1414 1415 dev_info(dev, "switch handler (dma => pio)\n"); 1416 1417 /* probe again */ 1418 return fsi_stream_probe(fsi, dev); 1419 } 1420 1421 return 0; 1422} 1423 1424static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) 1425{ 1426 fsi_stream_stop(fsi, io); 1427 1428 if (io->chan) 1429 dma_release_channel(io->chan); 1430 1431 io->chan = NULL; 1432 return 0; 1433} 1434 1435static struct fsi_stream_handler fsi_dma_push_handler = { 1436 .init = fsi_dma_init, 1437 .probe = fsi_dma_probe, 1438 .transfer = fsi_dma_transfer, 1439 .remove = fsi_dma_remove, 1440 .start_stop = fsi_dma_push_start_stop, 1441}; 1442 1443/* 1444 * dai ops 1445 */ 1446static void fsi_fifo_init(struct fsi_priv *fsi, 1447 struct fsi_stream *io, 1448 struct device *dev) 1449{ 1450 struct fsi_master *master = fsi_get_master(fsi); 1451 int is_play = fsi_stream_is_play(fsi, io); 1452 u32 shift, i; 1453 int frame_capa; 1454 1455 /* get on-chip RAM capacity */ 1456 shift = fsi_master_read(master, FIFO_SZ); 1457 shift >>= fsi_get_port_shift(fsi, io); 1458 shift &= FIFO_SZ_MASK; 1459 frame_capa = 256 << shift; 1460 dev_dbg(dev, "fifo = %d words\n", frame_capa); 1461 1462 /* 1463 * The maximum number of sample data varies depending 1464 * on the number of channels selected for the format. 1465 * 1466 * FIFOs are used in 4-channel units in 3-channel mode 1467 * and in 8-channel units in 5- to 7-channel mode 1468 * meaning that more FIFOs than the required size of DPRAM 1469 * are used. 1470 * 1471 * ex) if 256 words of DP-RAM is connected 1472 * 1 channel: 256 (256 x 1 = 256) 1473 * 2 channels: 128 (128 x 2 = 256) 1474 * 3 channels: 64 ( 64 x 3 = 192) 1475 * 4 channels: 64 ( 64 x 4 = 256) 1476 * 5 channels: 32 ( 32 x 5 = 160) 1477 * 6 channels: 32 ( 32 x 6 = 192) 1478 * 7 channels: 32 ( 32 x 7 = 224) 1479 * 8 channels: 32 ( 32 x 8 = 256) 1480 */ 1481 for (i = 1; i < fsi->chan_num; i <<= 1) 1482 frame_capa >>= 1; 1483 dev_dbg(dev, "%d channel %d store\n", 1484 fsi->chan_num, frame_capa); 1485 1486 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); 1487 1488 /* 1489 * set interrupt generation factor 1490 * clear FIFO 1491 */ 1492 if (is_play) { 1493 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); 1494 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); 1495 } else { 1496 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); 1497 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1498 } 1499} 1500 1501static int fsi_hw_startup(struct fsi_priv *fsi, 1502 struct fsi_stream *io, 1503 struct device *dev) 1504{ 1505 u32 data = 0; 1506 1507 /* clock setting */ 1508 if (fsi_is_clk_master(fsi)) 1509 data = DIMD | DOMD; 1510 1511 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); 1512 1513 /* clock inversion (CKG2) */ 1514 data = 0; 1515 if (fsi->bit_clk_inv) 1516 data |= (1 << 0); 1517 if (fsi->lr_clk_inv) 1518 data |= (1 << 4); 1519 if (fsi_is_clk_master(fsi)) 1520 data <<= 8; 1521 fsi_reg_write(fsi, CKG2, data); 1522 1523 /* spdif ? */ 1524 if (fsi_is_spdif(fsi)) { 1525 fsi_spdif_clk_ctrl(fsi, 1); 1526 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); 1527 } 1528 1529 /* 1530 * get bus settings 1531 */ 1532 data = 0; 1533 switch (io->sample_width) { 1534 case 2: 1535 data = BUSOP_GET(16, io->bus_option); 1536 break; 1537 case 4: 1538 data = BUSOP_GET(24, io->bus_option); 1539 break; 1540 } 1541 fsi_format_bus_setup(fsi, io, data, dev); 1542 1543 /* irq clear */ 1544 fsi_irq_disable(fsi, io); 1545 fsi_irq_clear_status(fsi); 1546 1547 /* fifo init */ 1548 fsi_fifo_init(fsi, io, dev); 1549 1550 /* start master clock */ 1551 if (fsi_is_clk_master(fsi)) 1552 return fsi_clk_enable(dev, fsi); 1553 1554 return 0; 1555} 1556 1557static int fsi_hw_shutdown(struct fsi_priv *fsi, 1558 struct device *dev) 1559{ 1560 /* stop master clock */ 1561 if (fsi_is_clk_master(fsi)) 1562 return fsi_clk_disable(dev, fsi); 1563 1564 return 0; 1565} 1566 1567static int fsi_dai_startup(struct snd_pcm_substream *substream, 1568 struct snd_soc_dai *dai) 1569{ 1570 struct fsi_priv *fsi = fsi_get_priv(substream); 1571 1572 fsi_clk_invalid(fsi); 1573 1574 return 0; 1575} 1576 1577static void fsi_dai_shutdown(struct snd_pcm_substream *substream, 1578 struct snd_soc_dai *dai) 1579{ 1580 struct fsi_priv *fsi = fsi_get_priv(substream); 1581 1582 fsi_clk_invalid(fsi); 1583} 1584 1585static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 1586 struct snd_soc_dai *dai) 1587{ 1588 struct fsi_priv *fsi = fsi_get_priv(substream); 1589 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1590 int ret = 0; 1591 1592 switch (cmd) { 1593 case SNDRV_PCM_TRIGGER_START: 1594 fsi_stream_init(fsi, io, substream); 1595 if (!ret) 1596 ret = fsi_hw_startup(fsi, io, dai->dev); 1597 if (!ret) 1598 ret = fsi_stream_start(fsi, io); 1599 if (!ret) 1600 ret = fsi_stream_transfer(io); 1601 break; 1602 case SNDRV_PCM_TRIGGER_STOP: 1603 if (!ret) 1604 ret = fsi_hw_shutdown(fsi, dai->dev); 1605 fsi_stream_stop(fsi, io); 1606 fsi_stream_quit(fsi, io); 1607 break; 1608 } 1609 1610 return ret; 1611} 1612 1613static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) 1614{ 1615 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1616 case SND_SOC_DAIFMT_I2S: 1617 fsi->fmt = CR_I2S; 1618 fsi->chan_num = 2; 1619 break; 1620 case SND_SOC_DAIFMT_LEFT_J: 1621 fsi->fmt = CR_PCM; 1622 fsi->chan_num = 2; 1623 break; 1624 default: 1625 return -EINVAL; 1626 } 1627 1628 return 0; 1629} 1630 1631static int fsi_set_fmt_spdif(struct fsi_priv *fsi) 1632{ 1633 struct fsi_master *master = fsi_get_master(fsi); 1634 1635 if (fsi_version(master) < 2) 1636 return -EINVAL; 1637 1638 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; 1639 fsi->chan_num = 2; 1640 1641 return 0; 1642} 1643 1644static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1645{ 1646 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); 1647 int ret; 1648 1649 /* set clock master audio interface */ 1650 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1651 case SND_SOC_DAIFMT_BC_FC: 1652 break; 1653 case SND_SOC_DAIFMT_BP_FP: 1654 fsi->clk_master = 1; /* cpu is master */ 1655 break; 1656 default: 1657 return -EINVAL; 1658 } 1659 1660 /* set clock inversion */ 1661 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1662 case SND_SOC_DAIFMT_NB_IF: 1663 fsi->bit_clk_inv = 0; 1664 fsi->lr_clk_inv = 1; 1665 break; 1666 case SND_SOC_DAIFMT_IB_NF: 1667 fsi->bit_clk_inv = 1; 1668 fsi->lr_clk_inv = 0; 1669 break; 1670 case SND_SOC_DAIFMT_IB_IF: 1671 fsi->bit_clk_inv = 1; 1672 fsi->lr_clk_inv = 1; 1673 break; 1674 case SND_SOC_DAIFMT_NB_NF: 1675 default: 1676 fsi->bit_clk_inv = 0; 1677 fsi->lr_clk_inv = 0; 1678 break; 1679 } 1680 1681 if (fsi_is_clk_master(fsi)) { 1682 if (fsi->clk_cpg) 1683 fsi_clk_init(dai->dev, fsi, 0, 1, 1, 1684 fsi_clk_set_rate_cpg); 1685 else 1686 fsi_clk_init(dai->dev, fsi, 1, 1, 0, 1687 fsi_clk_set_rate_external); 1688 } 1689 1690 /* set format */ 1691 if (fsi_is_spdif(fsi)) 1692 ret = fsi_set_fmt_spdif(fsi); 1693 else 1694 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1695 1696 return ret; 1697} 1698 1699static int fsi_dai_hw_params(struct snd_pcm_substream *substream, 1700 struct snd_pcm_hw_params *params, 1701 struct snd_soc_dai *dai) 1702{ 1703 struct fsi_priv *fsi = fsi_get_priv(substream); 1704 1705 if (fsi_is_clk_master(fsi)) 1706 fsi_clk_valid(fsi, params_rate(params)); 1707 1708 return 0; 1709} 1710 1711/* 1712 * Select below from Sound Card, not auto 1713 * SND_SOC_DAIFMT_CBC_CFC 1714 * SND_SOC_DAIFMT_CBP_CFP 1715 */ 1716static u64 fsi_dai_formats = 1717 SND_SOC_POSSIBLE_DAIFMT_I2S | 1718 SND_SOC_POSSIBLE_DAIFMT_LEFT_J | 1719 SND_SOC_POSSIBLE_DAIFMT_NB_NF | 1720 SND_SOC_POSSIBLE_DAIFMT_NB_IF | 1721 SND_SOC_POSSIBLE_DAIFMT_IB_NF | 1722 SND_SOC_POSSIBLE_DAIFMT_IB_IF; 1723 1724static const struct snd_soc_dai_ops fsi_dai_ops = { 1725 .startup = fsi_dai_startup, 1726 .shutdown = fsi_dai_shutdown, 1727 .trigger = fsi_dai_trigger, 1728 .set_fmt = fsi_dai_set_fmt, 1729 .hw_params = fsi_dai_hw_params, 1730 .auto_selectable_formats = &fsi_dai_formats, 1731 .num_auto_selectable_formats = 1, 1732}; 1733 1734/* 1735 * pcm ops 1736 */ 1737 1738static const struct snd_pcm_hardware fsi_pcm_hardware = { 1739 .info = SNDRV_PCM_INFO_INTERLEAVED | 1740 SNDRV_PCM_INFO_MMAP | 1741 SNDRV_PCM_INFO_MMAP_VALID, 1742 .buffer_bytes_max = 64 * 1024, 1743 .period_bytes_min = 32, 1744 .period_bytes_max = 8192, 1745 .periods_min = 1, 1746 .periods_max = 32, 1747 .fifo_size = 256, 1748}; 1749 1750static int fsi_pcm_open(struct snd_soc_component *component, 1751 struct snd_pcm_substream *substream) 1752{ 1753 struct snd_pcm_runtime *runtime = substream->runtime; 1754 int ret = 0; 1755 1756 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); 1757 1758 ret = snd_pcm_hw_constraint_integer(runtime, 1759 SNDRV_PCM_HW_PARAM_PERIODS); 1760 1761 return ret; 1762} 1763 1764static snd_pcm_uframes_t fsi_pointer(struct snd_soc_component *component, 1765 struct snd_pcm_substream *substream) 1766{ 1767 struct fsi_priv *fsi = fsi_get_priv(substream); 1768 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1769 1770 return fsi_sample2frame(fsi, io->buff_sample_pos); 1771} 1772 1773/* 1774 * snd_soc_component 1775 */ 1776 1777#define PREALLOC_BUFFER (32 * 1024) 1778#define PREALLOC_BUFFER_MAX (32 * 1024) 1779 1780static int fsi_pcm_new(struct snd_soc_component *component, 1781 struct snd_soc_pcm_runtime *rtd) 1782{ 1783 snd_pcm_set_managed_buffer_all( 1784 rtd->pcm, 1785 SNDRV_DMA_TYPE_DEV, 1786 rtd->card->snd_card->dev, 1787 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1788 return 0; 1789} 1790 1791/* 1792 * alsa struct 1793 */ 1794 1795static struct snd_soc_dai_driver fsi_soc_dai[] = { 1796 { 1797 .name = "fsia-dai", 1798 .playback = { 1799 .rates = FSI_RATES, 1800 .formats = FSI_FMTS, 1801 .channels_min = 2, 1802 .channels_max = 2, 1803 }, 1804 .capture = { 1805 .rates = FSI_RATES, 1806 .formats = FSI_FMTS, 1807 .channels_min = 2, 1808 .channels_max = 2, 1809 }, 1810 .ops = &fsi_dai_ops, 1811 }, 1812 { 1813 .name = "fsib-dai", 1814 .playback = { 1815 .rates = FSI_RATES, 1816 .formats = FSI_FMTS, 1817 .channels_min = 2, 1818 .channels_max = 2, 1819 }, 1820 .capture = { 1821 .rates = FSI_RATES, 1822 .formats = FSI_FMTS, 1823 .channels_min = 2, 1824 .channels_max = 2, 1825 }, 1826 .ops = &fsi_dai_ops, 1827 }, 1828}; 1829 1830static const struct snd_soc_component_driver fsi_soc_component = { 1831 .name = "fsi", 1832 .open = fsi_pcm_open, 1833 .pointer = fsi_pointer, 1834 .pcm_construct = fsi_pcm_new, 1835}; 1836 1837/* 1838 * platform function 1839 */ 1840static void fsi_of_parse(char *name, 1841 struct device_node *np, 1842 struct sh_fsi_port_info *info, 1843 struct device *dev) 1844{ 1845 int i; 1846 char prop[128]; 1847 unsigned long flags = 0; 1848 struct { 1849 char *name; 1850 unsigned int val; 1851 } of_parse_property[] = { 1852 { "spdif-connection", SH_FSI_FMT_SPDIF }, 1853 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE }, 1854 { "use-internal-clock", SH_FSI_CLK_CPG }, 1855 }; 1856 1857 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) { 1858 sprintf(prop, "%s,%s", name, of_parse_property[i].name); 1859 if (of_property_present(np, prop)) 1860 flags |= of_parse_property[i].val; 1861 } 1862 info->flags = flags; 1863 1864 dev_dbg(dev, "%s flags : %lx\n", name, info->flags); 1865} 1866 1867static void fsi_port_info_init(struct fsi_priv *fsi, 1868 struct sh_fsi_port_info *info) 1869{ 1870 if (info->flags & SH_FSI_FMT_SPDIF) 1871 fsi->spdif = 1; 1872 1873 if (info->flags & SH_FSI_CLK_CPG) 1874 fsi->clk_cpg = 1; 1875 1876 if (info->flags & SH_FSI_ENABLE_STREAM_MODE) 1877 fsi->enable_stream = 1; 1878} 1879 1880static void fsi_handler_init(struct fsi_priv *fsi, 1881 struct sh_fsi_port_info *info) 1882{ 1883 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ 1884 fsi->playback.priv = fsi; 1885 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ 1886 fsi->capture.priv = fsi; 1887 1888 if (info->tx_id) { 1889 fsi->playback.dma_id = info->tx_id; 1890 fsi->playback.handler = &fsi_dma_push_handler; 1891 } 1892} 1893 1894static const struct fsi_core fsi1_core = { 1895 .ver = 1, 1896 1897 /* Interrupt */ 1898 .int_st = INT_ST, 1899 .iemsk = IEMSK, 1900 .imsk = IMSK, 1901}; 1902 1903static const struct fsi_core fsi2_core = { 1904 .ver = 2, 1905 1906 /* Interrupt */ 1907 .int_st = CPU_INT_ST, 1908 .iemsk = CPU_IEMSK, 1909 .imsk = CPU_IMSK, 1910 .a_mclk = A_MST_CTLR, 1911 .b_mclk = B_MST_CTLR, 1912}; 1913 1914static const struct of_device_id fsi_of_match[] = { 1915 { .compatible = "renesas,sh_fsi", .data = &fsi1_core}, 1916 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core}, 1917 {}, 1918}; 1919MODULE_DEVICE_TABLE(of, fsi_of_match); 1920 1921static const struct platform_device_id fsi_id_table[] = { 1922 { "sh_fsi", (kernel_ulong_t)&fsi1_core }, 1923 {}, 1924}; 1925MODULE_DEVICE_TABLE(platform, fsi_id_table); 1926 1927static int fsi_probe(struct platform_device *pdev) 1928{ 1929 struct fsi_master *master; 1930 struct device_node *np = pdev->dev.of_node; 1931 struct sh_fsi_platform_info info; 1932 const struct fsi_core *core; 1933 struct fsi_priv *fsi; 1934 struct resource *res; 1935 unsigned int irq; 1936 int ret; 1937 1938 memset(&info, 0, sizeof(info)); 1939 1940 core = NULL; 1941 if (np) { 1942 core = of_device_get_match_data(&pdev->dev); 1943 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev); 1944 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev); 1945 } else { 1946 const struct platform_device_id *id_entry = pdev->id_entry; 1947 if (id_entry) 1948 core = (struct fsi_core *)id_entry->driver_data; 1949 1950 if (pdev->dev.platform_data) 1951 memcpy(&info, pdev->dev.platform_data, sizeof(info)); 1952 } 1953 1954 if (!core) { 1955 dev_err(&pdev->dev, "unknown fsi device\n"); 1956 return -ENODEV; 1957 } 1958 1959 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1960 irq = platform_get_irq(pdev, 0); 1961 if (!res || (int)irq <= 0) { 1962 dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); 1963 return -ENODEV; 1964 } 1965 1966 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 1967 if (!master) 1968 return -ENOMEM; 1969 1970 master->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1971 if (!master->base) { 1972 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); 1973 return -ENXIO; 1974 } 1975 1976 /* master setting */ 1977 master->core = core; 1978 spin_lock_init(&master->lock); 1979 1980 /* FSI A setting */ 1981 fsi = &master->fsia; 1982 fsi->base = master->base; 1983 fsi->phys = res->start; 1984 fsi->master = master; 1985 fsi_port_info_init(fsi, &info.port_a); 1986 fsi_handler_init(fsi, &info.port_a); 1987 ret = fsi_stream_probe(fsi, &pdev->dev); 1988 if (ret < 0) { 1989 dev_err(&pdev->dev, "FSIA stream probe failed\n"); 1990 return ret; 1991 } 1992 1993 /* FSI B setting */ 1994 fsi = &master->fsib; 1995 fsi->base = master->base + 0x40; 1996 fsi->phys = res->start + 0x40; 1997 fsi->master = master; 1998 fsi_port_info_init(fsi, &info.port_b); 1999 fsi_handler_init(fsi, &info.port_b); 2000 ret = fsi_stream_probe(fsi, &pdev->dev); 2001 if (ret < 0) { 2002 dev_err(&pdev->dev, "FSIB stream probe failed\n"); 2003 goto exit_fsia; 2004 } 2005 2006 pm_runtime_enable(&pdev->dev); 2007 dev_set_drvdata(&pdev->dev, master); 2008 2009 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0, 2010 dev_name(&pdev->dev), master); 2011 if (ret) { 2012 dev_err(&pdev->dev, "irq request err\n"); 2013 goto exit_fsib; 2014 } 2015 2016 ret = devm_snd_soc_register_component(&pdev->dev, &fsi_soc_component, 2017 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 2018 if (ret < 0) { 2019 dev_err(&pdev->dev, "cannot snd component register\n"); 2020 goto exit_fsib; 2021 } 2022 2023 return ret; 2024 2025exit_fsib: 2026 pm_runtime_disable(&pdev->dev); 2027 fsi_stream_remove(&master->fsib); 2028exit_fsia: 2029 fsi_stream_remove(&master->fsia); 2030 2031 return ret; 2032} 2033 2034static void fsi_remove(struct platform_device *pdev) 2035{ 2036 struct fsi_master *master; 2037 2038 master = dev_get_drvdata(&pdev->dev); 2039 2040 pm_runtime_disable(&pdev->dev); 2041 2042 fsi_stream_remove(&master->fsia); 2043 fsi_stream_remove(&master->fsib); 2044} 2045 2046static void __fsi_suspend(struct fsi_priv *fsi, 2047 struct fsi_stream *io, 2048 struct device *dev) 2049{ 2050 if (!fsi_stream_is_working(fsi, io)) 2051 return; 2052 2053 fsi_stream_stop(fsi, io); 2054 fsi_hw_shutdown(fsi, dev); 2055} 2056 2057static void __fsi_resume(struct fsi_priv *fsi, 2058 struct fsi_stream *io, 2059 struct device *dev) 2060{ 2061 if (!fsi_stream_is_working(fsi, io)) 2062 return; 2063 2064 fsi_hw_startup(fsi, io, dev); 2065 fsi_stream_start(fsi, io); 2066} 2067 2068static int fsi_suspend(struct device *dev) 2069{ 2070 struct fsi_master *master = dev_get_drvdata(dev); 2071 struct fsi_priv *fsia = &master->fsia; 2072 struct fsi_priv *fsib = &master->fsib; 2073 2074 __fsi_suspend(fsia, &fsia->playback, dev); 2075 __fsi_suspend(fsia, &fsia->capture, dev); 2076 2077 __fsi_suspend(fsib, &fsib->playback, dev); 2078 __fsi_suspend(fsib, &fsib->capture, dev); 2079 2080 return 0; 2081} 2082 2083static int fsi_resume(struct device *dev) 2084{ 2085 struct fsi_master *master = dev_get_drvdata(dev); 2086 struct fsi_priv *fsia = &master->fsia; 2087 struct fsi_priv *fsib = &master->fsib; 2088 2089 __fsi_resume(fsia, &fsia->playback, dev); 2090 __fsi_resume(fsia, &fsia->capture, dev); 2091 2092 __fsi_resume(fsib, &fsib->playback, dev); 2093 __fsi_resume(fsib, &fsib->capture, dev); 2094 2095 return 0; 2096} 2097 2098static const struct dev_pm_ops fsi_pm_ops = { 2099 .suspend = fsi_suspend, 2100 .resume = fsi_resume, 2101}; 2102 2103static struct platform_driver fsi_driver = { 2104 .driver = { 2105 .name = "fsi-pcm-audio", 2106 .pm = &fsi_pm_ops, 2107 .of_match_table = fsi_of_match, 2108 }, 2109 .probe = fsi_probe, 2110 .remove_new = fsi_remove, 2111 .id_table = fsi_id_table, 2112}; 2113 2114module_platform_driver(fsi_driver); 2115 2116MODULE_LICENSE("GPL v2"); 2117MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); 2118MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 2119MODULE_ALIAS("platform:fsi-pcm-audio"); 2120