1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * linux/sound/soc/pxa/mmp-sspa.h 4 * 5 * Copyright (C) 2011 Marvell International Ltd. 6 */ 7#ifndef _MMP_SSPA_H 8#define _MMP_SSPA_H 9 10/* 11 * SSPA Registers 12 */ 13#define SSPA_D (0x00) 14#define SSPA_ID (0x04) 15#define SSPA_CTL (0x08) 16#define SSPA_SP (0x0c) 17#define SSPA_FIFO_UL (0x10) 18#define SSPA_INT_MASK (0x14) 19#define SSPA_C (0x18) 20#define SSPA_FIFO_NOFS (0x1c) 21#define SSPA_FIFO_SIZE (0x20) 22 23/* SSPA Control Register */ 24#define SSPA_CTL_XPH (1 << 31) /* Read Phase */ 25#define SSPA_CTL_XFIG (1 << 15) /* Transmit Zeros when FIFO Empty */ 26#define SSPA_CTL_JST (1 << 3) /* Audio Sample Justification */ 27#define SSPA_CTL_XFRLEN2_MASK (7 << 24) 28#define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */ 29#define SSPA_CTL_XWDLEN2_MASK (7 << 21) 30#define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */ 31#define SSPA_CTL_XDATDLY(x) ((x) << 19) /* Transmit Data Delay */ 32#define SSPA_CTL_XSSZ2_MASK (7 << 16) 33#define SSPA_CTL_XSSZ2(x) ((x) << 16) /* Transmit Sample Audio Size */ 34#define SSPA_CTL_XFRLEN1_MASK (7 << 8) 35#define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */ 36#define SSPA_CTL_XWDLEN1_MASK (7 << 5) 37#define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */ 38#define SSPA_CTL_XSSZ1_MASK (7 << 0) 39#define SSPA_CTL_XSSZ1(x) ((x) << 0) /* XSSZ1 */ 40 41#define SSPA_CTL_8_BITS (0x0) /* Sample Size */ 42#define SSPA_CTL_12_BITS (0x1) 43#define SSPA_CTL_16_BITS (0x2) 44#define SSPA_CTL_20_BITS (0x3) 45#define SSPA_CTL_24_BITS (0x4) 46#define SSPA_CTL_32_BITS (0x5) 47 48/* SSPA Serial Port Register */ 49#define SSPA_SP_WEN (1 << 31) /* Write Configuration Enable */ 50#define SSPA_SP_MSL (1 << 18) /* Master Slave Configuration */ 51#define SSPA_SP_CLKP (1 << 17) /* CLKP Polarity Clock Edge Select */ 52#define SSPA_SP_FSP (1 << 16) /* FSP Polarity Clock Edge Select */ 53#define SSPA_SP_FFLUSH (1 << 2) /* FIFO Flush */ 54#define SSPA_SP_S_RST (1 << 1) /* Active High Reset Signal */ 55#define SSPA_SP_S_EN (1 << 0) /* Serial Clock Domain Enable */ 56#define SSPA_SP_FWID_MASK (0x3f << 20) 57#define SSPA_SP_FWID(x) ((x) << 20) /* Frame-Sync Width */ 58#define SSPA_TXSP_FPER_MASK (0x3f << 4) 59#define SSPA_TXSP_FPER(x) ((x) << 4) /* Frame-Sync Active */ 60 61/* sspa clock sources */ 62#define MMP_SSPA_CLK_PLL 0 63#define MMP_SSPA_CLK_VCXO 1 64#define MMP_SSPA_CLK_AUDIO 3 65 66/* sspa pll id */ 67#define MMP_SYSCLK 0 68#define MMP_SSPA_CLK 1 69 70#endif /* _MMP_SSPA_H */ 71