1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * mt8195-afe-common.h  --  Mediatek 8195 audio driver definitions
4 *
5 * Copyright (c) 2021 MediaTek Inc.
6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7 *         Trevor Wu <trevor.wu@mediatek.com>
8 */
9
10#ifndef _MT_8195_AFE_COMMON_H_
11#define _MT_8195_AFE_COMMON_H_
12
13#include <sound/soc.h>
14#include <linux/list.h>
15#include <linux/regmap.h>
16#include "../common/mtk-base-afe.h"
17
18enum {
19	MT8195_DAI_START,
20	MT8195_AFE_MEMIF_START = MT8195_DAI_START,
21	MT8195_AFE_MEMIF_DL2 = MT8195_AFE_MEMIF_START,
22	MT8195_AFE_MEMIF_DL3,
23	MT8195_AFE_MEMIF_DL6,
24	MT8195_AFE_MEMIF_DL7,
25	MT8195_AFE_MEMIF_DL8,
26	MT8195_AFE_MEMIF_DL10,
27	MT8195_AFE_MEMIF_DL11,
28	MT8195_AFE_MEMIF_UL_START,
29	MT8195_AFE_MEMIF_UL1 = MT8195_AFE_MEMIF_UL_START,
30	MT8195_AFE_MEMIF_UL2,
31	MT8195_AFE_MEMIF_UL3,
32	MT8195_AFE_MEMIF_UL4,
33	MT8195_AFE_MEMIF_UL5,
34	MT8195_AFE_MEMIF_UL6,
35	MT8195_AFE_MEMIF_UL8,
36	MT8195_AFE_MEMIF_UL9,
37	MT8195_AFE_MEMIF_UL10,
38	MT8195_AFE_MEMIF_END,
39	MT8195_AFE_MEMIF_NUM = (MT8195_AFE_MEMIF_END - MT8195_AFE_MEMIF_START),
40	MT8195_AFE_IO_START = MT8195_AFE_MEMIF_END,
41	MT8195_AFE_IO_DL_SRC = MT8195_AFE_IO_START,
42	MT8195_AFE_IO_DPTX,
43	MT8195_AFE_IO_ETDM_START,
44	MT8195_AFE_IO_ETDM1_IN = MT8195_AFE_IO_ETDM_START,
45	MT8195_AFE_IO_ETDM2_IN,
46	MT8195_AFE_IO_ETDM1_OUT,
47	MT8195_AFE_IO_ETDM2_OUT,
48	MT8195_AFE_IO_ETDM3_OUT,
49	MT8195_AFE_IO_ETDM_END,
50	MT8195_AFE_IO_ETDM_NUM =
51		(MT8195_AFE_IO_ETDM_END - MT8195_AFE_IO_ETDM_START),
52	MT8195_AFE_IO_PCM = MT8195_AFE_IO_ETDM_END,
53	MT8195_AFE_IO_UL_SRC1,
54	MT8195_AFE_IO_UL_SRC2,
55	MT8195_AFE_IO_END,
56	MT8195_AFE_IO_NUM = (MT8195_AFE_IO_END - MT8195_AFE_IO_START),
57	MT8195_DAI_END = MT8195_AFE_IO_END,
58	MT8195_DAI_NUM = (MT8195_DAI_END - MT8195_DAI_START),
59};
60
61enum {
62	MT8195_TOP_CG_A1SYS_TIMING,
63	MT8195_TOP_CG_A2SYS_TIMING,
64	MT8195_TOP_CG_26M_TIMING,
65	MT8195_TOP_CG_NUM,
66};
67
68enum {
69	MT8195_AFE_IRQ_1,
70	MT8195_AFE_IRQ_2,
71	MT8195_AFE_IRQ_3,
72	MT8195_AFE_IRQ_8,
73	MT8195_AFE_IRQ_9,
74	MT8195_AFE_IRQ_10,
75	MT8195_AFE_IRQ_13,
76	MT8195_AFE_IRQ_14,
77	MT8195_AFE_IRQ_15,
78	MT8195_AFE_IRQ_16,
79	MT8195_AFE_IRQ_17,
80	MT8195_AFE_IRQ_18,
81	MT8195_AFE_IRQ_19,
82	MT8195_AFE_IRQ_20,
83	MT8195_AFE_IRQ_21,
84	MT8195_AFE_IRQ_22,
85	MT8195_AFE_IRQ_23,
86	MT8195_AFE_IRQ_24,
87	MT8195_AFE_IRQ_25,
88	MT8195_AFE_IRQ_26,
89	MT8195_AFE_IRQ_27,
90	MT8195_AFE_IRQ_28,
91	MT8195_AFE_IRQ_NUM,
92};
93
94enum {
95	MT8195_ETDM_OUT1_1X_EN = 9,
96	MT8195_ETDM_OUT2_1X_EN = 10,
97	MT8195_ETDM_OUT3_1X_EN = 11,
98	MT8195_ETDM_IN1_1X_EN = 12,
99	MT8195_ETDM_IN2_1X_EN = 13,
100	MT8195_ETDM_IN1_NX_EN = 25,
101	MT8195_ETDM_IN2_NX_EN = 26,
102};
103
104enum {
105	MT8195_MTKAIF_MISO_0,
106	MT8195_MTKAIF_MISO_1,
107	MT8195_MTKAIF_MISO_2,
108	MT8195_MTKAIF_MISO_NUM,
109};
110
111struct mtk_dai_memif_irq_priv {
112	unsigned int asys_timing_sel;
113};
114
115struct mtkaif_param {
116	bool mtkaif_calibration_ok;
117	int mtkaif_chosen_phase[MT8195_MTKAIF_MISO_NUM];
118	int mtkaif_phase_cycle[MT8195_MTKAIF_MISO_NUM];
119	int mtkaif_dmic_on;
120	int mtkaif_adda6_only;
121};
122
123struct clk;
124
125struct mt8195_afe_private {
126	struct clk **clk;
127	struct clk_lookup **lookup;
128	struct regmap *topckgen;
129	int pm_runtime_bypass_reg_ctl;
130#ifdef CONFIG_DEBUG_FS
131	struct dentry **debugfs_dentry;
132#endif
133	int afe_on_ref_cnt;
134	int top_cg_ref_cnt[MT8195_TOP_CG_NUM];
135	spinlock_t afe_ctrl_lock;	/* Lock for afe control */
136	struct mtk_dai_memif_irq_priv irq_priv[MT8195_AFE_IRQ_NUM];
137	struct mtkaif_param mtkaif_params;
138
139	/* dai */
140	void *dai_priv[MT8195_DAI_NUM];
141};
142
143int mt8195_afe_fs_timing(unsigned int rate);
144/* dai register */
145int mt8195_dai_adda_register(struct mtk_base_afe *afe);
146int mt8195_dai_etdm_register(struct mtk_base_afe *afe);
147int mt8195_dai_pcm_register(struct mtk_base_afe *afe);
148
149#define MT8195_SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put, id) \
150{ \
151	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
152	.info = snd_soc_info_enum_double, \
153	.get = xhandler_get, .put = xhandler_put, \
154	.device = id, \
155	.private_value = (unsigned long)&xenum, \
156}
157
158#endif
159