1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * skl.c - Implementation of ASoC Intel SKL HD Audio driver 4 * 5 * Copyright (C) 2014-2015 Intel Corp 6 * Author: Jeeja KP <jeeja.kp@intel.com> 7 * 8 * Derived mostly from Intel HDA driver with following copyrights: 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 12 * 13 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 14 */ 15 16#include <linux/module.h> 17#include <linux/pci.h> 18#include <linux/pm_runtime.h> 19#include <linux/platform_device.h> 20#include <linux/firmware.h> 21#include <linux/delay.h> 22#include <sound/pcm.h> 23#include <sound/soc-acpi.h> 24#include <sound/soc-acpi-intel-match.h> 25#include <sound/hda_register.h> 26#include <sound/hdaudio.h> 27#include <sound/hda_i915.h> 28#include <sound/hda_codec.h> 29#include <sound/intel-nhlt.h> 30#include <sound/intel-dsp-config.h> 31#include "skl.h" 32#include "skl-sst-dsp.h" 33#include "skl-sst-ipc.h" 34 35#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 36#include "../../../soc/codecs/hdac_hda.h" 37#endif 38static int skl_pci_binding; 39module_param_named(pci_binding, skl_pci_binding, int, 0444); 40MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc"); 41 42/* 43 * initialize the PCI registers 44 */ 45static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, 46 unsigned char mask, unsigned char val) 47{ 48 unsigned char data; 49 50 pci_read_config_byte(pci, reg, &data); 51 data &= ~mask; 52 data |= (val & mask); 53 pci_write_config_byte(pci, reg, data); 54} 55 56static void skl_init_pci(struct skl_dev *skl) 57{ 58 struct hdac_bus *bus = skl_to_bus(skl); 59 60 /* 61 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 62 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 63 * Ensuring these bits are 0 clears playback static on some HD Audio 64 * codecs. 65 * The PCI register TCSEL is defined in the Intel manuals. 66 */ 67 dev_dbg(bus->dev, "Clearing TCSEL\n"); 68 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); 69} 70 71static void update_pci_dword(struct pci_dev *pci, 72 unsigned int reg, u32 mask, u32 val) 73{ 74 u32 data = 0; 75 76 pci_read_config_dword(pci, reg, &data); 77 data &= ~mask; 78 data |= (val & mask); 79 pci_write_config_dword(pci, reg, data); 80} 81 82/* 83 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits 84 * 85 * @dev: device pointer 86 * @enable: enable/disable flag 87 */ 88static void skl_enable_miscbdcge(struct device *dev, bool enable) 89{ 90 struct pci_dev *pci = to_pci_dev(dev); 91 u32 val; 92 93 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; 94 95 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); 96} 97 98/** 99 * skl_clock_power_gating: Enable/Disable clock and power gating 100 * 101 * @dev: Device pointer 102 * @enable: Enable/Disable flag 103 */ 104static void skl_clock_power_gating(struct device *dev, bool enable) 105{ 106 struct pci_dev *pci = to_pci_dev(dev); 107 struct hdac_bus *bus = pci_get_drvdata(pci); 108 u32 val; 109 110 /* Update PDCGE bit of CGCTL register */ 111 val = enable ? AZX_CGCTL_ADSPDCGE : 0; 112 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); 113 114 /* Update L1SEN bit of EM2 register */ 115 val = enable ? AZX_REG_VS_EM2_L1SEN : 0; 116 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val); 117 118 /* Update ADSPPGD bit of PGCTL register */ 119 val = enable ? 0 : AZX_PGCTL_ADSPPGD; 120 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val); 121} 122 123/* 124 * While performing reset, controller may not come back properly causing 125 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset 126 * (init chip) and then again set CGCTL.MISCBDCGE to 1 127 */ 128static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 129{ 130 struct hdac_ext_link *hlink; 131 int ret; 132 133 snd_hdac_set_codec_wakeup(bus, true); 134 skl_enable_miscbdcge(bus->dev, false); 135 ret = snd_hdac_bus_init_chip(bus, full_reset); 136 137 /* Reset stream-to-link mapping */ 138 list_for_each_entry(hlink, &bus->hlink_list, list) 139 writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); 140 141 skl_enable_miscbdcge(bus->dev, true); 142 snd_hdac_set_codec_wakeup(bus, false); 143 144 return ret; 145} 146 147void skl_update_d0i3c(struct device *dev, bool enable) 148{ 149 struct pci_dev *pci = to_pci_dev(dev); 150 struct hdac_bus *bus = pci_get_drvdata(pci); 151 u8 reg; 152 int timeout = 50; 153 154 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 155 /* Do not write to D0I3C until command in progress bit is cleared */ 156 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 157 udelay(10); 158 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 159 } 160 161 /* Highly unlikely. But if it happens, flag error explicitly */ 162 if (!timeout) { 163 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n"); 164 return; 165 } 166 167 if (enable) 168 reg = reg | AZX_REG_VS_D0I3C_I3; 169 else 170 reg = reg & (~AZX_REG_VS_D0I3C_I3); 171 172 snd_hdac_chip_writeb(bus, VS_D0I3C, reg); 173 174 timeout = 50; 175 /* Wait for cmd in progress to be cleared before exiting the function */ 176 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 177 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { 178 udelay(10); 179 reg = snd_hdac_chip_readb(bus, VS_D0I3C); 180 } 181 182 /* Highly unlikely. But if it happens, flag error explicitly */ 183 if (!timeout) { 184 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n"); 185 return; 186 } 187 188 dev_dbg(bus->dev, "D0I3C register = 0x%x\n", 189 snd_hdac_chip_readb(bus, VS_D0I3C)); 190} 191 192/** 193 * skl_dum_set - set DUM bit in EM2 register 194 * @bus: HD-audio core bus 195 * 196 * Addresses incorrect position reporting for capture streams. 197 * Used on device power up. 198 */ 199static void skl_dum_set(struct hdac_bus *bus) 200{ 201 /* For the DUM bit to be set, CRST needs to be out of reset state */ 202 if (!(snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)) { 203 skl_enable_miscbdcge(bus->dev, false); 204 snd_hdac_bus_exit_link_reset(bus); 205 skl_enable_miscbdcge(bus->dev, true); 206 } 207 208 snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM); 209} 210 211/* called from IRQ */ 212static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) 213{ 214 snd_pcm_period_elapsed(hstr->substream); 215} 216 217static irqreturn_t skl_interrupt(int irq, void *dev_id) 218{ 219 struct hdac_bus *bus = dev_id; 220 u32 status; 221 222 if (!pm_runtime_active(bus->dev)) 223 return IRQ_NONE; 224 225 spin_lock(&bus->reg_lock); 226 227 status = snd_hdac_chip_readl(bus, INTSTS); 228 if (status == 0 || status == 0xffffffff) { 229 spin_unlock(&bus->reg_lock); 230 return IRQ_NONE; 231 } 232 233 /* clear rirb int */ 234 status = snd_hdac_chip_readb(bus, RIRBSTS); 235 if (status & RIRB_INT_MASK) { 236 if (status & RIRB_INT_RESPONSE) 237 snd_hdac_bus_update_rirb(bus); 238 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 239 } 240 241 spin_unlock(&bus->reg_lock); 242 243 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 244} 245 246static irqreturn_t skl_threaded_handler(int irq, void *dev_id) 247{ 248 struct hdac_bus *bus = dev_id; 249 u32 status; 250 251 status = snd_hdac_chip_readl(bus, INTSTS); 252 253 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); 254 255 return IRQ_HANDLED; 256} 257 258static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect) 259{ 260 struct skl_dev *skl = bus_to_skl(bus); 261 int ret; 262 263 ret = request_threaded_irq(skl->pci->irq, skl_interrupt, 264 skl_threaded_handler, 265 IRQF_SHARED, 266 KBUILD_MODNAME, bus); 267 if (ret) { 268 dev_err(bus->dev, 269 "unable to grab IRQ %d, disabling device\n", 270 skl->pci->irq); 271 return ret; 272 } 273 274 bus->irq = skl->pci->irq; 275 pci_intx(skl->pci, 1); 276 277 return 0; 278} 279 280static int skl_suspend_late(struct device *dev) 281{ 282 struct pci_dev *pci = to_pci_dev(dev); 283 struct hdac_bus *bus = pci_get_drvdata(pci); 284 struct skl_dev *skl = bus_to_skl(bus); 285 286 return skl_suspend_late_dsp(skl); 287} 288 289#ifdef CONFIG_PM 290static int _skl_suspend(struct hdac_bus *bus) 291{ 292 struct skl_dev *skl = bus_to_skl(bus); 293 struct pci_dev *pci = to_pci_dev(bus->dev); 294 int ret; 295 296 snd_hdac_ext_bus_link_power_down_all(bus); 297 298 ret = skl_suspend_dsp(skl); 299 if (ret < 0) 300 return ret; 301 302 snd_hdac_bus_stop_chip(bus); 303 update_pci_dword(pci, AZX_PCIREG_PGCTL, 304 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); 305 skl_enable_miscbdcge(bus->dev, false); 306 snd_hdac_bus_enter_link_reset(bus); 307 skl_enable_miscbdcge(bus->dev, true); 308 skl_cleanup_resources(skl); 309 310 return 0; 311} 312 313static int _skl_resume(struct hdac_bus *bus) 314{ 315 struct skl_dev *skl = bus_to_skl(bus); 316 317 skl_init_pci(skl); 318 skl_dum_set(bus); 319 skl_init_chip(bus, true); 320 321 return skl_resume_dsp(skl); 322} 323#endif 324 325#ifdef CONFIG_PM_SLEEP 326/* 327 * power management 328 */ 329static int skl_suspend(struct device *dev) 330{ 331 struct pci_dev *pci = to_pci_dev(dev); 332 struct hdac_bus *bus = pci_get_drvdata(pci); 333 struct skl_dev *skl = bus_to_skl(bus); 334 int ret; 335 336 /* 337 * Do not suspend if streams which are marked ignore suspend are 338 * running, we need to save the state for these and continue 339 */ 340 if (skl->supend_active) { 341 /* turn off the links and stop the CORB/RIRB DMA if it is On */ 342 snd_hdac_ext_bus_link_power_down_all(bus); 343 344 if (bus->cmd_dma_state) 345 snd_hdac_bus_stop_cmd_io(bus); 346 347 enable_irq_wake(bus->irq); 348 pci_save_state(pci); 349 } else { 350 ret = _skl_suspend(bus); 351 if (ret < 0) 352 return ret; 353 skl->fw_loaded = false; 354 } 355 356 return 0; 357} 358 359static int skl_resume(struct device *dev) 360{ 361 struct pci_dev *pci = to_pci_dev(dev); 362 struct hdac_bus *bus = pci_get_drvdata(pci); 363 struct skl_dev *skl = bus_to_skl(bus); 364 struct hdac_ext_link *hlink; 365 int ret; 366 367 /* 368 * resume only when we are not in suspend active, otherwise need to 369 * restore the device 370 */ 371 if (skl->supend_active) { 372 pci_restore_state(pci); 373 snd_hdac_ext_bus_link_power_up_all(bus); 374 disable_irq_wake(bus->irq); 375 /* 376 * turn On the links which are On before active suspend 377 * and start the CORB/RIRB DMA if On before 378 * active suspend. 379 */ 380 list_for_each_entry(hlink, &bus->hlink_list, list) { 381 if (hlink->ref_count) 382 snd_hdac_ext_bus_link_power_up(hlink); 383 } 384 385 ret = 0; 386 if (bus->cmd_dma_state) 387 snd_hdac_bus_init_cmd_io(bus); 388 } else { 389 ret = _skl_resume(bus); 390 } 391 392 return ret; 393} 394#endif /* CONFIG_PM_SLEEP */ 395 396#ifdef CONFIG_PM 397static int skl_runtime_suspend(struct device *dev) 398{ 399 struct pci_dev *pci = to_pci_dev(dev); 400 struct hdac_bus *bus = pci_get_drvdata(pci); 401 402 dev_dbg(bus->dev, "in %s\n", __func__); 403 404 return _skl_suspend(bus); 405} 406 407static int skl_runtime_resume(struct device *dev) 408{ 409 struct pci_dev *pci = to_pci_dev(dev); 410 struct hdac_bus *bus = pci_get_drvdata(pci); 411 412 dev_dbg(bus->dev, "in %s\n", __func__); 413 414 return _skl_resume(bus); 415} 416#endif /* CONFIG_PM */ 417 418static const struct dev_pm_ops skl_pm = { 419 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) 420 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) 421 .suspend_late = skl_suspend_late, 422}; 423 424/* 425 * destructor 426 */ 427static int skl_free(struct hdac_bus *bus) 428{ 429 struct skl_dev *skl = bus_to_skl(bus); 430 431 skl->init_done = 0; /* to be sure */ 432 433 snd_hdac_stop_streams_and_chip(bus); 434 435 if (bus->irq >= 0) 436 free_irq(bus->irq, (void *)bus); 437 snd_hdac_bus_free_stream_pages(bus); 438 snd_hdac_ext_stream_free_all(bus); 439 snd_hdac_ext_link_free_all(bus); 440 441 if (bus->remap_addr) 442 iounmap(bus->remap_addr); 443 444 pci_release_regions(skl->pci); 445 pci_disable_device(skl->pci); 446 447 snd_hdac_ext_bus_exit(bus); 448 449 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 450 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 451 snd_hdac_i915_exit(bus); 452 } 453 454 return 0; 455} 456 457/* 458 * For each ssp there are 3 clocks (mclk/sclk/sclkfs). 459 * e.g. for ssp0, clocks will be named as 460 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs" 461 * So for skl+, there are 6 ssps, so 18 clocks will be created. 462 */ 463static struct skl_ssp_clk skl_ssp_clks[] = { 464 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"}, 465 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"}, 466 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"}, 467 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"}, 468 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"}, 469 {.name = "ssp2_sclkfs"}, 470 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"}, 471 {.name = "ssp5_sclkfs"}, 472}; 473 474static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl_dev *skl, 475 struct snd_soc_acpi_mach *machines) 476{ 477 struct snd_soc_acpi_mach *mach; 478 479 /* point to common table */ 480 mach = snd_soc_acpi_intel_hda_machines; 481 482 /* all entries in the machine table use the same firmware */ 483 mach->fw_filename = machines->fw_filename; 484 485 return mach; 486} 487 488static int skl_find_machine(struct skl_dev *skl, void *driver_data) 489{ 490 struct hdac_bus *bus = skl_to_bus(skl); 491 struct snd_soc_acpi_mach *mach = driver_data; 492 struct skl_machine_pdata *pdata; 493 494 mach = snd_soc_acpi_find_machine(mach); 495 if (!mach) { 496 dev_dbg(bus->dev, "No matching I2S machine driver found\n"); 497 mach = skl_find_hda_machine(skl, driver_data); 498 if (!mach) { 499 dev_err(bus->dev, "No matching machine driver found\n"); 500 return -ENODEV; 501 } 502 } 503 504 skl->mach = mach; 505 skl->fw_name = mach->fw_filename; 506 pdata = mach->pdata; 507 508 if (pdata) { 509 skl->use_tplg_pcm = pdata->use_tplg_pcm; 510 mach->mach_params.dmic_num = 511 intel_nhlt_get_dmic_geo(&skl->pci->dev, 512 skl->nhlt); 513 } 514 515 return 0; 516} 517 518static int skl_machine_device_register(struct skl_dev *skl) 519{ 520 struct snd_soc_acpi_mach *mach = skl->mach; 521 struct hdac_bus *bus = skl_to_bus(skl); 522 struct platform_device *pdev; 523 int ret; 524 525 pdev = platform_device_alloc(mach->drv_name, -1); 526 if (pdev == NULL) { 527 dev_err(bus->dev, "platform device alloc failed\n"); 528 return -EIO; 529 } 530 531 mach->mach_params.platform = dev_name(bus->dev); 532 mach->mach_params.codec_mask = bus->codec_mask; 533 534 ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach)); 535 if (ret) { 536 dev_err(bus->dev, "failed to add machine device platform data\n"); 537 platform_device_put(pdev); 538 return ret; 539 } 540 541 ret = platform_device_add(pdev); 542 if (ret) { 543 dev_err(bus->dev, "failed to add machine device\n"); 544 platform_device_put(pdev); 545 return -EIO; 546 } 547 548 549 skl->i2s_dev = pdev; 550 551 return 0; 552} 553 554static void skl_machine_device_unregister(struct skl_dev *skl) 555{ 556 if (skl->i2s_dev) 557 platform_device_unregister(skl->i2s_dev); 558} 559 560static int skl_dmic_device_register(struct skl_dev *skl) 561{ 562 struct hdac_bus *bus = skl_to_bus(skl); 563 struct platform_device *pdev; 564 int ret; 565 566 /* SKL has one dmic port, so allocate dmic device for this */ 567 pdev = platform_device_alloc("dmic-codec", -1); 568 if (!pdev) { 569 dev_err(bus->dev, "failed to allocate dmic device\n"); 570 return -ENOMEM; 571 } 572 573 ret = platform_device_add(pdev); 574 if (ret) { 575 dev_err(bus->dev, "failed to add dmic device: %d\n", ret); 576 platform_device_put(pdev); 577 return ret; 578 } 579 skl->dmic_dev = pdev; 580 581 return 0; 582} 583 584static void skl_dmic_device_unregister(struct skl_dev *skl) 585{ 586 if (skl->dmic_dev) 587 platform_device_unregister(skl->dmic_dev); 588} 589 590static struct skl_clk_parent_src skl_clk_src[] = { 591 { .clk_id = SKL_XTAL, .name = "xtal" }, 592 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 }, 593 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 }, 594}; 595 596struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id) 597{ 598 unsigned int i; 599 600 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) { 601 if (skl_clk_src[i].clk_id == clk_id) 602 return &skl_clk_src[i]; 603 } 604 605 return NULL; 606} 607 608static void init_skl_xtal_rate(int pci_id) 609{ 610 switch (pci_id) { 611 case PCI_DEVICE_ID_INTEL_HDA_SKL_LP: 612 case PCI_DEVICE_ID_INTEL_HDA_KBL_LP: 613 skl_clk_src[0].rate = 24000000; 614 return; 615 616 default: 617 skl_clk_src[0].rate = 19200000; 618 return; 619 } 620} 621 622static int skl_clock_device_register(struct skl_dev *skl) 623{ 624 struct platform_device_info pdevinfo = {NULL}; 625 struct skl_clk_pdata *clk_pdata; 626 627 if (!skl->nhlt) 628 return 0; 629 630 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata), 631 GFP_KERNEL); 632 if (!clk_pdata) 633 return -ENOMEM; 634 635 init_skl_xtal_rate(skl->pci->device); 636 637 clk_pdata->parent_clks = skl_clk_src; 638 clk_pdata->ssp_clks = skl_ssp_clks; 639 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks); 640 641 /* Query NHLT to fill the rates and parent */ 642 skl_get_clks(skl, clk_pdata->ssp_clks); 643 clk_pdata->pvt_data = skl; 644 645 /* Register Platform device */ 646 pdevinfo.parent = &skl->pci->dev; 647 pdevinfo.id = -1; 648 pdevinfo.name = "skl-ssp-clk"; 649 pdevinfo.data = clk_pdata; 650 pdevinfo.size_data = sizeof(*clk_pdata); 651 skl->clk_dev = platform_device_register_full(&pdevinfo); 652 return PTR_ERR_OR_ZERO(skl->clk_dev); 653} 654 655static void skl_clock_device_unregister(struct skl_dev *skl) 656{ 657 if (skl->clk_dev) 658 platform_device_unregister(skl->clk_dev); 659} 660 661#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 662 663#define IDISP_INTEL_VENDOR_ID 0x80860000 664 665/* 666 * load the legacy codec driver 667 */ 668static void load_codec_module(struct hda_codec *codec) 669{ 670#ifdef MODULE 671 char modalias[MODULE_NAME_LEN]; 672 const char *mod = NULL; 673 674 snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias)); 675 mod = modalias; 676 dev_dbg(&codec->core.dev, "loading %s codec module\n", mod); 677 request_module(mod); 678#endif 679} 680 681#endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ 682 683static struct hda_codec *skl_codec_device_init(struct hdac_bus *bus, int addr) 684{ 685 struct hda_codec *codec; 686 int ret; 687 688 codec = snd_hda_codec_device_init(to_hda_bus(bus), addr, "ehdaudio%dD%d", bus->idx, addr); 689 if (IS_ERR(codec)) { 690 dev_err(bus->dev, "device init failed for hdac device\n"); 691 return codec; 692 } 693 694 codec->core.type = HDA_DEV_ASOC; 695 696 ret = snd_hdac_device_register(&codec->core); 697 if (ret) { 698 dev_err(bus->dev, "failed to register hdac device\n"); 699 put_device(&codec->core.dev); 700 return ERR_PTR(ret); 701 } 702 703 return codec; 704} 705 706/* 707 * Probe the given codec address 708 */ 709static int probe_codec(struct hdac_bus *bus, int addr) 710{ 711 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 712 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 713 unsigned int res = -1; 714#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 715 struct skl_dev *skl = bus_to_skl(bus); 716 struct hdac_hda_priv *hda_codec; 717#endif 718 struct hda_codec *codec; 719 720 mutex_lock(&bus->cmd_mutex); 721 snd_hdac_bus_send_cmd(bus, cmd); 722 snd_hdac_bus_get_response(bus, addr, &res); 723 mutex_unlock(&bus->cmd_mutex); 724 if (res == -1) 725 return -EIO; 726 dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res); 727 728#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 729 hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec), 730 GFP_KERNEL); 731 if (!hda_codec) 732 return -ENOMEM; 733 734 codec = skl_codec_device_init(bus, addr); 735 if (IS_ERR(codec)) 736 return PTR_ERR(codec); 737 738 hda_codec->codec = codec; 739 hda_codec->dev_index = addr; 740 dev_set_drvdata(&codec->core.dev, hda_codec); 741 742 /* use legacy bus only for HDA codecs, idisp uses ext bus */ 743 if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) { 744 codec->core.type = HDA_DEV_LEGACY; 745 load_codec_module(hda_codec->codec); 746 } 747 return 0; 748#else 749 codec = skl_codec_device_init(bus, addr); 750 return PTR_ERR_OR_ZERO(codec); 751#endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */ 752} 753 754/* Codec initialization */ 755static void skl_codec_create(struct hdac_bus *bus) 756{ 757 int c, max_slots; 758 759 max_slots = HDA_MAX_CODECS; 760 761 /* First try to probe all given codec slots */ 762 for (c = 0; c < max_slots; c++) { 763 if ((bus->codec_mask & (1 << c))) { 764 if (probe_codec(bus, c) < 0) { 765 /* 766 * Some BIOSen give you wrong codec addresses 767 * that don't exist 768 */ 769 dev_warn(bus->dev, 770 "Codec #%d probe error; disabling it...\n", c); 771 bus->codec_mask &= ~(1 << c); 772 /* 773 * More badly, accessing to a non-existing 774 * codec often screws up the controller bus, 775 * and disturbs the further communications. 776 * Thus if an error occurs during probing, 777 * better to reset the controller bus to get 778 * back to the sanity state. 779 */ 780 snd_hdac_bus_stop_chip(bus); 781 skl_init_chip(bus, true); 782 } 783 } 784 } 785} 786 787static void skl_probe_work(struct work_struct *work) 788{ 789 struct skl_dev *skl = container_of(work, struct skl_dev, probe_work); 790 struct hdac_bus *bus = skl_to_bus(skl); 791 struct hdac_ext_link *hlink; 792 int err; 793 794 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 795 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true); 796 797 skl_init_pci(skl); 798 skl_dum_set(bus); 799 800 err = skl_init_chip(bus, true); 801 if (err < 0) { 802 dev_err(bus->dev, "Init chip failed with err: %d\n", err); 803 goto out_err; 804 } 805 806 /* codec detection */ 807 if (!bus->codec_mask) 808 dev_info(bus->dev, "no hda codecs found!\n"); 809 810 /* create codec instances */ 811 skl_codec_create(bus); 812 813 /* register platform dai and controls */ 814 err = skl_platform_register(bus->dev); 815 if (err < 0) { 816 dev_err(bus->dev, "platform register failed: %d\n", err); 817 goto out_err; 818 } 819 820 err = skl_machine_device_register(skl); 821 if (err < 0) { 822 dev_err(bus->dev, "machine register failed: %d\n", err); 823 goto out_err; 824 } 825 826 /* 827 * we are done probing so decrement link counts 828 */ 829 list_for_each_entry(hlink, &bus->hlink_list, list) 830 snd_hdac_ext_bus_link_put(bus, hlink); 831 832 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 833 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 834 835 /* configure PM */ 836 pm_runtime_put_noidle(bus->dev); 837 pm_runtime_allow(bus->dev); 838 skl->init_done = 1; 839 840 return; 841 842out_err: 843 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 844 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 845} 846 847/* 848 * constructor 849 */ 850static int skl_create(struct pci_dev *pci, 851 struct skl_dev **rskl) 852{ 853 struct hdac_ext_bus_ops *ext_ops = NULL; 854 struct skl_dev *skl; 855 struct hdac_bus *bus; 856 struct hda_bus *hbus; 857 int err; 858 859 *rskl = NULL; 860 861 err = pci_enable_device(pci); 862 if (err < 0) 863 return err; 864 865 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); 866 if (!skl) { 867 pci_disable_device(pci); 868 return -ENOMEM; 869 } 870 871 hbus = skl_to_hbus(skl); 872 bus = skl_to_bus(skl); 873 874 INIT_LIST_HEAD(&skl->ppl_list); 875 INIT_LIST_HEAD(&skl->bind_list); 876 877#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 878 ext_ops = snd_soc_hdac_hda_get_ops(); 879#endif 880 snd_hdac_ext_bus_init(bus, &pci->dev, NULL, ext_ops); 881 bus->use_posbuf = 1; 882 skl->pci = pci; 883 INIT_WORK(&skl->probe_work, skl_probe_work); 884 bus->bdl_pos_adj = 0; 885 886 mutex_init(&hbus->prepare_mutex); 887 hbus->pci = pci; 888 hbus->mixer_assigned = -1; 889 hbus->modelname = "sklbus"; 890 891 *rskl = skl; 892 893 return 0; 894} 895 896static int skl_first_init(struct hdac_bus *bus) 897{ 898 struct skl_dev *skl = bus_to_skl(bus); 899 struct pci_dev *pci = skl->pci; 900 int err; 901 unsigned short gcap; 902 int cp_streams, pb_streams, start_idx; 903 904 err = pci_request_regions(pci, "Skylake HD audio"); 905 if (err < 0) 906 return err; 907 908 bus->addr = pci_resource_start(pci, 0); 909 bus->remap_addr = pci_ioremap_bar(pci, 0); 910 if (bus->remap_addr == NULL) { 911 dev_err(bus->dev, "ioremap error\n"); 912 return -ENXIO; 913 } 914 915 snd_hdac_bus_parse_capabilities(bus); 916 917 /* check if PPCAP exists */ 918 if (!bus->ppcap) { 919 dev_err(bus->dev, "bus ppcap not set, HDAudio or DSP not present?\n"); 920 return -ENODEV; 921 } 922 923 if (skl_acquire_irq(bus, 0) < 0) 924 return -EBUSY; 925 926 pci_set_master(pci); 927 synchronize_irq(bus->irq); 928 929 gcap = snd_hdac_chip_readw(bus, GCAP); 930 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); 931 932 /* read number of streams from GCAP register */ 933 cp_streams = (gcap >> 8) & 0x0f; 934 pb_streams = (gcap >> 12) & 0x0f; 935 936 if (!pb_streams && !cp_streams) { 937 dev_err(bus->dev, "no streams found in GCAP definitions?\n"); 938 return -EIO; 939 } 940 941 bus->num_streams = cp_streams + pb_streams; 942 943 /* allow 64bit DMA address if supported by H/W */ 944 if (dma_set_mask_and_coherent(bus->dev, DMA_BIT_MASK(64))) 945 dma_set_mask_and_coherent(bus->dev, DMA_BIT_MASK(32)); 946 dma_set_max_seg_size(bus->dev, UINT_MAX); 947 948 /* initialize streams */ 949 snd_hdac_ext_stream_init_all 950 (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 951 start_idx = cp_streams; 952 snd_hdac_ext_stream_init_all 953 (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 954 955 err = snd_hdac_bus_alloc_stream_pages(bus); 956 if (err < 0) 957 return err; 958 959 return 0; 960} 961 962static int skl_probe(struct pci_dev *pci, 963 const struct pci_device_id *pci_id) 964{ 965 struct skl_dev *skl; 966 struct hdac_bus *bus = NULL; 967 int err; 968 969 switch (skl_pci_binding) { 970 case SND_SKL_PCI_BIND_AUTO: 971 err = snd_intel_dsp_driver_probe(pci); 972 if (err != SND_INTEL_DSP_DRIVER_ANY && 973 err != SND_INTEL_DSP_DRIVER_SST) 974 return -ENODEV; 975 break; 976 case SND_SKL_PCI_BIND_LEGACY: 977 dev_info(&pci->dev, "Module parameter forced binding with HDAudio legacy, aborting probe\n"); 978 return -ENODEV; 979 case SND_SKL_PCI_BIND_ASOC: 980 dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n"); 981 break; 982 default: 983 dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n"); 984 break; 985 } 986 987 /* we use ext core ops, so provide NULL for ops here */ 988 err = skl_create(pci, &skl); 989 if (err < 0) 990 return err; 991 992 bus = skl_to_bus(skl); 993 994 err = skl_first_init(bus); 995 if (err < 0) { 996 dev_err(bus->dev, "skl_first_init failed with err: %d\n", err); 997 goto out_free; 998 } 999 1000 skl->pci_id = pci->device; 1001 1002 device_disable_async_suspend(bus->dev); 1003 1004 skl->nhlt = intel_nhlt_init(bus->dev); 1005 1006 if (skl->nhlt == NULL) { 1007#if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC) 1008 dev_err(bus->dev, "no nhlt info found\n"); 1009 err = -ENODEV; 1010 goto out_free; 1011#else 1012 dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDAudio codec\n"); 1013#endif 1014 } else { 1015 1016 err = skl_nhlt_create_sysfs(skl); 1017 if (err < 0) { 1018 dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err); 1019 goto out_nhlt_free; 1020 } 1021 1022 skl_nhlt_update_topology_bin(skl); 1023 1024 /* create device for dsp clk */ 1025 err = skl_clock_device_register(skl); 1026 if (err < 0) { 1027 dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err); 1028 goto out_clk_free; 1029 } 1030 } 1031 1032 pci_set_drvdata(skl->pci, bus); 1033 1034 1035 err = skl_find_machine(skl, (void *)pci_id->driver_data); 1036 if (err < 0) { 1037 dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err); 1038 goto out_nhlt_free; 1039 } 1040 1041 err = skl_init_dsp(skl); 1042 if (err < 0) { 1043 dev_dbg(bus->dev, "error failed to register dsp\n"); 1044 goto out_nhlt_free; 1045 } 1046 skl->enable_miscbdcge = skl_enable_miscbdcge; 1047 skl->clock_power_gating = skl_clock_power_gating; 1048 1049 if (bus->mlcap) 1050 snd_hdac_ext_bus_get_ml_capabilities(bus); 1051 1052 /* create device for soc dmic */ 1053 err = skl_dmic_device_register(skl); 1054 if (err < 0) { 1055 dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err); 1056 goto out_dsp_free; 1057 } 1058 1059 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { 1060 err = snd_hdac_i915_init(bus); 1061 if (err < 0) 1062 goto out_dmic_unregister; 1063 } 1064 schedule_work(&skl->probe_work); 1065 1066 return 0; 1067 1068out_dmic_unregister: 1069 skl_dmic_device_unregister(skl); 1070out_dsp_free: 1071 skl_free_dsp(skl); 1072out_clk_free: 1073 skl_clock_device_unregister(skl); 1074out_nhlt_free: 1075 if (skl->nhlt) 1076 intel_nhlt_free(skl->nhlt); 1077out_free: 1078 skl_free(bus); 1079 1080 return err; 1081} 1082 1083static void skl_shutdown(struct pci_dev *pci) 1084{ 1085 struct hdac_bus *bus = pci_get_drvdata(pci); 1086 struct hdac_stream *s; 1087 struct hdac_ext_stream *stream; 1088 struct skl_dev *skl; 1089 1090 if (!bus) 1091 return; 1092 1093 skl = bus_to_skl(bus); 1094 1095 if (!skl->init_done) 1096 return; 1097 1098 snd_hdac_stop_streams(bus); 1099 snd_hdac_ext_bus_link_power_down_all(bus); 1100 skl_dsp_sleep(skl->dsp); 1101 1102 list_for_each_entry(s, &bus->stream_list, list) { 1103 stream = stream_to_hdac_ext_stream(s); 1104 snd_hdac_ext_stream_decouple(bus, stream, false); 1105 } 1106 1107 snd_hdac_bus_stop_chip(bus); 1108} 1109 1110static void skl_remove(struct pci_dev *pci) 1111{ 1112 struct hdac_bus *bus = pci_get_drvdata(pci); 1113 struct skl_dev *skl = bus_to_skl(bus); 1114 1115 cancel_work_sync(&skl->probe_work); 1116 1117 pm_runtime_get_noresume(&pci->dev); 1118 1119 /* codec removal, invoke bus_device_remove */ 1120 snd_hdac_ext_bus_device_remove(bus); 1121 1122 skl_platform_unregister(&pci->dev); 1123 skl_free_dsp(skl); 1124 skl_machine_device_unregister(skl); 1125 skl_dmic_device_unregister(skl); 1126 skl_clock_device_unregister(skl); 1127 skl_nhlt_remove_sysfs(skl); 1128 if (skl->nhlt) 1129 intel_nhlt_free(skl->nhlt); 1130 skl_free(bus); 1131} 1132 1133/* PCI IDs */ 1134static const struct pci_device_id skl_ids[] = { 1135#if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL) 1136 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, &snd_soc_acpi_intel_skl_machines) }, 1137#endif 1138#if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL) 1139 { PCI_DEVICE_DATA(INTEL, HDA_APL, &snd_soc_acpi_intel_bxt_machines) }, 1140#endif 1141#if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL) 1142 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, &snd_soc_acpi_intel_kbl_machines) }, 1143#endif 1144#if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK) 1145 { PCI_DEVICE_DATA(INTEL, HDA_GML, &snd_soc_acpi_intel_glk_machines) }, 1146#endif 1147#if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL) 1148 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, &snd_soc_acpi_intel_cnl_machines) }, 1149#endif 1150#if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL) 1151 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, &snd_soc_acpi_intel_cnl_machines) }, 1152#endif 1153#if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_LP) 1154 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, &snd_soc_acpi_intel_cnl_machines) }, 1155#endif 1156#if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_H) 1157 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, &snd_soc_acpi_intel_cnl_machines) }, 1158#endif 1159 { 0, } 1160}; 1161MODULE_DEVICE_TABLE(pci, skl_ids); 1162 1163/* pci_driver definition */ 1164static struct pci_driver skl_driver = { 1165 .name = KBUILD_MODNAME, 1166 .id_table = skl_ids, 1167 .probe = skl_probe, 1168 .remove = skl_remove, 1169 .shutdown = skl_shutdown, 1170 .driver = { 1171 .pm = &skl_pm, 1172 }, 1173}; 1174module_pci_driver(skl_driver); 1175 1176MODULE_LICENSE("GPL v2"); 1177MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); 1178