1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2020 NXP
4 */
5
6#ifndef _FSL_AUD2HTX_H
7#define _FSL_AUD2HTX_H
8
9#define FSL_AUD2HTX_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
10			     SNDRV_PCM_FMTBIT_S32_LE)
11
12/* AUD2HTX Register Map */
13#define AUD2HTX_CTRL          0x0   /* AUD2HTX Control Register */
14#define AUD2HTX_CTRL_EXT      0x4   /* AUD2HTX Control Extended Register */
15#define AUD2HTX_WR            0x8   /* AUD2HTX Write Register */
16#define AUD2HTX_STATUS        0xC   /* AUD2HTX Status Register */
17#define AUD2HTX_IRQ_NOMASK    0x10  /* AUD2HTX Nonmasked Interrupt Flags Register */
18#define AUD2HTX_IRQ_MASKED    0x14  /* AUD2HTX Masked Interrupt Flags Register */
19#define AUD2HTX_IRQ_MASK      0x18  /* AUD2HTX IRQ Masks Register */
20
21/* AUD2HTX Control Register */
22#define AUD2HTX_CTRL_EN          BIT(0)
23
24/* AUD2HTX Control Extended Register */
25#define AUD2HTX_CTRE_DE          BIT(0)
26#define AUD2HTX_CTRE_DT_SHIFT    0x1
27#define AUD2HTX_CTRE_DT_WIDTH    0x2
28#define AUD2HTX_CTRE_DT_MASK     ((BIT(AUD2HTX_CTRE_DT_WIDTH) - 1) \
29				 << AUD2HTX_CTRE_DT_SHIFT)
30#define AUD2HTX_CTRE_WL_SHIFT    16
31#define AUD2HTX_CTRE_WL_WIDTH    5
32#define AUD2HTX_CTRE_WL_MASK     ((BIT(AUD2HTX_CTRE_WL_WIDTH) - 1) \
33				 << AUD2HTX_CTRE_WL_SHIFT)
34#define AUD2HTX_CTRE_WH_SHIFT    24
35#define AUD2HTX_CTRE_WH_WIDTH    5
36#define AUD2HTX_CTRE_WH_MASK     ((BIT(AUD2HTX_CTRE_WH_WIDTH) - 1) \
37				 << AUD2HTX_CTRE_WH_SHIFT)
38
39/* AUD2HTX IRQ Masks Register */
40#define AUD2HTX_WM_HIGH_IRQ_MASK BIT(2)
41#define AUD2HTX_WM_LOW_IRQ_MASK  BIT(1)
42#define AUD2HTX_OVF_MASK         BIT(0)
43
44#define AUD2HTX_FIFO_DEPTH       0x20
45#define AUD2HTX_WTMK_LOW         0x10
46#define AUD2HTX_WTMK_HIGH        0x10
47#define AUD2HTX_MAXBURST         0x10
48
49/**
50 * fsl_aud2htx: AUD2HTX private data
51 *
52 * @pdev: platform device pointer
53 * @regmap: regmap handler
54 * @bus_clk: clock source to access register
55 * @dma_params_rx: DMA parameters for receive channel
56 * @dma_params_tx: DMA parameters for transmit channel
57 */
58struct fsl_aud2htx {
59	struct platform_device *pdev;
60	struct regmap *regmap;
61	struct clk *bus_clk;
62
63	struct snd_dmaengine_dai_dma_data dma_params_rx;
64	struct snd_dmaengine_dai_dma_data dma_params_tx;
65};
66
67#endif /* _FSL_AUD2HTX_H */
68