1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 3// Copyright (c) 2017-2018, Linaro Limited 4 5#include <linux/module.h> 6#include <linux/init.h> 7#include <linux/platform_device.h> 8#include <linux/device.h> 9#include <linux/wait.h> 10#include <linux/bitops.h> 11#include <linux/regulator/consumer.h> 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/kernel.h> 15#include <linux/slimbus.h> 16#include <sound/soc.h> 17#include <sound/pcm_params.h> 18#include <sound/soc-dapm.h> 19#include <linux/of_gpio.h> 20#include <linux/of.h> 21#include <linux/of_irq.h> 22#include <sound/tlv.h> 23#include <sound/info.h> 24#include "wcd9335.h" 25#include "wcd-clsh-v2.h" 26 27#include <dt-bindings/sound/qcom,wcd9335.h> 28 29#define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 30 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 31 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 32/* Fractional Rates */ 33#define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100) 34#define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 35 SNDRV_PCM_FMTBIT_S24_LE) 36 37/* slave port water mark level 38 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 39 */ 40#define SLAVE_PORT_WATER_MARK_6BYTES 0 41#define SLAVE_PORT_WATER_MARK_9BYTES 1 42#define SLAVE_PORT_WATER_MARK_12BYTES 2 43#define SLAVE_PORT_WATER_MARK_15BYTES 3 44#define SLAVE_PORT_WATER_MARK_SHIFT 1 45#define SLAVE_PORT_ENABLE 1 46#define SLAVE_PORT_DISABLE 0 47#define WCD9335_SLIM_WATER_MARK_VAL \ 48 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 49 (SLAVE_PORT_ENABLE)) 50 51#define WCD9335_SLIM_NUM_PORT_REG 3 52#define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2) 53 54#define WCD9335_MCLK_CLK_12P288MHZ 12288000 55#define WCD9335_MCLK_CLK_9P6MHZ 9600000 56 57#define WCD9335_SLIM_CLOSE_TIMEOUT 1000 58#define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0) 59#define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1) 60#define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2) 61 62#define WCD9335_NUM_INTERPOLATORS 9 63#define WCD9335_RX_START 16 64#define WCD9335_SLIM_CH_START 128 65#define WCD9335_MAX_MICBIAS 4 66#define WCD9335_MAX_VALID_ADC_MUX 13 67#define WCD9335_INVALID_ADC_MUX 9 68 69#define TX_HPF_CUT_OFF_FREQ_MASK 0x60 70#define CF_MIN_3DB_4HZ 0x0 71#define CF_MIN_3DB_75HZ 0x1 72#define CF_MIN_3DB_150HZ 0x2 73#define WCD9335_DMIC_CLK_DIV_2 0x0 74#define WCD9335_DMIC_CLK_DIV_3 0x1 75#define WCD9335_DMIC_CLK_DIV_4 0x2 76#define WCD9335_DMIC_CLK_DIV_6 0x3 77#define WCD9335_DMIC_CLK_DIV_8 0x4 78#define WCD9335_DMIC_CLK_DIV_16 0x5 79#define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02 80#define WCD9335_AMIC_PWR_LEVEL_LP 0 81#define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1 82#define WCD9335_AMIC_PWR_LEVEL_HP 2 83#define WCD9335_AMIC_PWR_LVL_MASK 0x60 84#define WCD9335_AMIC_PWR_LVL_SHIFT 0x5 85 86#define WCD9335_DEC_PWR_LVL_MASK 0x06 87#define WCD9335_DEC_PWR_LVL_LP 0x02 88#define WCD9335_DEC_PWR_LVL_HP 0x04 89#define WCD9335_DEC_PWR_LVL_DF 0x00 90 91#define WCD9335_SLIM_RX_CH(p) \ 92 {.port = p + WCD9335_RX_START, .shift = p,} 93 94#define WCD9335_SLIM_TX_CH(p) \ 95 {.port = p, .shift = p,} 96 97/* vout step value */ 98#define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25) 99 100#define WCD9335_INTERPOLATOR_PATH(id) \ 101 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 102 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 103 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 104 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 105 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 106 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 107 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 108 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 109 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 110 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 111 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 112 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 113 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 114 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 115 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 116 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 117 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 118 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 119 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 120 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 121 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 122 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 123 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 124 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 125 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 126 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 127 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 128 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 129 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 130 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 131 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 132 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 133 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 134 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 135 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 136 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \ 137 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \ 138 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 139 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"} 140 141#define WCD9335_ADC_MUX_PATH(id) \ 142 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 143 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 144 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 145 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \ 146 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \ 147 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \ 148 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 149 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 150 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 151 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 152 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 153 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 154 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 155 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 156 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 157 {"AMIC MUX" #id, "ADC4", "ADC4"}, \ 158 {"AMIC MUX" #id, "ADC5", "ADC5"}, \ 159 {"AMIC MUX" #id, "ADC6", "ADC6"} 160 161enum { 162 WCD9335_RX0 = 0, 163 WCD9335_RX1, 164 WCD9335_RX2, 165 WCD9335_RX3, 166 WCD9335_RX4, 167 WCD9335_RX5, 168 WCD9335_RX6, 169 WCD9335_RX7, 170 WCD9335_RX8, 171 WCD9335_RX9, 172 WCD9335_RX10, 173 WCD9335_RX11, 174 WCD9335_RX12, 175 WCD9335_RX_MAX, 176}; 177 178enum { 179 WCD9335_TX0 = 0, 180 WCD9335_TX1, 181 WCD9335_TX2, 182 WCD9335_TX3, 183 WCD9335_TX4, 184 WCD9335_TX5, 185 WCD9335_TX6, 186 WCD9335_TX7, 187 WCD9335_TX8, 188 WCD9335_TX9, 189 WCD9335_TX10, 190 WCD9335_TX11, 191 WCD9335_TX12, 192 WCD9335_TX13, 193 WCD9335_TX14, 194 WCD9335_TX15, 195 WCD9335_TX_MAX, 196}; 197 198enum { 199 SIDO_SOURCE_INTERNAL = 0, 200 SIDO_SOURCE_RCO_BG, 201}; 202 203enum wcd9335_sido_voltage { 204 SIDO_VOLTAGE_SVS_MV = 950, 205 SIDO_VOLTAGE_NOMINAL_MV = 1100, 206}; 207 208enum { 209 COMPANDER_1, /* HPH_L */ 210 COMPANDER_2, /* HPH_R */ 211 COMPANDER_3, /* LO1_DIFF */ 212 COMPANDER_4, /* LO2_DIFF */ 213 COMPANDER_5, /* LO3_SE */ 214 COMPANDER_6, /* LO4_SE */ 215 COMPANDER_7, /* SWR SPK CH1 */ 216 COMPANDER_8, /* SWR SPK CH2 */ 217 COMPANDER_MAX, 218}; 219 220enum { 221 INTn_2_INP_SEL_ZERO = 0, 222 INTn_2_INP_SEL_RX0, 223 INTn_2_INP_SEL_RX1, 224 INTn_2_INP_SEL_RX2, 225 INTn_2_INP_SEL_RX3, 226 INTn_2_INP_SEL_RX4, 227 INTn_2_INP_SEL_RX5, 228 INTn_2_INP_SEL_RX6, 229 INTn_2_INP_SEL_RX7, 230 INTn_2_INP_SEL_PROXIMITY, 231}; 232 233enum { 234 INTn_1_MIX_INP_SEL_ZERO = 0, 235 INTn_1_MIX_INP_SEL_DEC0, 236 INTn_1_MIX_INP_SEL_DEC1, 237 INTn_1_MIX_INP_SEL_IIR0, 238 INTn_1_MIX_INP_SEL_IIR1, 239 INTn_1_MIX_INP_SEL_RX0, 240 INTn_1_MIX_INP_SEL_RX1, 241 INTn_1_MIX_INP_SEL_RX2, 242 INTn_1_MIX_INP_SEL_RX3, 243 INTn_1_MIX_INP_SEL_RX4, 244 INTn_1_MIX_INP_SEL_RX5, 245 INTn_1_MIX_INP_SEL_RX6, 246 INTn_1_MIX_INP_SEL_RX7, 247 248}; 249 250enum { 251 INTERP_EAR = 0, 252 INTERP_HPHL, 253 INTERP_HPHR, 254 INTERP_LO1, 255 INTERP_LO2, 256 INTERP_LO3, 257 INTERP_LO4, 258 INTERP_SPKR1, 259 INTERP_SPKR2, 260}; 261 262enum wcd_clock_type { 263 WCD_CLK_OFF, 264 WCD_CLK_RCO, 265 WCD_CLK_MCLK, 266}; 267 268enum { 269 MIC_BIAS_1 = 1, 270 MIC_BIAS_2, 271 MIC_BIAS_3, 272 MIC_BIAS_4 273}; 274 275enum { 276 MICB_PULLUP_ENABLE, 277 MICB_PULLUP_DISABLE, 278 MICB_ENABLE, 279 MICB_DISABLE, 280}; 281 282struct wcd9335_slim_ch { 283 u32 ch_num; 284 u16 port; 285 u16 shift; 286 struct list_head list; 287}; 288 289struct wcd_slim_codec_dai_data { 290 struct list_head slim_ch_list; 291 struct slim_stream_config sconfig; 292 struct slim_stream_runtime *sruntime; 293}; 294 295struct wcd9335_codec { 296 struct device *dev; 297 struct clk *mclk; 298 struct clk *native_clk; 299 u32 mclk_rate; 300 u8 version; 301 302 struct slim_device *slim; 303 struct slim_device *slim_ifc_dev; 304 struct regmap *regmap; 305 struct regmap *if_regmap; 306 struct regmap_irq_chip_data *irq_data; 307 308 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX]; 309 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX]; 310 u32 num_rx_port; 311 u32 num_tx_port; 312 313 int sido_input_src; 314 enum wcd9335_sido_voltage sido_voltage; 315 316 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 317 struct snd_soc_component *component; 318 319 int master_bias_users; 320 int clk_mclk_users; 321 int clk_rco_users; 322 int sido_ccl_cnt; 323 enum wcd_clock_type clk_type; 324 325 struct wcd_clsh_ctrl *clsh_ctrl; 326 u32 hph_mode; 327 int prim_int_users[WCD9335_NUM_INTERPOLATORS]; 328 329 int comp_enabled[COMPANDER_MAX]; 330 331 int intr1; 332 int reset_gpio; 333 struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY]; 334 335 unsigned int rx_port_value[WCD9335_RX_MAX]; 336 unsigned int tx_port_value[WCD9335_TX_MAX]; 337 int hph_l_gain; 338 int hph_r_gain; 339 u32 rx_bias_count; 340 341 /*TX*/ 342 int micb_ref[WCD9335_MAX_MICBIAS]; 343 int pullup_ref[WCD9335_MAX_MICBIAS]; 344 345 int dmic_0_1_clk_cnt; 346 int dmic_2_3_clk_cnt; 347 int dmic_4_5_clk_cnt; 348 int dmic_sample_rate; 349 int mad_dmic_sample_rate; 350 351 int native_clk_users; 352}; 353 354struct wcd9335_irq { 355 int irq; 356 irqreturn_t (*handler)(int irq, void *data); 357 char *name; 358}; 359 360static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = { 361 WCD9335_SLIM_TX_CH(0), 362 WCD9335_SLIM_TX_CH(1), 363 WCD9335_SLIM_TX_CH(2), 364 WCD9335_SLIM_TX_CH(3), 365 WCD9335_SLIM_TX_CH(4), 366 WCD9335_SLIM_TX_CH(5), 367 WCD9335_SLIM_TX_CH(6), 368 WCD9335_SLIM_TX_CH(7), 369 WCD9335_SLIM_TX_CH(8), 370 WCD9335_SLIM_TX_CH(9), 371 WCD9335_SLIM_TX_CH(10), 372 WCD9335_SLIM_TX_CH(11), 373 WCD9335_SLIM_TX_CH(12), 374 WCD9335_SLIM_TX_CH(13), 375 WCD9335_SLIM_TX_CH(14), 376 WCD9335_SLIM_TX_CH(15), 377}; 378 379static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = { 380 WCD9335_SLIM_RX_CH(0), /* 16 */ 381 WCD9335_SLIM_RX_CH(1), /* 17 */ 382 WCD9335_SLIM_RX_CH(2), 383 WCD9335_SLIM_RX_CH(3), 384 WCD9335_SLIM_RX_CH(4), 385 WCD9335_SLIM_RX_CH(5), 386 WCD9335_SLIM_RX_CH(6), 387 WCD9335_SLIM_RX_CH(7), 388 WCD9335_SLIM_RX_CH(8), 389 WCD9335_SLIM_RX_CH(9), 390 WCD9335_SLIM_RX_CH(10), 391 WCD9335_SLIM_RX_CH(11), 392 WCD9335_SLIM_RX_CH(12), 393}; 394 395struct interp_sample_rate { 396 int rate; 397 int rate_val; 398}; 399 400static struct interp_sample_rate int_mix_rate_val[] = { 401 {48000, 0x4}, /* 48K */ 402 {96000, 0x5}, /* 96K */ 403 {192000, 0x6}, /* 192K */ 404}; 405 406static struct interp_sample_rate int_prim_rate_val[] = { 407 {8000, 0x0}, /* 8K */ 408 {16000, 0x1}, /* 16K */ 409 {24000, -EINVAL},/* 24K */ 410 {32000, 0x3}, /* 32K */ 411 {48000, 0x4}, /* 48K */ 412 {96000, 0x5}, /* 96K */ 413 {192000, 0x6}, /* 192K */ 414 {384000, 0x7}, /* 384K */ 415 {44100, 0x8}, /* 44.1K */ 416}; 417 418struct wcd9335_reg_mask_val { 419 u16 reg; 420 u8 mask; 421 u8 val; 422}; 423 424static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = { 425 /* Rbuckfly/R_EAR(32) */ 426 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00}, 427 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60}, 428 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00}, 429 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50}, 430 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50}, 431 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08}, 432 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08}, 433 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C}, 434 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00}, 435 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40}, 436 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03}, 437 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02}, 438 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01}, 439 {WCD9335_EAR_CMBUFF, 0x08, 0x00}, 440 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 441 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 442 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 443 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 444 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80}, 445 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80}, 446 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01}, 447 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01}, 448 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01}, 449 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01}, 450 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01}, 451 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01}, 452 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01}, 453 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01}, 454 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01}, 455 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01}, 456 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01}, 457 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01}, 458 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01}, 459 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01}, 460 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01}, 461 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01}, 462 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01}, 463 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01}, 464 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01}, 465 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01}, 466 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08}, 467 {WCD9335_RCO_CTRL_2, 0x0F, 0x08}, 468 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10}, 469 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20}, 470 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A}, 471 {WCD9335_HPH_L_TEST, 0x01, 0x01}, 472 {WCD9335_HPH_R_TEST, 0x01, 0x01}, 473 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12}, 474 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08}, 475 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18}, 476 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12}, 477 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08}, 478 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18}, 479 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45}, 480 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4}, 481 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08}, 482 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02}, 483}; 484 485/* Cutoff frequency for high pass filter */ 486static const char * const cf_text[] = { 487 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 488}; 489 490static const char * const rx_cf_text[] = { 491 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 492 "CF_NEG_3DB_0P48HZ" 493}; 494 495static const char * const rx_int0_7_mix_mux_text[] = { 496 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 497 "RX6", "RX7", "PROXIMITY" 498}; 499 500static const char * const rx_int_mix_mux_text[] = { 501 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 502 "RX6", "RX7" 503}; 504 505static const char * const rx_prim_mix_text[] = { 506 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 507 "RX3", "RX4", "RX5", "RX6", "RX7" 508}; 509 510static const char * const rx_int_dem_inp_mux_text[] = { 511 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 512}; 513 514static const char * const rx_int0_interp_mux_text[] = { 515 "ZERO", "RX INT0 MIX2", 516}; 517 518static const char * const rx_int1_interp_mux_text[] = { 519 "ZERO", "RX INT1 MIX2", 520}; 521 522static const char * const rx_int2_interp_mux_text[] = { 523 "ZERO", "RX INT2 MIX2", 524}; 525 526static const char * const rx_int3_interp_mux_text[] = { 527 "ZERO", "RX INT3 MIX2", 528}; 529 530static const char * const rx_int4_interp_mux_text[] = { 531 "ZERO", "RX INT4 MIX2", 532}; 533 534static const char * const rx_int5_interp_mux_text[] = { 535 "ZERO", "RX INT5 MIX2", 536}; 537 538static const char * const rx_int6_interp_mux_text[] = { 539 "ZERO", "RX INT6 MIX2", 540}; 541 542static const char * const rx_int7_interp_mux_text[] = { 543 "ZERO", "RX INT7 MIX2", 544}; 545 546static const char * const rx_int8_interp_mux_text[] = { 547 "ZERO", "RX INT8 SEC MIX" 548}; 549 550static const char * const rx_hph_mode_mux_text[] = { 551 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 552 "Class-H Hi-Fi Low Power" 553}; 554 555static const char *const slim_rx_mux_text[] = { 556 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 557}; 558 559static const char * const adc_mux_text[] = { 560 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 561}; 562 563static const char * const dmic_mux_text[] = { 564 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 565 "SMIC0", "SMIC1", "SMIC2", "SMIC3" 566}; 567 568static const char * const dmic_mux_alt_text[] = { 569 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 570}; 571 572static const char * const amic_mux_text[] = { 573 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6" 574}; 575 576static const char * const sb_tx0_mux_text[] = { 577 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 578}; 579 580static const char * const sb_tx1_mux_text[] = { 581 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 582}; 583 584static const char * const sb_tx2_mux_text[] = { 585 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 586}; 587 588static const char * const sb_tx3_mux_text[] = { 589 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 590}; 591 592static const char * const sb_tx4_mux_text[] = { 593 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 594}; 595 596static const char * const sb_tx5_mux_text[] = { 597 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 598}; 599 600static const char * const sb_tx6_mux_text[] = { 601 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 602}; 603 604static const char * const sb_tx7_mux_text[] = { 605 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 606}; 607 608static const char * const sb_tx8_mux_text[] = { 609 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 610}; 611 612static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 613static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 614static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 615static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 616 617static const struct soc_enum cf_dec0_enum = 618 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 619 620static const struct soc_enum cf_dec1_enum = 621 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 622 623static const struct soc_enum cf_dec2_enum = 624 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 625 626static const struct soc_enum cf_dec3_enum = 627 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 628 629static const struct soc_enum cf_dec4_enum = 630 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 631 632static const struct soc_enum cf_dec5_enum = 633 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 634 635static const struct soc_enum cf_dec6_enum = 636 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 637 638static const struct soc_enum cf_dec7_enum = 639 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 640 641static const struct soc_enum cf_dec8_enum = 642 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 643 644static const struct soc_enum cf_int0_1_enum = 645 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 646 647static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2, 648 rx_cf_text); 649 650static const struct soc_enum cf_int1_1_enum = 651 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 652 653static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2, 654 rx_cf_text); 655 656static const struct soc_enum cf_int2_1_enum = 657 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 658 659static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2, 660 rx_cf_text); 661 662static const struct soc_enum cf_int3_1_enum = 663 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 664 665static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2, 666 rx_cf_text); 667 668static const struct soc_enum cf_int4_1_enum = 669 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 670 671static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2, 672 rx_cf_text); 673 674static const struct soc_enum cf_int5_1_enum = 675 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text); 676 677static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2, 678 rx_cf_text); 679 680static const struct soc_enum cf_int6_1_enum = 681 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text); 682 683static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2, 684 rx_cf_text); 685 686static const struct soc_enum cf_int7_1_enum = 687 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 688 689static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2, 690 rx_cf_text); 691 692static const struct soc_enum cf_int8_1_enum = 693 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 694 695static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2, 696 rx_cf_text); 697 698static const struct soc_enum rx_hph_mode_mux_enum = 699 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 700 rx_hph_mode_mux_text); 701 702static const struct soc_enum slim_rx_mux_enum = 703 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 704 705static const struct soc_enum rx_int0_2_mux_chain_enum = 706 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 707 rx_int0_7_mix_mux_text); 708 709static const struct soc_enum rx_int1_2_mux_chain_enum = 710 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 711 rx_int_mix_mux_text); 712 713static const struct soc_enum rx_int2_2_mux_chain_enum = 714 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 715 rx_int_mix_mux_text); 716 717static const struct soc_enum rx_int3_2_mux_chain_enum = 718 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 719 rx_int_mix_mux_text); 720 721static const struct soc_enum rx_int4_2_mux_chain_enum = 722 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 723 rx_int_mix_mux_text); 724 725static const struct soc_enum rx_int5_2_mux_chain_enum = 726 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9, 727 rx_int_mix_mux_text); 728 729static const struct soc_enum rx_int6_2_mux_chain_enum = 730 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9, 731 rx_int_mix_mux_text); 732 733static const struct soc_enum rx_int7_2_mux_chain_enum = 734 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 735 rx_int0_7_mix_mux_text); 736 737static const struct soc_enum rx_int8_2_mux_chain_enum = 738 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 739 rx_int_mix_mux_text); 740 741static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 742 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 743 rx_prim_mix_text); 744 745static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 746 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 747 rx_prim_mix_text); 748 749static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 750 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 751 rx_prim_mix_text); 752 753static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 754 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 755 rx_prim_mix_text); 756 757static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 758 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 759 rx_prim_mix_text); 760 761static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 762 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 763 rx_prim_mix_text); 764 765static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 766 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 767 rx_prim_mix_text); 768 769static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 770 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 771 rx_prim_mix_text); 772 773static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 774 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 775 rx_prim_mix_text); 776 777static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 778 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 779 rx_prim_mix_text); 780 781static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 782 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 783 rx_prim_mix_text); 784 785static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 786 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 787 rx_prim_mix_text); 788 789static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 790 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 791 rx_prim_mix_text); 792 793static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 794 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 795 rx_prim_mix_text); 796 797static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 798 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 799 rx_prim_mix_text); 800 801static const struct soc_enum rx_int5_1_mix_inp0_chain_enum = 802 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13, 803 rx_prim_mix_text); 804 805static const struct soc_enum rx_int5_1_mix_inp1_chain_enum = 806 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13, 807 rx_prim_mix_text); 808 809static const struct soc_enum rx_int5_1_mix_inp2_chain_enum = 810 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13, 811 rx_prim_mix_text); 812 813static const struct soc_enum rx_int6_1_mix_inp0_chain_enum = 814 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13, 815 rx_prim_mix_text); 816 817static const struct soc_enum rx_int6_1_mix_inp1_chain_enum = 818 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13, 819 rx_prim_mix_text); 820 821static const struct soc_enum rx_int6_1_mix_inp2_chain_enum = 822 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13, 823 rx_prim_mix_text); 824 825static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 826 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 827 rx_prim_mix_text); 828 829static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 830 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 831 rx_prim_mix_text); 832 833static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 834 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 835 rx_prim_mix_text); 836 837static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 838 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 839 rx_prim_mix_text); 840 841static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 842 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 843 rx_prim_mix_text); 844 845static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 846 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 847 rx_prim_mix_text); 848 849static const struct soc_enum rx_int0_dem_inp_mux_enum = 850 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0, 851 ARRAY_SIZE(rx_int_dem_inp_mux_text), 852 rx_int_dem_inp_mux_text); 853 854static const struct soc_enum rx_int1_dem_inp_mux_enum = 855 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0, 856 ARRAY_SIZE(rx_int_dem_inp_mux_text), 857 rx_int_dem_inp_mux_text); 858 859static const struct soc_enum rx_int2_dem_inp_mux_enum = 860 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0, 861 ARRAY_SIZE(rx_int_dem_inp_mux_text), 862 rx_int_dem_inp_mux_text); 863 864static const struct soc_enum rx_int0_interp_mux_enum = 865 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2, 866 rx_int0_interp_mux_text); 867 868static const struct soc_enum rx_int1_interp_mux_enum = 869 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2, 870 rx_int1_interp_mux_text); 871 872static const struct soc_enum rx_int2_interp_mux_enum = 873 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2, 874 rx_int2_interp_mux_text); 875 876static const struct soc_enum rx_int3_interp_mux_enum = 877 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2, 878 rx_int3_interp_mux_text); 879 880static const struct soc_enum rx_int4_interp_mux_enum = 881 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2, 882 rx_int4_interp_mux_text); 883 884static const struct soc_enum rx_int5_interp_mux_enum = 885 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2, 886 rx_int5_interp_mux_text); 887 888static const struct soc_enum rx_int6_interp_mux_enum = 889 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2, 890 rx_int6_interp_mux_text); 891 892static const struct soc_enum rx_int7_interp_mux_enum = 893 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2, 894 rx_int7_interp_mux_text); 895 896static const struct soc_enum rx_int8_interp_mux_enum = 897 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2, 898 rx_int8_interp_mux_text); 899 900static const struct soc_enum tx_adc_mux0_chain_enum = 901 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4, 902 adc_mux_text); 903 904static const struct soc_enum tx_adc_mux1_chain_enum = 905 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4, 906 adc_mux_text); 907 908static const struct soc_enum tx_adc_mux2_chain_enum = 909 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4, 910 adc_mux_text); 911 912static const struct soc_enum tx_adc_mux3_chain_enum = 913 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4, 914 adc_mux_text); 915 916static const struct soc_enum tx_adc_mux4_chain_enum = 917 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4, 918 adc_mux_text); 919 920static const struct soc_enum tx_adc_mux5_chain_enum = 921 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4, 922 adc_mux_text); 923 924static const struct soc_enum tx_adc_mux6_chain_enum = 925 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4, 926 adc_mux_text); 927 928static const struct soc_enum tx_adc_mux7_chain_enum = 929 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4, 930 adc_mux_text); 931 932static const struct soc_enum tx_adc_mux8_chain_enum = 933 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4, 934 adc_mux_text); 935 936static const struct soc_enum tx_dmic_mux0_enum = 937 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11, 938 dmic_mux_text); 939 940static const struct soc_enum tx_dmic_mux1_enum = 941 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11, 942 dmic_mux_text); 943 944static const struct soc_enum tx_dmic_mux2_enum = 945 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11, 946 dmic_mux_text); 947 948static const struct soc_enum tx_dmic_mux3_enum = 949 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11, 950 dmic_mux_text); 951 952static const struct soc_enum tx_dmic_mux4_enum = 953 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 954 dmic_mux_alt_text); 955 956static const struct soc_enum tx_dmic_mux5_enum = 957 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 958 dmic_mux_alt_text); 959 960static const struct soc_enum tx_dmic_mux6_enum = 961 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 962 dmic_mux_alt_text); 963 964static const struct soc_enum tx_dmic_mux7_enum = 965 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 966 dmic_mux_alt_text); 967 968static const struct soc_enum tx_dmic_mux8_enum = 969 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 970 dmic_mux_alt_text); 971 972static const struct soc_enum tx_amic_mux0_enum = 973 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7, 974 amic_mux_text); 975 976static const struct soc_enum tx_amic_mux1_enum = 977 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7, 978 amic_mux_text); 979 980static const struct soc_enum tx_amic_mux2_enum = 981 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7, 982 amic_mux_text); 983 984static const struct soc_enum tx_amic_mux3_enum = 985 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7, 986 amic_mux_text); 987 988static const struct soc_enum tx_amic_mux4_enum = 989 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7, 990 amic_mux_text); 991 992static const struct soc_enum tx_amic_mux5_enum = 993 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7, 994 amic_mux_text); 995 996static const struct soc_enum tx_amic_mux6_enum = 997 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7, 998 amic_mux_text); 999 1000static const struct soc_enum tx_amic_mux7_enum = 1001 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7, 1002 amic_mux_text); 1003 1004static const struct soc_enum tx_amic_mux8_enum = 1005 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7, 1006 amic_mux_text); 1007 1008static const struct soc_enum sb_tx0_mux_enum = 1009 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4, 1010 sb_tx0_mux_text); 1011 1012static const struct soc_enum sb_tx1_mux_enum = 1013 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4, 1014 sb_tx1_mux_text); 1015 1016static const struct soc_enum sb_tx2_mux_enum = 1017 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4, 1018 sb_tx2_mux_text); 1019 1020static const struct soc_enum sb_tx3_mux_enum = 1021 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4, 1022 sb_tx3_mux_text); 1023 1024static const struct soc_enum sb_tx4_mux_enum = 1025 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4, 1026 sb_tx4_mux_text); 1027 1028static const struct soc_enum sb_tx5_mux_enum = 1029 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4, 1030 sb_tx5_mux_text); 1031 1032static const struct soc_enum sb_tx6_mux_enum = 1033 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4, 1034 sb_tx6_mux_text); 1035 1036static const struct soc_enum sb_tx7_mux_enum = 1037 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4, 1038 sb_tx7_mux_text); 1039 1040static const struct soc_enum sb_tx8_mux_enum = 1041 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4, 1042 sb_tx8_mux_text); 1043 1044static const struct snd_kcontrol_new rx_int0_2_mux = 1045 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 1046 1047static const struct snd_kcontrol_new rx_int1_2_mux = 1048 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 1049 1050static const struct snd_kcontrol_new rx_int2_2_mux = 1051 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 1052 1053static const struct snd_kcontrol_new rx_int3_2_mux = 1054 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 1055 1056static const struct snd_kcontrol_new rx_int4_2_mux = 1057 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 1058 1059static const struct snd_kcontrol_new rx_int5_2_mux = 1060 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum); 1061 1062static const struct snd_kcontrol_new rx_int6_2_mux = 1063 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum); 1064 1065static const struct snd_kcontrol_new rx_int7_2_mux = 1066 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 1067 1068static const struct snd_kcontrol_new rx_int8_2_mux = 1069 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 1070 1071static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 1072 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 1073 1074static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 1075 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 1076 1077static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 1078 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 1079 1080static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 1081 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 1082 1083static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 1084 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 1085 1086static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 1087 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 1088 1089static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 1090 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 1091 1092static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 1093 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 1094 1095static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 1096 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 1097 1098static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 1099 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 1100 1101static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 1102 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 1103 1104static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 1105 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 1106 1107static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 1108 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 1109 1110static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 1111 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 1112 1113static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 1114 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 1115 1116static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux = 1117 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum); 1118 1119static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux = 1120 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum); 1121 1122static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux = 1123 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum); 1124 1125static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux = 1126 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum); 1127 1128static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux = 1129 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum); 1130 1131static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux = 1132 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum); 1133 1134static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 1135 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 1136 1137static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 1138 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 1139 1140static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 1141 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 1142 1143static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 1144 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 1145 1146static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 1147 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 1148 1149static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 1150 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 1151 1152static const struct snd_kcontrol_new rx_int0_interp_mux = 1153 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum); 1154 1155static const struct snd_kcontrol_new rx_int1_interp_mux = 1156 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum); 1157 1158static const struct snd_kcontrol_new rx_int2_interp_mux = 1159 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum); 1160 1161static const struct snd_kcontrol_new rx_int3_interp_mux = 1162 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum); 1163 1164static const struct snd_kcontrol_new rx_int4_interp_mux = 1165 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum); 1166 1167static const struct snd_kcontrol_new rx_int5_interp_mux = 1168 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum); 1169 1170static const struct snd_kcontrol_new rx_int6_interp_mux = 1171 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum); 1172 1173static const struct snd_kcontrol_new rx_int7_interp_mux = 1174 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum); 1175 1176static const struct snd_kcontrol_new rx_int8_interp_mux = 1177 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum); 1178 1179static const struct snd_kcontrol_new tx_dmic_mux0 = 1180 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 1181 1182static const struct snd_kcontrol_new tx_dmic_mux1 = 1183 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 1184 1185static const struct snd_kcontrol_new tx_dmic_mux2 = 1186 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 1187 1188static const struct snd_kcontrol_new tx_dmic_mux3 = 1189 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 1190 1191static const struct snd_kcontrol_new tx_dmic_mux4 = 1192 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 1193 1194static const struct snd_kcontrol_new tx_dmic_mux5 = 1195 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 1196 1197static const struct snd_kcontrol_new tx_dmic_mux6 = 1198 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 1199 1200static const struct snd_kcontrol_new tx_dmic_mux7 = 1201 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 1202 1203static const struct snd_kcontrol_new tx_dmic_mux8 = 1204 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 1205 1206static const struct snd_kcontrol_new tx_amic_mux0 = 1207 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 1208 1209static const struct snd_kcontrol_new tx_amic_mux1 = 1210 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 1211 1212static const struct snd_kcontrol_new tx_amic_mux2 = 1213 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 1214 1215static const struct snd_kcontrol_new tx_amic_mux3 = 1216 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 1217 1218static const struct snd_kcontrol_new tx_amic_mux4 = 1219 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 1220 1221static const struct snd_kcontrol_new tx_amic_mux5 = 1222 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 1223 1224static const struct snd_kcontrol_new tx_amic_mux6 = 1225 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 1226 1227static const struct snd_kcontrol_new tx_amic_mux7 = 1228 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 1229 1230static const struct snd_kcontrol_new tx_amic_mux8 = 1231 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 1232 1233static const struct snd_kcontrol_new sb_tx0_mux = 1234 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum); 1235 1236static const struct snd_kcontrol_new sb_tx1_mux = 1237 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum); 1238 1239static const struct snd_kcontrol_new sb_tx2_mux = 1240 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum); 1241 1242static const struct snd_kcontrol_new sb_tx3_mux = 1243 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum); 1244 1245static const struct snd_kcontrol_new sb_tx4_mux = 1246 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum); 1247 1248static const struct snd_kcontrol_new sb_tx5_mux = 1249 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum); 1250 1251static const struct snd_kcontrol_new sb_tx6_mux = 1252 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum); 1253 1254static const struct snd_kcontrol_new sb_tx7_mux = 1255 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum); 1256 1257static const struct snd_kcontrol_new sb_tx8_mux = 1258 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum); 1259 1260static int slim_rx_mux_get(struct snd_kcontrol *kc, 1261 struct snd_ctl_elem_value *ucontrol) 1262{ 1263 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1264 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1265 u32 port_id = w->shift; 1266 1267 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id]; 1268 1269 return 0; 1270} 1271 1272static int slim_rx_mux_put(struct snd_kcontrol *kc, 1273 struct snd_ctl_elem_value *ucontrol) 1274{ 1275 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1276 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1277 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1278 struct snd_soc_dapm_update *update = NULL; 1279 u32 port_id = w->shift; 1280 1281 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0]) 1282 return 0; 1283 1284 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0]; 1285 1286 /* Remove channel from any list it's in before adding it to a new one */ 1287 list_del_init(&wcd->rx_chs[port_id].list); 1288 1289 switch (wcd->rx_port_value[port_id]) { 1290 case 0: 1291 /* Channel already removed from lists. Nothing to do here */ 1292 break; 1293 case 1: 1294 list_add_tail(&wcd->rx_chs[port_id].list, 1295 &wcd->dai[AIF1_PB].slim_ch_list); 1296 break; 1297 case 2: 1298 list_add_tail(&wcd->rx_chs[port_id].list, 1299 &wcd->dai[AIF2_PB].slim_ch_list); 1300 break; 1301 case 3: 1302 list_add_tail(&wcd->rx_chs[port_id].list, 1303 &wcd->dai[AIF3_PB].slim_ch_list); 1304 break; 1305 case 4: 1306 list_add_tail(&wcd->rx_chs[port_id].list, 1307 &wcd->dai[AIF4_PB].slim_ch_list); 1308 break; 1309 default: 1310 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]); 1311 goto err; 1312 } 1313 1314 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 1315 e, update); 1316 1317 return 0; 1318err: 1319 return -EINVAL; 1320} 1321 1322static int slim_tx_mixer_get(struct snd_kcontrol *kc, 1323 struct snd_ctl_elem_value *ucontrol) 1324{ 1325 1326 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1327 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev); 1328 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 1329 struct soc_mixer_control *mixer = 1330 (struct soc_mixer_control *)kc->private_value; 1331 int dai_id = widget->shift; 1332 int port_id = mixer->shift; 1333 1334 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id] == dai_id; 1335 1336 return 0; 1337} 1338 1339static int slim_tx_mixer_put(struct snd_kcontrol *kc, 1340 struct snd_ctl_elem_value *ucontrol) 1341{ 1342 1343 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 1344 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev); 1345 struct snd_soc_dapm_update *update = NULL; 1346 struct soc_mixer_control *mixer = 1347 (struct soc_mixer_control *)kc->private_value; 1348 int enable = ucontrol->value.integer.value[0]; 1349 int dai_id = widget->shift; 1350 int port_id = mixer->shift; 1351 1352 switch (dai_id) { 1353 case AIF1_CAP: 1354 case AIF2_CAP: 1355 case AIF3_CAP: 1356 /* only add to the list if value not set */ 1357 if (enable && wcd->tx_port_value[port_id] != dai_id) { 1358 wcd->tx_port_value[port_id] = dai_id; 1359 list_add_tail(&wcd->tx_chs[port_id].list, 1360 &wcd->dai[dai_id].slim_ch_list); 1361 } else if (!enable && wcd->tx_port_value[port_id] == dai_id) { 1362 wcd->tx_port_value[port_id] = -1; 1363 list_del_init(&wcd->tx_chs[port_id].list); 1364 } 1365 break; 1366 default: 1367 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id); 1368 return -EINVAL; 1369 } 1370 1371 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 1372 1373 return 0; 1374} 1375 1376static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = { 1377 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 1378 slim_rx_mux_get, slim_rx_mux_put), 1379 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 1380 slim_rx_mux_get, slim_rx_mux_put), 1381 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 1382 slim_rx_mux_get, slim_rx_mux_put), 1383 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 1384 slim_rx_mux_get, slim_rx_mux_put), 1385 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 1386 slim_rx_mux_get, slim_rx_mux_put), 1387 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 1388 slim_rx_mux_get, slim_rx_mux_put), 1389 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 1390 slim_rx_mux_get, slim_rx_mux_put), 1391 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 1392 slim_rx_mux_get, slim_rx_mux_put), 1393}; 1394 1395static const struct snd_kcontrol_new aif1_cap_mixer[] = { 1396 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1397 slim_tx_mixer_get, slim_tx_mixer_put), 1398 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1399 slim_tx_mixer_get, slim_tx_mixer_put), 1400 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1401 slim_tx_mixer_get, slim_tx_mixer_put), 1402 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1403 slim_tx_mixer_get, slim_tx_mixer_put), 1404 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1405 slim_tx_mixer_get, slim_tx_mixer_put), 1406 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1407 slim_tx_mixer_get, slim_tx_mixer_put), 1408 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1409 slim_tx_mixer_get, slim_tx_mixer_put), 1410 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1411 slim_tx_mixer_get, slim_tx_mixer_put), 1412 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1413 slim_tx_mixer_get, slim_tx_mixer_put), 1414 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1415 slim_tx_mixer_get, slim_tx_mixer_put), 1416 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1417 slim_tx_mixer_get, slim_tx_mixer_put), 1418 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1419 slim_tx_mixer_get, slim_tx_mixer_put), 1420 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1421 slim_tx_mixer_get, slim_tx_mixer_put), 1422}; 1423 1424static const struct snd_kcontrol_new aif2_cap_mixer[] = { 1425 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1426 slim_tx_mixer_get, slim_tx_mixer_put), 1427 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1428 slim_tx_mixer_get, slim_tx_mixer_put), 1429 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1430 slim_tx_mixer_get, slim_tx_mixer_put), 1431 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1432 slim_tx_mixer_get, slim_tx_mixer_put), 1433 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1434 slim_tx_mixer_get, slim_tx_mixer_put), 1435 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1436 slim_tx_mixer_get, slim_tx_mixer_put), 1437 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1438 slim_tx_mixer_get, slim_tx_mixer_put), 1439 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1440 slim_tx_mixer_get, slim_tx_mixer_put), 1441 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1442 slim_tx_mixer_get, slim_tx_mixer_put), 1443 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1444 slim_tx_mixer_get, slim_tx_mixer_put), 1445 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1446 slim_tx_mixer_get, slim_tx_mixer_put), 1447 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1448 slim_tx_mixer_get, slim_tx_mixer_put), 1449 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1450 slim_tx_mixer_get, slim_tx_mixer_put), 1451}; 1452 1453static const struct snd_kcontrol_new aif3_cap_mixer[] = { 1454 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1455 slim_tx_mixer_get, slim_tx_mixer_put), 1456 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1457 slim_tx_mixer_get, slim_tx_mixer_put), 1458 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1459 slim_tx_mixer_get, slim_tx_mixer_put), 1460 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1461 slim_tx_mixer_get, slim_tx_mixer_put), 1462 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1463 slim_tx_mixer_get, slim_tx_mixer_put), 1464 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1465 slim_tx_mixer_get, slim_tx_mixer_put), 1466 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1467 slim_tx_mixer_get, slim_tx_mixer_put), 1468 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1469 slim_tx_mixer_get, slim_tx_mixer_put), 1470 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1471 slim_tx_mixer_get, slim_tx_mixer_put), 1472}; 1473 1474static int wcd9335_put_dec_enum(struct snd_kcontrol *kc, 1475 struct snd_ctl_elem_value *ucontrol) 1476{ 1477 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1478 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1479 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1480 unsigned int val, reg, sel; 1481 1482 val = ucontrol->value.enumerated.item[0]; 1483 1484 switch (e->reg) { 1485 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 1486 reg = WCD9335_CDC_TX0_TX_PATH_CFG0; 1487 break; 1488 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 1489 reg = WCD9335_CDC_TX1_TX_PATH_CFG0; 1490 break; 1491 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 1492 reg = WCD9335_CDC_TX2_TX_PATH_CFG0; 1493 break; 1494 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 1495 reg = WCD9335_CDC_TX3_TX_PATH_CFG0; 1496 break; 1497 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0: 1498 reg = WCD9335_CDC_TX4_TX_PATH_CFG0; 1499 break; 1500 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0: 1501 reg = WCD9335_CDC_TX5_TX_PATH_CFG0; 1502 break; 1503 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0: 1504 reg = WCD9335_CDC_TX6_TX_PATH_CFG0; 1505 break; 1506 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0: 1507 reg = WCD9335_CDC_TX7_TX_PATH_CFG0; 1508 break; 1509 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0: 1510 reg = WCD9335_CDC_TX8_TX_PATH_CFG0; 1511 break; 1512 default: 1513 return -EINVAL; 1514 } 1515 1516 /* AMIC: 0, DMIC: 1 */ 1517 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL; 1518 snd_soc_component_update_bits(component, reg, 1519 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK, 1520 sel); 1521 1522 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1523} 1524 1525static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc, 1526 struct snd_ctl_elem_value *ucontrol) 1527{ 1528 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1529 struct snd_soc_component *component; 1530 int reg, val; 1531 1532 component = snd_soc_dapm_kcontrol_component(kc); 1533 val = ucontrol->value.enumerated.item[0]; 1534 1535 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0) 1536 reg = WCD9335_CDC_RX0_RX_PATH_CFG0; 1537 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0) 1538 reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 1539 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0) 1540 reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 1541 else 1542 return -EINVAL; 1543 1544 /* Set Look Ahead Delay */ 1545 snd_soc_component_update_bits(component, reg, 1546 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK, 1547 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0); 1548 /* Set DEM INP Select */ 1549 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1550} 1551 1552static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 1553 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 1554 snd_soc_dapm_get_enum_double, 1555 wcd9335_int_dem_inp_mux_put); 1556 1557static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 1558 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 1559 snd_soc_dapm_get_enum_double, 1560 wcd9335_int_dem_inp_mux_put); 1561 1562static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 1563 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 1564 snd_soc_dapm_get_enum_double, 1565 wcd9335_int_dem_inp_mux_put); 1566 1567static const struct snd_kcontrol_new tx_adc_mux0 = 1568 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum, 1569 snd_soc_dapm_get_enum_double, 1570 wcd9335_put_dec_enum); 1571 1572static const struct snd_kcontrol_new tx_adc_mux1 = 1573 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum, 1574 snd_soc_dapm_get_enum_double, 1575 wcd9335_put_dec_enum); 1576 1577static const struct snd_kcontrol_new tx_adc_mux2 = 1578 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum, 1579 snd_soc_dapm_get_enum_double, 1580 wcd9335_put_dec_enum); 1581 1582static const struct snd_kcontrol_new tx_adc_mux3 = 1583 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum, 1584 snd_soc_dapm_get_enum_double, 1585 wcd9335_put_dec_enum); 1586 1587static const struct snd_kcontrol_new tx_adc_mux4 = 1588 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum, 1589 snd_soc_dapm_get_enum_double, 1590 wcd9335_put_dec_enum); 1591 1592static const struct snd_kcontrol_new tx_adc_mux5 = 1593 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum, 1594 snd_soc_dapm_get_enum_double, 1595 wcd9335_put_dec_enum); 1596 1597static const struct snd_kcontrol_new tx_adc_mux6 = 1598 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum, 1599 snd_soc_dapm_get_enum_double, 1600 wcd9335_put_dec_enum); 1601 1602static const struct snd_kcontrol_new tx_adc_mux7 = 1603 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum, 1604 snd_soc_dapm_get_enum_double, 1605 wcd9335_put_dec_enum); 1606 1607static const struct snd_kcontrol_new tx_adc_mux8 = 1608 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum, 1609 snd_soc_dapm_get_enum_double, 1610 wcd9335_put_dec_enum); 1611 1612static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1613 int rate_val, 1614 u32 rate) 1615{ 1616 struct snd_soc_component *component = dai->component; 1617 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 1618 struct wcd9335_slim_ch *ch; 1619 int val, j; 1620 1621 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1622 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1623 val = snd_soc_component_read(component, 1624 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1625 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1626 1627 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) 1628 snd_soc_component_update_bits(component, 1629 WCD9335_CDC_RX_PATH_MIX_CTL(j), 1630 WCD9335_CDC_MIX_PCM_RATE_MASK, 1631 rate_val); 1632 } 1633 } 1634 1635 return 0; 1636} 1637 1638static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1639 u8 rate_val, 1640 u32 rate) 1641{ 1642 struct snd_soc_component *comp = dai->component; 1643 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 1644 struct wcd9335_slim_ch *ch; 1645 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1646 int inp, j; 1647 1648 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1649 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0; 1650 /* 1651 * Loop through all interpolator MUX inputs and find out 1652 * to which interpolator input, the slim rx port 1653 * is connected 1654 */ 1655 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1656 cfg0 = snd_soc_component_read(comp, 1657 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1658 cfg1 = snd_soc_component_read(comp, 1659 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1660 1661 inp0_sel = cfg0 & 1662 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1663 inp1_sel = (cfg0 >> 4) & 1664 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1665 inp2_sel = (cfg1 >> 4) & 1666 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1667 1668 if ((inp0_sel == inp) || (inp1_sel == inp) || 1669 (inp2_sel == inp)) { 1670 /* rate is in Hz */ 1671 if ((j == 0) && (rate == 44100)) 1672 dev_info(wcd->dev, 1673 "Cannot set 44.1KHz on INT0\n"); 1674 else 1675 snd_soc_component_update_bits(comp, 1676 WCD9335_CDC_RX_PATH_CTL(j), 1677 WCD9335_CDC_MIX_PCM_RATE_MASK, 1678 rate_val); 1679 } 1680 } 1681 } 1682 1683 return 0; 1684} 1685 1686static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate) 1687{ 1688 int i; 1689 1690 /* set mixing path rate */ 1691 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) { 1692 if (rate == int_mix_rate_val[i].rate) { 1693 wcd9335_set_mix_interpolator_rate(dai, 1694 int_mix_rate_val[i].rate_val, rate); 1695 break; 1696 } 1697 } 1698 1699 /* set primary path sample rate */ 1700 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) { 1701 if (rate == int_prim_rate_val[i].rate) { 1702 wcd9335_set_prim_interpolator_rate(dai, 1703 int_prim_rate_val[i].rate_val, rate); 1704 break; 1705 } 1706 } 1707 1708 return 0; 1709} 1710 1711static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd, 1712 struct wcd_slim_codec_dai_data *dai_data, 1713 int direction) 1714{ 1715 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1716 struct slim_stream_config *cfg = &dai_data->sconfig; 1717 struct wcd9335_slim_ch *ch; 1718 u16 payload = 0; 1719 int ret, i; 1720 1721 cfg->ch_count = 0; 1722 cfg->direction = direction; 1723 cfg->port_mask = 0; 1724 1725 /* Configure slave interface device */ 1726 list_for_each_entry(ch, slim_ch_list, list) { 1727 cfg->ch_count++; 1728 payload |= 1 << ch->shift; 1729 cfg->port_mask |= BIT(ch->port); 1730 } 1731 1732 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1733 if (!cfg->chs) 1734 return -ENOMEM; 1735 1736 i = 0; 1737 list_for_each_entry(ch, slim_ch_list, list) { 1738 cfg->chs[i++] = ch->ch_num; 1739 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1740 /* write to interface device */ 1741 ret = regmap_write(wcd->if_regmap, 1742 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1743 payload); 1744 1745 if (ret < 0) 1746 goto err; 1747 1748 /* configure the slave port for water mark and enable*/ 1749 ret = regmap_write(wcd->if_regmap, 1750 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port), 1751 WCD9335_SLIM_WATER_MARK_VAL); 1752 if (ret < 0) 1753 goto err; 1754 } else { 1755 ret = regmap_write(wcd->if_regmap, 1756 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1757 payload & 0x00FF); 1758 if (ret < 0) 1759 goto err; 1760 1761 /* ports 8,9 */ 1762 ret = regmap_write(wcd->if_regmap, 1763 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1764 (payload & 0xFF00)>>8); 1765 if (ret < 0) 1766 goto err; 1767 1768 /* configure the slave port for water mark and enable*/ 1769 ret = regmap_write(wcd->if_regmap, 1770 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port), 1771 WCD9335_SLIM_WATER_MARK_VAL); 1772 1773 if (ret < 0) 1774 goto err; 1775 } 1776 } 1777 1778 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM"); 1779 1780 return 0; 1781 1782err: 1783 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1784 kfree(cfg->chs); 1785 cfg->chs = NULL; 1786 1787 return ret; 1788} 1789 1790static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai, 1791 u8 rate_val, u32 rate) 1792{ 1793 struct snd_soc_component *comp = dai->component; 1794 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 1795 u8 shift = 0, shift_val = 0, tx_mux_sel; 1796 struct wcd9335_slim_ch *ch; 1797 int tx_port, tx_port_reg; 1798 int decimator = -1; 1799 1800 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1801 tx_port = ch->port; 1802 if ((tx_port == 12) || (tx_port >= 14)) { 1803 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1804 tx_port, dai->id); 1805 return -EINVAL; 1806 } 1807 /* Find the SB TX MUX input - which decimator is connected */ 1808 if (tx_port < 4) { 1809 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0; 1810 shift = (tx_port << 1); 1811 shift_val = 0x03; 1812 } else if (tx_port < 8) { 1813 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1; 1814 shift = ((tx_port - 4) << 1); 1815 shift_val = 0x03; 1816 } else if (tx_port < 11) { 1817 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2; 1818 shift = ((tx_port - 8) << 1); 1819 shift_val = 0x03; 1820 } else if (tx_port == 11) { 1821 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1822 shift = 0; 1823 shift_val = 0x0F; 1824 } else /* (tx_port == 13) */ { 1825 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1826 shift = 4; 1827 shift_val = 0x03; 1828 } 1829 1830 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1831 (shift_val << shift); 1832 1833 tx_mux_sel = tx_mux_sel >> shift; 1834 if (tx_port <= 8) { 1835 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1836 decimator = tx_port; 1837 } else if (tx_port <= 10) { 1838 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1839 decimator = ((tx_port == 9) ? 7 : 6); 1840 } else if (tx_port == 11) { 1841 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1842 decimator = tx_mux_sel - 1; 1843 } else if (tx_port == 13) { 1844 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1845 decimator = 5; 1846 } 1847 1848 if (decimator >= 0) { 1849 snd_soc_component_update_bits(comp, 1850 WCD9335_CDC_TX_PATH_CTL(decimator), 1851 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1852 rate_val); 1853 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) { 1854 /* Check if the TX Mux input is RX MIX TXn */ 1855 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n", 1856 tx_port, tx_port); 1857 } else { 1858 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n", 1859 decimator); 1860 return -EINVAL; 1861 } 1862 } 1863 1864 return 0; 1865} 1866 1867static int wcd9335_hw_params(struct snd_pcm_substream *substream, 1868 struct snd_pcm_hw_params *params, 1869 struct snd_soc_dai *dai) 1870{ 1871 struct wcd9335_codec *wcd; 1872 int ret, tx_fs_rate = 0; 1873 1874 wcd = snd_soc_component_get_drvdata(dai->component); 1875 1876 switch (substream->stream) { 1877 case SNDRV_PCM_STREAM_PLAYBACK: 1878 ret = wcd9335_set_interpolator_rate(dai, params_rate(params)); 1879 if (ret) { 1880 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1881 params_rate(params)); 1882 return ret; 1883 } 1884 switch (params_width(params)) { 1885 case 16 ... 24: 1886 wcd->dai[dai->id].sconfig.bps = params_width(params); 1887 break; 1888 default: 1889 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1890 __func__, params_width(params)); 1891 return -EINVAL; 1892 } 1893 break; 1894 1895 case SNDRV_PCM_STREAM_CAPTURE: 1896 switch (params_rate(params)) { 1897 case 8000: 1898 tx_fs_rate = 0; 1899 break; 1900 case 16000: 1901 tx_fs_rate = 1; 1902 break; 1903 case 32000: 1904 tx_fs_rate = 3; 1905 break; 1906 case 48000: 1907 tx_fs_rate = 4; 1908 break; 1909 case 96000: 1910 tx_fs_rate = 5; 1911 break; 1912 case 192000: 1913 tx_fs_rate = 6; 1914 break; 1915 case 384000: 1916 tx_fs_rate = 7; 1917 break; 1918 default: 1919 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n", 1920 __func__, params_rate(params)); 1921 return -EINVAL; 1922 1923 } 1924 1925 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate, 1926 params_rate(params)); 1927 if (ret < 0) { 1928 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1929 return ret; 1930 } 1931 switch (params_width(params)) { 1932 case 16 ... 32: 1933 wcd->dai[dai->id].sconfig.bps = params_width(params); 1934 break; 1935 default: 1936 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1937 __func__, params_width(params)); 1938 return -EINVAL; 1939 } 1940 break; 1941 default: 1942 dev_err(wcd->dev, "Invalid stream type %d\n", 1943 substream->stream); 1944 return -EINVAL; 1945 } 1946 1947 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1948 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1949 1950 return 0; 1951} 1952 1953static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd, 1954 struct snd_soc_dai *dai) 1955{ 1956 struct wcd_slim_codec_dai_data *dai_data; 1957 struct wcd9335_codec *wcd; 1958 struct slim_stream_config *cfg; 1959 1960 wcd = snd_soc_component_get_drvdata(dai->component); 1961 1962 dai_data = &wcd->dai[dai->id]; 1963 1964 switch (cmd) { 1965 case SNDRV_PCM_TRIGGER_START: 1966 case SNDRV_PCM_TRIGGER_RESUME: 1967 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1968 cfg = &dai_data->sconfig; 1969 slim_stream_prepare(dai_data->sruntime, cfg); 1970 slim_stream_enable(dai_data->sruntime); 1971 break; 1972 case SNDRV_PCM_TRIGGER_STOP: 1973 case SNDRV_PCM_TRIGGER_SUSPEND: 1974 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1975 slim_stream_disable(dai_data->sruntime); 1976 slim_stream_unprepare(dai_data->sruntime); 1977 break; 1978 default: 1979 break; 1980 } 1981 1982 return 0; 1983} 1984 1985static int wcd9335_set_channel_map(struct snd_soc_dai *dai, 1986 unsigned int tx_num, unsigned int *tx_slot, 1987 unsigned int rx_num, unsigned int *rx_slot) 1988{ 1989 struct wcd9335_codec *wcd; 1990 int i; 1991 1992 wcd = snd_soc_component_get_drvdata(dai->component); 1993 1994 if (!tx_slot || !rx_slot) { 1995 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1996 tx_slot, rx_slot); 1997 return -EINVAL; 1998 } 1999 2000 wcd->num_rx_port = rx_num; 2001 for (i = 0; i < rx_num; i++) { 2002 wcd->rx_chs[i].ch_num = rx_slot[i]; 2003 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 2004 } 2005 2006 wcd->num_tx_port = tx_num; 2007 for (i = 0; i < tx_num; i++) { 2008 wcd->tx_chs[i].ch_num = tx_slot[i]; 2009 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 2010 } 2011 2012 return 0; 2013} 2014 2015static int wcd9335_get_channel_map(struct snd_soc_dai *dai, 2016 unsigned int *tx_num, unsigned int *tx_slot, 2017 unsigned int *rx_num, unsigned int *rx_slot) 2018{ 2019 struct wcd9335_slim_ch *ch; 2020 struct wcd9335_codec *wcd; 2021 int i = 0; 2022 2023 wcd = snd_soc_component_get_drvdata(dai->component); 2024 2025 switch (dai->id) { 2026 case AIF1_PB: 2027 case AIF2_PB: 2028 case AIF3_PB: 2029 case AIF4_PB: 2030 if (!rx_slot || !rx_num) { 2031 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 2032 rx_slot, rx_num); 2033 return -EINVAL; 2034 } 2035 2036 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2037 rx_slot[i++] = ch->ch_num; 2038 2039 *rx_num = i; 2040 break; 2041 case AIF1_CAP: 2042 case AIF2_CAP: 2043 case AIF3_CAP: 2044 if (!tx_slot || !tx_num) { 2045 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 2046 tx_slot, tx_num); 2047 return -EINVAL; 2048 } 2049 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2050 tx_slot[i++] = ch->ch_num; 2051 2052 *tx_num = i; 2053 break; 2054 default: 2055 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2056 break; 2057 } 2058 2059 return 0; 2060} 2061 2062static const struct snd_soc_dai_ops wcd9335_dai_ops = { 2063 .hw_params = wcd9335_hw_params, 2064 .trigger = wcd9335_trigger, 2065 .set_channel_map = wcd9335_set_channel_map, 2066 .get_channel_map = wcd9335_get_channel_map, 2067}; 2068 2069static struct snd_soc_dai_driver wcd9335_slim_dais[] = { 2070 [0] = { 2071 .name = "wcd9335_rx1", 2072 .id = AIF1_PB, 2073 .playback = { 2074 .stream_name = "AIF1 Playback", 2075 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2076 SNDRV_PCM_RATE_384000, 2077 .formats = WCD9335_FORMATS_S16_S24_LE, 2078 .rate_max = 384000, 2079 .rate_min = 8000, 2080 .channels_min = 1, 2081 .channels_max = 2, 2082 }, 2083 .ops = &wcd9335_dai_ops, 2084 }, 2085 [1] = { 2086 .name = "wcd9335_tx1", 2087 .id = AIF1_CAP, 2088 .capture = { 2089 .stream_name = "AIF1 Capture", 2090 .rates = WCD9335_RATES_MASK, 2091 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2092 .rate_min = 8000, 2093 .rate_max = 192000, 2094 .channels_min = 1, 2095 .channels_max = 4, 2096 }, 2097 .ops = &wcd9335_dai_ops, 2098 }, 2099 [2] = { 2100 .name = "wcd9335_rx2", 2101 .id = AIF2_PB, 2102 .playback = { 2103 .stream_name = "AIF2 Playback", 2104 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2105 SNDRV_PCM_RATE_384000, 2106 .formats = WCD9335_FORMATS_S16_S24_LE, 2107 .rate_min = 8000, 2108 .rate_max = 384000, 2109 .channels_min = 1, 2110 .channels_max = 2, 2111 }, 2112 .ops = &wcd9335_dai_ops, 2113 }, 2114 [3] = { 2115 .name = "wcd9335_tx2", 2116 .id = AIF2_CAP, 2117 .capture = { 2118 .stream_name = "AIF2 Capture", 2119 .rates = WCD9335_RATES_MASK, 2120 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2121 .rate_min = 8000, 2122 .rate_max = 192000, 2123 .channels_min = 1, 2124 .channels_max = 4, 2125 }, 2126 .ops = &wcd9335_dai_ops, 2127 }, 2128 [4] = { 2129 .name = "wcd9335_rx3", 2130 .id = AIF3_PB, 2131 .playback = { 2132 .stream_name = "AIF3 Playback", 2133 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2134 SNDRV_PCM_RATE_384000, 2135 .formats = WCD9335_FORMATS_S16_S24_LE, 2136 .rate_min = 8000, 2137 .rate_max = 384000, 2138 .channels_min = 1, 2139 .channels_max = 2, 2140 }, 2141 .ops = &wcd9335_dai_ops, 2142 }, 2143 [5] = { 2144 .name = "wcd9335_tx3", 2145 .id = AIF3_CAP, 2146 .capture = { 2147 .stream_name = "AIF3 Capture", 2148 .rates = WCD9335_RATES_MASK, 2149 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2150 .rate_min = 8000, 2151 .rate_max = 192000, 2152 .channels_min = 1, 2153 .channels_max = 4, 2154 }, 2155 .ops = &wcd9335_dai_ops, 2156 }, 2157 [6] = { 2158 .name = "wcd9335_rx4", 2159 .id = AIF4_PB, 2160 .playback = { 2161 .stream_name = "AIF4 Playback", 2162 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2163 SNDRV_PCM_RATE_384000, 2164 .formats = WCD9335_FORMATS_S16_S24_LE, 2165 .rate_min = 8000, 2166 .rate_max = 384000, 2167 .channels_min = 1, 2168 .channels_max = 2, 2169 }, 2170 .ops = &wcd9335_dai_ops, 2171 }, 2172}; 2173 2174static int wcd9335_get_compander(struct snd_kcontrol *kc, 2175 struct snd_ctl_elem_value *ucontrol) 2176{ 2177 2178 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2179 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 2180 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2181 2182 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 2183 return 0; 2184} 2185 2186static int wcd9335_set_compander(struct snd_kcontrol *kc, 2187 struct snd_ctl_elem_value *ucontrol) 2188{ 2189 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2190 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2191 int comp = ((struct soc_mixer_control *) kc->private_value)->shift; 2192 int value = ucontrol->value.integer.value[0]; 2193 int sel; 2194 2195 wcd->comp_enabled[comp] = value; 2196 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER : 2197 WCD9335_HPH_GAIN_SRC_SEL_REGISTER; 2198 2199 /* Any specific register configuration for compander */ 2200 switch (comp) { 2201 case COMPANDER_1: 2202 /* Set Gain Source Select based on compander enable/disable */ 2203 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 2204 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2205 break; 2206 case COMPANDER_2: 2207 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 2208 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2209 break; 2210 case COMPANDER_5: 2211 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN, 2212 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2213 break; 2214 case COMPANDER_6: 2215 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN, 2216 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2217 break; 2218 default: 2219 break; 2220 } 2221 2222 return 0; 2223} 2224 2225static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc, 2226 struct snd_ctl_elem_value *ucontrol) 2227{ 2228 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2229 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2230 2231 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 2232 2233 return 0; 2234} 2235 2236static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc, 2237 struct snd_ctl_elem_value *ucontrol) 2238{ 2239 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2240 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2241 u32 mode_val; 2242 2243 mode_val = ucontrol->value.enumerated.item[0]; 2244 2245 if (mode_val == 0) { 2246 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 2247 mode_val = CLS_H_HIFI; 2248 } 2249 wcd->hph_mode = mode_val; 2250 2251 return 0; 2252} 2253 2254static const struct snd_kcontrol_new wcd9335_snd_controls[] = { 2255 /* -84dB min - 40dB max */ 2256 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL, 2257 -84, 40, digital_gain), 2258 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL, 2259 -84, 40, digital_gain), 2260 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL, 2261 -84, 40, digital_gain), 2262 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL, 2263 -84, 40, digital_gain), 2264 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL, 2265 -84, 40, digital_gain), 2266 SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL, 2267 -84, 40, digital_gain), 2268 SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL, 2269 -84, 40, digital_gain), 2270 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL, 2271 -84, 40, digital_gain), 2272 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL, 2273 -84, 40, digital_gain), 2274 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL, 2275 -84, 40, digital_gain), 2276 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL, 2277 -84, 40, digital_gain), 2278 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL, 2279 -84, 40, digital_gain), 2280 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL, 2281 -84, 40, digital_gain), 2282 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL, 2283 -84, 40, digital_gain), 2284 SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL, 2285 -84, 40, digital_gain), 2286 SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL, 2287 -84, 40, digital_gain), 2288 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL, 2289 -84, 40, digital_gain), 2290 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL, 2291 -84, 40, digital_gain), 2292 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 2293 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 2294 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 2295 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 2296 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 2297 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 2298 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 2299 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 2300 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 2301 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 2302 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum), 2303 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum), 2304 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum), 2305 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum), 2306 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 2307 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 2308 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 2309 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 2310 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 2311 wcd9335_get_compander, wcd9335_set_compander), 2312 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 2313 wcd9335_get_compander, wcd9335_set_compander), 2314 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 2315 wcd9335_get_compander, wcd9335_set_compander), 2316 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 2317 wcd9335_get_compander, wcd9335_set_compander), 2318 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0, 2319 wcd9335_get_compander, wcd9335_set_compander), 2320 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0, 2321 wcd9335_get_compander, wcd9335_set_compander), 2322 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 2323 wcd9335_get_compander, wcd9335_set_compander), 2324 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 2325 wcd9335_get_compander, wcd9335_set_compander), 2326 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2327 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put), 2328 2329 /* Gain Controls */ 2330 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1, 2331 ear_pa_gain), 2332 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1, 2333 line_gain), 2334 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1, 2335 line_gain), 2336 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER, 2337 3, 16, 1, line_gain), 2338 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER, 2339 3, 16, 1, line_gain), 2340 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1, 2341 line_gain), 2342 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1, 2343 line_gain), 2344 2345 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0, 2346 analog_gain), 2347 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0, 2348 analog_gain), 2349 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0, 2350 analog_gain), 2351 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0, 2352 analog_gain), 2353 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0, 2354 analog_gain), 2355 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0, 2356 analog_gain), 2357 2358 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 2359 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 2360 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 2361 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 2362 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 2363 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 2364 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 2365 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 2366 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 2367}; 2368 2369static const struct snd_soc_dapm_route wcd9335_audio_map[] = { 2370 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"}, 2371 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"}, 2372 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"}, 2373 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"}, 2374 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"}, 2375 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"}, 2376 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"}, 2377 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"}, 2378 2379 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"}, 2380 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"}, 2381 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"}, 2382 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"}, 2383 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"}, 2384 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"}, 2385 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"}, 2386 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"}, 2387 2388 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"}, 2389 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"}, 2390 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"}, 2391 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"}, 2392 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"}, 2393 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"}, 2394 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"}, 2395 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"}, 2396 2397 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"}, 2398 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"}, 2399 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"}, 2400 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"}, 2401 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"}, 2402 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"}, 2403 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"}, 2404 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"}, 2405 2406 {"SLIM RX0", NULL, "SLIM RX0 MUX"}, 2407 {"SLIM RX1", NULL, "SLIM RX1 MUX"}, 2408 {"SLIM RX2", NULL, "SLIM RX2 MUX"}, 2409 {"SLIM RX3", NULL, "SLIM RX3 MUX"}, 2410 {"SLIM RX4", NULL, "SLIM RX4 MUX"}, 2411 {"SLIM RX5", NULL, "SLIM RX5 MUX"}, 2412 {"SLIM RX6", NULL, "SLIM RX6 MUX"}, 2413 {"SLIM RX7", NULL, "SLIM RX7 MUX"}, 2414 2415 WCD9335_INTERPOLATOR_PATH(0), 2416 WCD9335_INTERPOLATOR_PATH(1), 2417 WCD9335_INTERPOLATOR_PATH(2), 2418 WCD9335_INTERPOLATOR_PATH(3), 2419 WCD9335_INTERPOLATOR_PATH(4), 2420 WCD9335_INTERPOLATOR_PATH(5), 2421 WCD9335_INTERPOLATOR_PATH(6), 2422 WCD9335_INTERPOLATOR_PATH(7), 2423 WCD9335_INTERPOLATOR_PATH(8), 2424 2425 /* EAR PA */ 2426 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"}, 2427 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 2428 {"RX INT0 DAC", NULL, "RX_BIAS"}, 2429 {"EAR PA", NULL, "RX INT0 DAC"}, 2430 {"EAR", NULL, "EAR PA"}, 2431 2432 /* HPHL */ 2433 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"}, 2434 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 2435 {"RX INT1 DAC", NULL, "RX_BIAS"}, 2436 {"HPHL PA", NULL, "RX INT1 DAC"}, 2437 {"HPHL", NULL, "HPHL PA"}, 2438 2439 /* HPHR */ 2440 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"}, 2441 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 2442 {"RX INT2 DAC", NULL, "RX_BIAS"}, 2443 {"HPHR PA", NULL, "RX INT2 DAC"}, 2444 {"HPHR", NULL, "HPHR PA"}, 2445 2446 /* LINEOUT1 */ 2447 {"RX INT3 DAC", NULL, "RX INT3 INTERP"}, 2448 {"RX INT3 DAC", NULL, "RX_BIAS"}, 2449 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 2450 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 2451 2452 /* LINEOUT2 */ 2453 {"RX INT4 DAC", NULL, "RX INT4 INTERP"}, 2454 {"RX INT4 DAC", NULL, "RX_BIAS"}, 2455 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 2456 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 2457 2458 /* LINEOUT3 */ 2459 {"RX INT5 DAC", NULL, "RX INT5 INTERP"}, 2460 {"RX INT5 DAC", NULL, "RX_BIAS"}, 2461 {"LINEOUT3 PA", NULL, "RX INT5 DAC"}, 2462 {"LINEOUT3", NULL, "LINEOUT3 PA"}, 2463 2464 /* LINEOUT4 */ 2465 {"RX INT6 DAC", NULL, "RX INT6 INTERP"}, 2466 {"RX INT6 DAC", NULL, "RX_BIAS"}, 2467 {"LINEOUT4 PA", NULL, "RX INT6 DAC"}, 2468 {"LINEOUT4", NULL, "LINEOUT4 PA"}, 2469 2470 /* SLIMBUS Connections */ 2471 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 2472 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 2473 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 2474 2475 /* ADC Mux */ 2476 WCD9335_ADC_MUX_PATH(0), 2477 WCD9335_ADC_MUX_PATH(1), 2478 WCD9335_ADC_MUX_PATH(2), 2479 WCD9335_ADC_MUX_PATH(3), 2480 WCD9335_ADC_MUX_PATH(4), 2481 WCD9335_ADC_MUX_PATH(5), 2482 WCD9335_ADC_MUX_PATH(6), 2483 WCD9335_ADC_MUX_PATH(7), 2484 WCD9335_ADC_MUX_PATH(8), 2485 2486 /* ADC Connections */ 2487 {"ADC1", NULL, "AMIC1"}, 2488 {"ADC2", NULL, "AMIC2"}, 2489 {"ADC3", NULL, "AMIC3"}, 2490 {"ADC4", NULL, "AMIC4"}, 2491 {"ADC5", NULL, "AMIC5"}, 2492 {"ADC6", NULL, "AMIC6"}, 2493}; 2494 2495static int wcd9335_micbias_control(struct snd_soc_component *component, 2496 int micb_num, int req, bool is_dapm) 2497{ 2498 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component); 2499 int micb_index = micb_num - 1; 2500 u16 micb_reg; 2501 2502 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) { 2503 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n", 2504 micb_index); 2505 return -EINVAL; 2506 } 2507 2508 switch (micb_num) { 2509 case MIC_BIAS_1: 2510 micb_reg = WCD9335_ANA_MICB1; 2511 break; 2512 case MIC_BIAS_2: 2513 micb_reg = WCD9335_ANA_MICB2; 2514 break; 2515 case MIC_BIAS_3: 2516 micb_reg = WCD9335_ANA_MICB3; 2517 break; 2518 case MIC_BIAS_4: 2519 micb_reg = WCD9335_ANA_MICB4; 2520 break; 2521 default: 2522 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2523 __func__, micb_num); 2524 return -EINVAL; 2525 } 2526 2527 switch (req) { 2528 case MICB_PULLUP_ENABLE: 2529 wcd->pullup_ref[micb_index]++; 2530 if ((wcd->pullup_ref[micb_index] == 1) && 2531 (wcd->micb_ref[micb_index] == 0)) 2532 snd_soc_component_update_bits(component, micb_reg, 2533 0xC0, 0x80); 2534 break; 2535 case MICB_PULLUP_DISABLE: 2536 wcd->pullup_ref[micb_index]--; 2537 if ((wcd->pullup_ref[micb_index] == 0) && 2538 (wcd->micb_ref[micb_index] == 0)) 2539 snd_soc_component_update_bits(component, micb_reg, 2540 0xC0, 0x00); 2541 break; 2542 case MICB_ENABLE: 2543 wcd->micb_ref[micb_index]++; 2544 if (wcd->micb_ref[micb_index] == 1) 2545 snd_soc_component_update_bits(component, micb_reg, 2546 0xC0, 0x40); 2547 break; 2548 case MICB_DISABLE: 2549 wcd->micb_ref[micb_index]--; 2550 if ((wcd->micb_ref[micb_index] == 0) && 2551 (wcd->pullup_ref[micb_index] > 0)) 2552 snd_soc_component_update_bits(component, micb_reg, 2553 0xC0, 0x80); 2554 else if ((wcd->micb_ref[micb_index] == 0) && 2555 (wcd->pullup_ref[micb_index] == 0)) { 2556 snd_soc_component_update_bits(component, micb_reg, 2557 0xC0, 0x00); 2558 } 2559 break; 2560 } 2561 2562 return 0; 2563} 2564 2565static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2566 int event) 2567{ 2568 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2569 int micb_num; 2570 2571 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1"))) 2572 micb_num = MIC_BIAS_1; 2573 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2"))) 2574 micb_num = MIC_BIAS_2; 2575 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3"))) 2576 micb_num = MIC_BIAS_3; 2577 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4"))) 2578 micb_num = MIC_BIAS_4; 2579 else 2580 return -EINVAL; 2581 2582 switch (event) { 2583 case SND_SOC_DAPM_PRE_PMU: 2584 /* 2585 * MIC BIAS can also be requested by MBHC, 2586 * so use ref count to handle micbias pullup 2587 * and enable requests 2588 */ 2589 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true); 2590 break; 2591 case SND_SOC_DAPM_POST_PMU: 2592 /* wait for cnp time */ 2593 usleep_range(1000, 1100); 2594 break; 2595 case SND_SOC_DAPM_POST_PMD: 2596 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true); 2597 break; 2598 } 2599 2600 return 0; 2601} 2602 2603static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2604 struct snd_kcontrol *kc, int event) 2605{ 2606 return __wcd9335_codec_enable_micbias(w, event); 2607} 2608 2609static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp, 2610 u16 amic_reg, bool set) 2611{ 2612 u8 mask = 0x20; 2613 u8 val; 2614 2615 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 || 2616 amic_reg == WCD9335_ANA_AMIC5) 2617 mask = 0x40; 2618 2619 val = set ? mask : 0x00; 2620 2621 switch (amic_reg) { 2622 case WCD9335_ANA_AMIC1: 2623 case WCD9335_ANA_AMIC2: 2624 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask, 2625 val); 2626 break; 2627 case WCD9335_ANA_AMIC3: 2628 case WCD9335_ANA_AMIC4: 2629 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask, 2630 val); 2631 break; 2632 case WCD9335_ANA_AMIC5: 2633 case WCD9335_ANA_AMIC6: 2634 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask, 2635 val); 2636 break; 2637 default: 2638 dev_err(comp->dev, "%s: invalid amic: %d\n", 2639 __func__, amic_reg); 2640 break; 2641 } 2642} 2643 2644static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w, 2645 struct snd_kcontrol *kc, int event) 2646{ 2647 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2648 2649 switch (event) { 2650 case SND_SOC_DAPM_PRE_PMU: 2651 wcd9335_codec_set_tx_hold(comp, w->reg, true); 2652 break; 2653 default: 2654 break; 2655 } 2656 2657 return 0; 2658} 2659 2660static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp, 2661 int adc_mux_n) 2662{ 2663 int mux_sel, reg, mreg; 2664 2665 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX || 2666 adc_mux_n == WCD9335_INVALID_ADC_MUX) 2667 return 0; 2668 2669 /* Check whether adc mux input is AMIC or DMIC */ 2670 if (adc_mux_n < 4) { 2671 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n; 2672 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n; 2673 mux_sel = snd_soc_component_read(comp, reg) & 0x3; 2674 } else { 2675 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4; 2676 mreg = reg; 2677 mux_sel = snd_soc_component_read(comp, reg) >> 6; 2678 } 2679 2680 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC) 2681 return 0; 2682 2683 return snd_soc_component_read(comp, mreg) & 0x07; 2684} 2685 2686static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 2687 int amic) 2688{ 2689 u16 pwr_level_reg = 0; 2690 2691 switch (amic) { 2692 case 1: 2693 case 2: 2694 pwr_level_reg = WCD9335_ANA_AMIC1; 2695 break; 2696 2697 case 3: 2698 case 4: 2699 pwr_level_reg = WCD9335_ANA_AMIC3; 2700 break; 2701 2702 case 5: 2703 case 6: 2704 pwr_level_reg = WCD9335_ANA_AMIC5; 2705 break; 2706 default: 2707 dev_err(comp->dev, "invalid amic: %d\n", amic); 2708 break; 2709 } 2710 2711 return pwr_level_reg; 2712} 2713 2714static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w, 2715 struct snd_kcontrol *kc, int event) 2716{ 2717 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2718 unsigned int decimator; 2719 char *dec_adc_mux_name = NULL; 2720 char *widget_name = NULL; 2721 char *wname; 2722 int ret = 0, amic_n; 2723 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 2724 u16 tx_gain_ctl_reg; 2725 char *dec; 2726 u8 hpf_coff_freq; 2727 2728 widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL); 2729 if (!widget_name) 2730 return -ENOMEM; 2731 2732 wname = widget_name; 2733 dec_adc_mux_name = strsep(&widget_name, " "); 2734 if (!dec_adc_mux_name) { 2735 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2736 __func__, w->name); 2737 ret = -EINVAL; 2738 goto out; 2739 } 2740 dec_adc_mux_name = widget_name; 2741 2742 dec = strpbrk(dec_adc_mux_name, "012345678"); 2743 if (!dec) { 2744 dev_err(comp->dev, "%s: decimator index not found\n", 2745 __func__); 2746 ret = -EINVAL; 2747 goto out; 2748 } 2749 2750 ret = kstrtouint(dec, 10, &decimator); 2751 if (ret < 0) { 2752 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2753 __func__, wname); 2754 ret = -EINVAL; 2755 goto out; 2756 } 2757 2758 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator; 2759 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 2760 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 2761 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator; 2762 2763 switch (event) { 2764 case SND_SOC_DAPM_PRE_PMU: 2765 amic_n = wcd9335_codec_find_amic_input(comp, decimator); 2766 if (amic_n) 2767 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp, 2768 amic_n); 2769 2770 if (pwr_level_reg) { 2771 switch ((snd_soc_component_read(comp, pwr_level_reg) & 2772 WCD9335_AMIC_PWR_LVL_MASK) >> 2773 WCD9335_AMIC_PWR_LVL_SHIFT) { 2774 case WCD9335_AMIC_PWR_LEVEL_LP: 2775 snd_soc_component_update_bits(comp, dec_cfg_reg, 2776 WCD9335_DEC_PWR_LVL_MASK, 2777 WCD9335_DEC_PWR_LVL_LP); 2778 break; 2779 2780 case WCD9335_AMIC_PWR_LEVEL_HP: 2781 snd_soc_component_update_bits(comp, dec_cfg_reg, 2782 WCD9335_DEC_PWR_LVL_MASK, 2783 WCD9335_DEC_PWR_LVL_HP); 2784 break; 2785 case WCD9335_AMIC_PWR_LEVEL_DEFAULT: 2786 default: 2787 snd_soc_component_update_bits(comp, dec_cfg_reg, 2788 WCD9335_DEC_PWR_LVL_MASK, 2789 WCD9335_DEC_PWR_LVL_DF); 2790 break; 2791 } 2792 } 2793 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2794 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2795 2796 if (hpf_coff_freq != CF_MIN_3DB_150HZ) 2797 snd_soc_component_update_bits(comp, dec_cfg_reg, 2798 TX_HPF_CUT_OFF_FREQ_MASK, 2799 CF_MIN_3DB_150HZ << 5); 2800 /* Enable TX PGA Mute */ 2801 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2802 0x10, 0x10); 2803 /* Enable APC */ 2804 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08); 2805 break; 2806 case SND_SOC_DAPM_POST_PMU: 2807 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00); 2808 2809 if (decimator == 0) { 2810 snd_soc_component_write(comp, 2811 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2812 snd_soc_component_write(comp, 2813 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3); 2814 snd_soc_component_write(comp, 2815 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2816 snd_soc_component_write(comp, 2817 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03); 2818 } 2819 2820 snd_soc_component_update_bits(comp, hpf_gate_reg, 2821 0x01, 0x01); 2822 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2823 0x10, 0x00); 2824 snd_soc_component_write(comp, tx_gain_ctl_reg, 2825 snd_soc_component_read(comp, tx_gain_ctl_reg)); 2826 break; 2827 case SND_SOC_DAPM_PRE_PMD: 2828 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2829 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2830 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10); 2831 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00); 2832 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 2833 snd_soc_component_update_bits(comp, dec_cfg_reg, 2834 TX_HPF_CUT_OFF_FREQ_MASK, 2835 hpf_coff_freq << 5); 2836 } 2837 break; 2838 case SND_SOC_DAPM_POST_PMD: 2839 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00); 2840 break; 2841 } 2842out: 2843 kfree(wname); 2844 return ret; 2845} 2846 2847static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component, 2848 u32 mclk_rate, u32 dmic_clk_rate) 2849{ 2850 u32 div_factor; 2851 u8 dmic_ctl_val; 2852 2853 dev_err(component->dev, 2854 "%s: mclk_rate = %d, dmic_sample_rate = %d\n", 2855 __func__, mclk_rate, dmic_clk_rate); 2856 2857 /* Default value to return in case of error */ 2858 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 2859 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2860 else 2861 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2862 2863 if (dmic_clk_rate == 0) { 2864 dev_err(component->dev, 2865 "%s: dmic_sample_rate cannot be 0\n", 2866 __func__); 2867 goto done; 2868 } 2869 2870 div_factor = mclk_rate / dmic_clk_rate; 2871 switch (div_factor) { 2872 case 2: 2873 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2874 break; 2875 case 3: 2876 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2877 break; 2878 case 4: 2879 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4; 2880 break; 2881 case 6: 2882 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6; 2883 break; 2884 case 8: 2885 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8; 2886 break; 2887 case 16: 2888 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16; 2889 break; 2890 default: 2891 dev_err(component->dev, 2892 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 2893 __func__, div_factor, mclk_rate, dmic_clk_rate); 2894 break; 2895 } 2896 2897done: 2898 return dmic_ctl_val; 2899} 2900 2901static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w, 2902 struct snd_kcontrol *kc, int event) 2903{ 2904 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2905 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 2906 u8 dmic_clk_en = 0x01; 2907 u16 dmic_clk_reg; 2908 s32 *dmic_clk_cnt; 2909 u8 dmic_rate_val, dmic_rate_shift = 1; 2910 unsigned int dmic; 2911 int ret; 2912 char *wname; 2913 2914 wname = strpbrk(w->name, "012345"); 2915 if (!wname) { 2916 dev_err(comp->dev, "%s: widget not found\n", __func__); 2917 return -EINVAL; 2918 } 2919 2920 ret = kstrtouint(wname, 10, &dmic); 2921 if (ret < 0) { 2922 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 2923 __func__); 2924 return -EINVAL; 2925 } 2926 2927 switch (dmic) { 2928 case 0: 2929 case 1: 2930 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt); 2931 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL; 2932 break; 2933 case 2: 2934 case 3: 2935 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt); 2936 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL; 2937 break; 2938 case 4: 2939 case 5: 2940 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt); 2941 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL; 2942 break; 2943 default: 2944 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 2945 __func__); 2946 return -EINVAL; 2947 } 2948 2949 switch (event) { 2950 case SND_SOC_DAPM_PRE_PMU: 2951 dmic_rate_val = 2952 wcd9335_get_dmic_clk_val(comp, 2953 wcd->mclk_rate, 2954 wcd->dmic_sample_rate); 2955 2956 (*dmic_clk_cnt)++; 2957 if (*dmic_clk_cnt == 1) { 2958 snd_soc_component_update_bits(comp, dmic_clk_reg, 2959 0x07 << dmic_rate_shift, 2960 dmic_rate_val << dmic_rate_shift); 2961 snd_soc_component_update_bits(comp, dmic_clk_reg, 2962 dmic_clk_en, dmic_clk_en); 2963 } 2964 2965 break; 2966 case SND_SOC_DAPM_POST_PMD: 2967 dmic_rate_val = 2968 wcd9335_get_dmic_clk_val(comp, 2969 wcd->mclk_rate, 2970 wcd->mad_dmic_sample_rate); 2971 (*dmic_clk_cnt)--; 2972 if (*dmic_clk_cnt == 0) { 2973 snd_soc_component_update_bits(comp, dmic_clk_reg, 2974 dmic_clk_en, 0); 2975 snd_soc_component_update_bits(comp, dmic_clk_reg, 2976 0x07 << dmic_rate_shift, 2977 dmic_rate_val << dmic_rate_shift); 2978 } 2979 break; 2980 } 2981 2982 return 0; 2983} 2984 2985static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 2986 struct snd_soc_component *component) 2987{ 2988 int port_num = 0; 2989 unsigned short reg = 0; 2990 unsigned int val = 0; 2991 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2992 struct wcd9335_slim_ch *ch; 2993 2994 list_for_each_entry(ch, &dai->slim_ch_list, list) { 2995 if (ch->port >= WCD9335_RX_START) { 2996 port_num = ch->port - WCD9335_RX_START; 2997 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 2998 } else { 2999 port_num = ch->port; 3000 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 3001 } 3002 3003 regmap_read(wcd->if_regmap, reg, &val); 3004 if (!(val & BIT(port_num % 8))) 3005 regmap_write(wcd->if_regmap, reg, 3006 val | BIT(port_num % 8)); 3007 } 3008} 3009 3010static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w, 3011 struct snd_kcontrol *kc, 3012 int event) 3013{ 3014 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3015 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 3016 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 3017 3018 switch (event) { 3019 case SND_SOC_DAPM_POST_PMU: 3020 wcd9335_codec_enable_int_port(dai, comp); 3021 break; 3022 case SND_SOC_DAPM_POST_PMD: 3023 kfree(dai->sconfig.chs); 3024 3025 break; 3026 } 3027 3028 return 0; 3029} 3030 3031static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 3032 struct snd_kcontrol *kc, int event) 3033{ 3034 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3035 u16 gain_reg; 3036 int val = 0; 3037 3038 switch (w->reg) { 3039 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3040 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL; 3041 break; 3042 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3043 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL; 3044 break; 3045 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3046 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL; 3047 break; 3048 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3049 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL; 3050 break; 3051 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3052 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL; 3053 break; 3054 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3055 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL; 3056 break; 3057 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3058 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL; 3059 break; 3060 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3061 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL; 3062 break; 3063 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3064 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL; 3065 break; 3066 default: 3067 dev_err(comp->dev, "%s: No gain register avail for %s\n", 3068 __func__, w->name); 3069 return 0; 3070 } 3071 3072 switch (event) { 3073 case SND_SOC_DAPM_POST_PMU: 3074 val = snd_soc_component_read(comp, gain_reg); 3075 snd_soc_component_write(comp, gain_reg, val); 3076 break; 3077 case SND_SOC_DAPM_POST_PMD: 3078 break; 3079 } 3080 3081 return 0; 3082} 3083 3084static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind) 3085{ 3086 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3087 3088 switch (reg) { 3089 case WCD9335_CDC_RX0_RX_PATH_CTL: 3090 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3091 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3092 *ind = 0; 3093 break; 3094 case WCD9335_CDC_RX1_RX_PATH_CTL: 3095 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3096 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3097 *ind = 1; 3098 break; 3099 case WCD9335_CDC_RX2_RX_PATH_CTL: 3100 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3101 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3102 *ind = 2; 3103 break; 3104 case WCD9335_CDC_RX3_RX_PATH_CTL: 3105 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3106 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3107 *ind = 3; 3108 break; 3109 case WCD9335_CDC_RX4_RX_PATH_CTL: 3110 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3111 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3112 *ind = 4; 3113 break; 3114 case WCD9335_CDC_RX5_RX_PATH_CTL: 3115 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3116 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3117 *ind = 5; 3118 break; 3119 case WCD9335_CDC_RX6_RX_PATH_CTL: 3120 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3121 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3122 *ind = 6; 3123 break; 3124 case WCD9335_CDC_RX7_RX_PATH_CTL: 3125 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3126 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3127 *ind = 7; 3128 break; 3129 case WCD9335_CDC_RX8_RX_PATH_CTL: 3130 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3131 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3132 *ind = 8; 3133 break; 3134 } 3135 3136 return prim_int_reg; 3137} 3138 3139static void wcd9335_codec_hd2_control(struct snd_soc_component *component, 3140 u16 prim_int_reg, int event) 3141{ 3142 u16 hd2_scale_reg; 3143 u16 hd2_enable_reg = 0; 3144 3145 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) { 3146 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3; 3147 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 3148 } 3149 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) { 3150 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3; 3151 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 3152 } 3153 3154 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 3155 snd_soc_component_update_bits(component, hd2_scale_reg, 3156 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3157 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500); 3158 snd_soc_component_update_bits(component, hd2_scale_reg, 3159 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3160 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2); 3161 snd_soc_component_update_bits(component, hd2_enable_reg, 3162 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3163 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE); 3164 } 3165 3166 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 3167 snd_soc_component_update_bits(component, hd2_enable_reg, 3168 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3169 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE); 3170 snd_soc_component_update_bits(component, hd2_scale_reg, 3171 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3172 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1); 3173 snd_soc_component_update_bits(component, hd2_scale_reg, 3174 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3175 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 3176 } 3177} 3178 3179static int wcd9335_codec_enable_prim_interpolator( 3180 struct snd_soc_component *comp, 3181 u16 reg, int event) 3182{ 3183 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3184 u16 ind = 0; 3185 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind); 3186 3187 switch (event) { 3188 case SND_SOC_DAPM_PRE_PMU: 3189 wcd->prim_int_users[ind]++; 3190 if (wcd->prim_int_users[ind] == 1) { 3191 snd_soc_component_update_bits(comp, prim_int_reg, 3192 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3193 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3194 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3195 snd_soc_component_update_bits(comp, prim_int_reg, 3196 WCD9335_CDC_RX_CLK_EN_MASK, 3197 WCD9335_CDC_RX_CLK_ENABLE); 3198 } 3199 3200 if ((reg != prim_int_reg) && 3201 ((snd_soc_component_read(comp, prim_int_reg)) & 3202 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)) 3203 snd_soc_component_update_bits(comp, reg, 3204 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3205 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3206 break; 3207 case SND_SOC_DAPM_POST_PMD: 3208 wcd->prim_int_users[ind]--; 3209 if (wcd->prim_int_users[ind] == 0) { 3210 snd_soc_component_update_bits(comp, prim_int_reg, 3211 WCD9335_CDC_RX_CLK_EN_MASK, 3212 WCD9335_CDC_RX_CLK_DISABLE); 3213 snd_soc_component_update_bits(comp, prim_int_reg, 3214 WCD9335_CDC_RX_RESET_MASK, 3215 WCD9335_CDC_RX_RESET_ENABLE); 3216 snd_soc_component_update_bits(comp, prim_int_reg, 3217 WCD9335_CDC_RX_RESET_MASK, 3218 WCD9335_CDC_RX_RESET_DISABLE); 3219 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3220 } 3221 break; 3222 } 3223 3224 return 0; 3225} 3226 3227static int wcd9335_config_compander(struct snd_soc_component *component, 3228 int interp_n, int event) 3229{ 3230 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3231 int comp; 3232 u16 comp_ctl0_reg, rx_path_cfg0_reg; 3233 3234 /* EAR does not have compander */ 3235 if (!interp_n) 3236 return 0; 3237 3238 comp = interp_n - 1; 3239 if (!wcd->comp_enabled[comp]) 3240 return 0; 3241 3242 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp); 3243 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp); 3244 3245 if (SND_SOC_DAPM_EVENT_ON(event)) { 3246 /* Enable Compander Clock */ 3247 snd_soc_component_update_bits(component, comp_ctl0_reg, 3248 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3249 WCD9335_CDC_COMPANDER_CLK_ENABLE); 3250 /* Reset comander */ 3251 snd_soc_component_update_bits(component, comp_ctl0_reg, 3252 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3253 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3254 snd_soc_component_update_bits(component, comp_ctl0_reg, 3255 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3256 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3257 /* Enables DRE in this path */ 3258 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3259 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3260 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE); 3261 } 3262 3263 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3264 snd_soc_component_update_bits(component, comp_ctl0_reg, 3265 WCD9335_CDC_COMPANDER_HALT_MASK, 3266 WCD9335_CDC_COMPANDER_HALT); 3267 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3268 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3269 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE); 3270 3271 snd_soc_component_update_bits(component, comp_ctl0_reg, 3272 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3273 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3274 snd_soc_component_update_bits(component, comp_ctl0_reg, 3275 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3276 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3277 snd_soc_component_update_bits(component, comp_ctl0_reg, 3278 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3279 WCD9335_CDC_COMPANDER_CLK_DISABLE); 3280 snd_soc_component_update_bits(component, comp_ctl0_reg, 3281 WCD9335_CDC_COMPANDER_HALT_MASK, 3282 WCD9335_CDC_COMPANDER_NOHALT); 3283 } 3284 3285 return 0; 3286} 3287 3288static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w, 3289 struct snd_kcontrol *kc, int event) 3290{ 3291 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3292 u16 gain_reg; 3293 u16 reg; 3294 int val; 3295 3296 if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT0 INTERP"))) { 3297 reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3298 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL; 3299 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT1 INTERP"))) { 3300 reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3301 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL; 3302 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT2 INTERP"))) { 3303 reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3304 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL; 3305 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT3 INTERP"))) { 3306 reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3307 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL; 3308 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT4 INTERP"))) { 3309 reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3310 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL; 3311 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT5 INTERP"))) { 3312 reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3313 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL; 3314 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT6 INTERP"))) { 3315 reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3316 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL; 3317 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT7 INTERP"))) { 3318 reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3319 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL; 3320 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT8 INTERP"))) { 3321 reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3322 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL; 3323 } else { 3324 dev_err(comp->dev, "%s: Interpolator reg not found\n", 3325 __func__); 3326 return -EINVAL; 3327 } 3328 3329 switch (event) { 3330 case SND_SOC_DAPM_PRE_PMU: 3331 /* Reset if needed */ 3332 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3333 break; 3334 case SND_SOC_DAPM_POST_PMU: 3335 wcd9335_config_compander(comp, w->shift, event); 3336 val = snd_soc_component_read(comp, gain_reg); 3337 snd_soc_component_write(comp, gain_reg, val); 3338 break; 3339 case SND_SOC_DAPM_POST_PMD: 3340 wcd9335_config_compander(comp, w->shift, event); 3341 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3342 break; 3343 } 3344 3345 return 0; 3346} 3347 3348static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component, 3349 u8 gain) 3350{ 3351 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3352 u8 hph_l_en, hph_r_en; 3353 u8 l_val, r_val; 3354 u8 hph_pa_status; 3355 bool is_hphl_pa, is_hphr_pa; 3356 3357 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH); 3358 is_hphl_pa = hph_pa_status >> 7; 3359 is_hphr_pa = (hph_pa_status & 0x40) >> 6; 3360 3361 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN); 3362 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN); 3363 3364 l_val = (hph_l_en & 0xC0) | 0x20 | gain; 3365 r_val = (hph_r_en & 0xC0) | 0x20 | gain; 3366 3367 /* 3368 * Set HPH_L & HPH_R gain source selection to REGISTER 3369 * for better click and pop only if corresponding PAs are 3370 * not enabled. Also cache the values of the HPHL/R 3371 * PA gains to be applied after PAs are enabled 3372 */ 3373 if ((l_val != hph_l_en) && !is_hphl_pa) { 3374 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val); 3375 wcd->hph_l_gain = hph_l_en & 0x1F; 3376 } 3377 3378 if ((r_val != hph_r_en) && !is_hphr_pa) { 3379 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val); 3380 wcd->hph_r_gain = hph_r_en & 0x1F; 3381 } 3382} 3383 3384static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp, 3385 int event) 3386{ 3387 if (SND_SOC_DAPM_EVENT_ON(event)) { 3388 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3389 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3390 0x06); 3391 snd_soc_component_update_bits(comp, 3392 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3393 0xF0, 0x40); 3394 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3395 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3396 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3397 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3398 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3399 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3400 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3401 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3402 0x0C); 3403 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3404 } 3405 3406 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3407 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3408 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3409 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3410 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3411 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3412 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3413 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3414 0x8A); 3415 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3416 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3417 0x0A); 3418 } 3419} 3420 3421static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp, 3422 int event) 3423{ 3424 if (SND_SOC_DAPM_EVENT_ON(event)) { 3425 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3426 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3427 0x0C); 3428 wcd9335_codec_hph_mode_gain_opt(comp, 0x10); 3429 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3430 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3431 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3432 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3433 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3434 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3435 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3436 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3437 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE); 3438 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3439 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3440 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE); 3441 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3442 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK, 3443 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60); 3444 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3445 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK, 3446 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60); 3447 snd_soc_component_update_bits(comp, 3448 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01); 3449 snd_soc_component_update_bits(comp, 3450 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10); 3451 } 3452 3453 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3454 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO, 3455 0x88); 3456 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL, 3457 0x33); 3458 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3459 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3460 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE); 3461 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3462 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3463 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE); 3464 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3465 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3466 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3467 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3468 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3469 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3470 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN, 3471 WCD9335_HPH_CONST_SEL_L_MASK, 3472 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3473 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN, 3474 WCD9335_HPH_CONST_SEL_L_MASK, 3475 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3476 } 3477} 3478 3479static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp, 3480 int event) 3481{ 3482 if (SND_SOC_DAPM_EVENT_ON(event)) { 3483 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3484 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3485 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3486 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3487 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3488 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3489 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3490 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3491 0x0C); 3492 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3493 } 3494 3495 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3496 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3497 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3498 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3499 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3500 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3501 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3502 } 3503} 3504 3505static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component, 3506 int event, int mode) 3507{ 3508 switch (mode) { 3509 case CLS_H_LP: 3510 wcd9335_codec_hph_lp_config(component, event); 3511 break; 3512 case CLS_H_LOHIFI: 3513 wcd9335_codec_hph_lohifi_config(component, event); 3514 break; 3515 case CLS_H_HIFI: 3516 wcd9335_codec_hph_hifi_config(component, event); 3517 break; 3518 } 3519} 3520 3521static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 3522 struct snd_kcontrol *kc, 3523 int event) 3524{ 3525 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3526 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3527 int hph_mode = wcd->hph_mode; 3528 u8 dem_inp; 3529 3530 switch (event) { 3531 case SND_SOC_DAPM_PRE_PMU: 3532 /* Read DEM INP Select */ 3533 dem_inp = snd_soc_component_read(comp, 3534 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03; 3535 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3536 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3537 dev_err(comp->dev, "Incorrect DEM Input\n"); 3538 return -EINVAL; 3539 } 3540 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3541 WCD_CLSH_STATE_HPHL, 3542 ((hph_mode == CLS_H_LOHIFI) ? 3543 CLS_H_HIFI : hph_mode)); 3544 3545 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3546 3547 break; 3548 case SND_SOC_DAPM_POST_PMU: 3549 usleep_range(1000, 1100); 3550 break; 3551 case SND_SOC_DAPM_PRE_PMD: 3552 break; 3553 case SND_SOC_DAPM_POST_PMD: 3554 /* 1000us required as per HW requirement */ 3555 usleep_range(1000, 1100); 3556 3557 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3558 WCD_CLSH_STATE_HPHR)) 3559 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3560 3561 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3562 WCD_CLSH_STATE_HPHL, 3563 ((hph_mode == CLS_H_LOHIFI) ? 3564 CLS_H_HIFI : hph_mode)); 3565 break; 3566 } 3567 3568 return 0; 3569} 3570 3571static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 3572 struct snd_kcontrol *kc, int event) 3573{ 3574 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3575 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3576 3577 switch (event) { 3578 case SND_SOC_DAPM_PRE_PMU: 3579 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3580 WCD_CLSH_STATE_LO, CLS_AB); 3581 break; 3582 case SND_SOC_DAPM_POST_PMD: 3583 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3584 WCD_CLSH_STATE_LO, CLS_AB); 3585 break; 3586 } 3587 3588 return 0; 3589} 3590 3591static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 3592 struct snd_kcontrol *kc, int event) 3593{ 3594 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3595 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3596 3597 switch (event) { 3598 case SND_SOC_DAPM_PRE_PMU: 3599 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3600 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3601 3602 break; 3603 case SND_SOC_DAPM_POST_PMD: 3604 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3605 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3606 break; 3607 } 3608 3609 return 0; 3610} 3611 3612static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd, 3613 int mode, int event) 3614{ 3615 u8 scale_val = 0; 3616 3617 switch (event) { 3618 case SND_SOC_DAPM_POST_PMU: 3619 switch (mode) { 3620 case CLS_H_HIFI: 3621 scale_val = 0x3; 3622 break; 3623 case CLS_H_LOHIFI: 3624 scale_val = 0x1; 3625 break; 3626 } 3627 break; 3628 case SND_SOC_DAPM_PRE_PMD: 3629 scale_val = 0x6; 3630 break; 3631 } 3632 3633 if (scale_val) 3634 snd_soc_component_update_bits(wcd->component, 3635 WCD9335_HPH_PA_CTL1, 3636 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3637 scale_val << 1); 3638 if (SND_SOC_DAPM_EVENT_ON(event)) { 3639 if (wcd->comp_enabled[COMPANDER_1] || 3640 wcd->comp_enabled[COMPANDER_2]) { 3641 /* GAIN Source Selection */ 3642 snd_soc_component_update_bits(wcd->component, 3643 WCD9335_HPH_L_EN, 3644 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3645 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3646 snd_soc_component_update_bits(wcd->component, 3647 WCD9335_HPH_R_EN, 3648 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3649 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3650 snd_soc_component_update_bits(wcd->component, 3651 WCD9335_HPH_AUTO_CHOP, 3652 WCD9335_HPH_AUTO_CHOP_MASK, 3653 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE); 3654 } 3655 snd_soc_component_update_bits(wcd->component, 3656 WCD9335_HPH_L_EN, 3657 WCD9335_HPH_PA_GAIN_MASK, 3658 wcd->hph_l_gain); 3659 snd_soc_component_update_bits(wcd->component, 3660 WCD9335_HPH_R_EN, 3661 WCD9335_HPH_PA_GAIN_MASK, 3662 wcd->hph_r_gain); 3663 } 3664 3665 if (SND_SOC_DAPM_EVENT_OFF(event)) 3666 snd_soc_component_update_bits(wcd->component, 3667 WCD9335_HPH_AUTO_CHOP, 3668 WCD9335_HPH_AUTO_CHOP_MASK, 3669 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN); 3670} 3671 3672static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 3673 struct snd_kcontrol *kc, 3674 int event) 3675{ 3676 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3677 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3678 int hph_mode = wcd->hph_mode; 3679 u8 dem_inp; 3680 3681 switch (event) { 3682 case SND_SOC_DAPM_PRE_PMU: 3683 3684 /* Read DEM INP Select */ 3685 dem_inp = snd_soc_component_read(comp, 3686 WCD9335_CDC_RX2_RX_PATH_SEC0) & 3687 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK; 3688 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3689 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3690 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n", 3691 hph_mode); 3692 return -EINVAL; 3693 } 3694 3695 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, 3696 WCD_CLSH_EVENT_PRE_DAC, 3697 WCD_CLSH_STATE_HPHR, 3698 ((hph_mode == CLS_H_LOHIFI) ? 3699 CLS_H_HIFI : hph_mode)); 3700 3701 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3702 3703 break; 3704 case SND_SOC_DAPM_POST_PMD: 3705 /* 1000us required as per HW requirement */ 3706 usleep_range(1000, 1100); 3707 3708 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3709 WCD_CLSH_STATE_HPHL)) 3710 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3711 3712 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3713 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ? 3714 CLS_H_HIFI : hph_mode)); 3715 break; 3716 } 3717 3718 return 0; 3719} 3720 3721static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 3722 struct snd_kcontrol *kc, 3723 int event) 3724{ 3725 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3726 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3727 int hph_mode = wcd->hph_mode; 3728 3729 switch (event) { 3730 case SND_SOC_DAPM_PRE_PMU: 3731 break; 3732 case SND_SOC_DAPM_POST_PMU: 3733 /* 3734 * 7ms sleep is required after PA is enabled as per 3735 * HW requirement 3736 */ 3737 usleep_range(7000, 7100); 3738 3739 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3740 snd_soc_component_update_bits(comp, 3741 WCD9335_CDC_RX1_RX_PATH_CTL, 3742 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3743 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3744 3745 /* Remove mix path mute if it is enabled */ 3746 if ((snd_soc_component_read(comp, 3747 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) & 3748 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3749 snd_soc_component_update_bits(comp, 3750 WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 3751 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3752 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3753 3754 break; 3755 case SND_SOC_DAPM_PRE_PMD: 3756 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3757 break; 3758 case SND_SOC_DAPM_POST_PMD: 3759 /* 5ms sleep is required after PA is disabled as per 3760 * HW requirement 3761 */ 3762 usleep_range(5000, 5500); 3763 break; 3764 } 3765 3766 return 0; 3767} 3768 3769static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w, 3770 struct snd_kcontrol *kc, 3771 int event) 3772{ 3773 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3774 int vol_reg = 0, mix_vol_reg = 0; 3775 3776 if (w->reg == WCD9335_ANA_LO_1_2) { 3777 if (w->shift == 7) { 3778 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3779 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL; 3780 } else if (w->shift == 6) { 3781 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3782 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL; 3783 } 3784 } else if (w->reg == WCD9335_ANA_LO_3_4) { 3785 if (w->shift == 7) { 3786 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3787 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL; 3788 } else if (w->shift == 6) { 3789 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3790 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL; 3791 } 3792 } else { 3793 dev_err(comp->dev, "Error enabling lineout PA\n"); 3794 return -EINVAL; 3795 } 3796 3797 switch (event) { 3798 case SND_SOC_DAPM_POST_PMU: 3799 /* 5ms sleep is required after PA is enabled as per 3800 * HW requirement 3801 */ 3802 usleep_range(5000, 5500); 3803 snd_soc_component_update_bits(comp, vol_reg, 3804 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3805 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3806 3807 /* Remove mix path mute if it is enabled */ 3808 if ((snd_soc_component_read(comp, mix_vol_reg)) & 3809 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3810 snd_soc_component_update_bits(comp, mix_vol_reg, 3811 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3812 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3813 break; 3814 case SND_SOC_DAPM_POST_PMD: 3815 /* 5ms sleep is required after PA is disabled as per 3816 * HW requirement 3817 */ 3818 usleep_range(5000, 5500); 3819 break; 3820 } 3821 3822 return 0; 3823} 3824 3825static void wcd9335_codec_init_flyback(struct snd_soc_component *component) 3826{ 3827 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 3828 WCD9335_HPH_CONST_SEL_L_MASK, 3829 WCD9335_HPH_CONST_SEL_L_BYPASS); 3830 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 3831 WCD9335_HPH_CONST_SEL_L_MASK, 3832 WCD9335_HPH_CONST_SEL_L_BYPASS); 3833 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3834 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK, 3835 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3836 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3837 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK, 3838 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3839} 3840 3841static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, 3842 struct snd_kcontrol *kc, int event) 3843{ 3844 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3845 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3846 3847 switch (event) { 3848 case SND_SOC_DAPM_PRE_PMU: 3849 wcd->rx_bias_count++; 3850 if (wcd->rx_bias_count == 1) { 3851 wcd9335_codec_init_flyback(comp); 3852 snd_soc_component_update_bits(comp, 3853 WCD9335_ANA_RX_SUPPLIES, 3854 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3855 WCD9335_ANA_RX_BIAS_ENABLE); 3856 } 3857 break; 3858 case SND_SOC_DAPM_POST_PMD: 3859 wcd->rx_bias_count--; 3860 if (!wcd->rx_bias_count) 3861 snd_soc_component_update_bits(comp, 3862 WCD9335_ANA_RX_SUPPLIES, 3863 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3864 WCD9335_ANA_RX_BIAS_DISABLE); 3865 break; 3866 } 3867 3868 return 0; 3869} 3870 3871static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 3872 struct snd_kcontrol *kc, int event) 3873{ 3874 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3875 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3876 int hph_mode = wcd->hph_mode; 3877 3878 switch (event) { 3879 case SND_SOC_DAPM_PRE_PMU: 3880 break; 3881 case SND_SOC_DAPM_POST_PMU: 3882 /* 3883 * 7ms sleep is required after PA is enabled as per 3884 * HW requirement 3885 */ 3886 usleep_range(7000, 7100); 3887 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3888 snd_soc_component_update_bits(comp, 3889 WCD9335_CDC_RX2_RX_PATH_CTL, 3890 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3891 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3892 /* Remove mix path mute if it is enabled */ 3893 if ((snd_soc_component_read(comp, 3894 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) & 3895 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3896 snd_soc_component_update_bits(comp, 3897 WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 3898 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3899 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3900 3901 break; 3902 3903 case SND_SOC_DAPM_PRE_PMD: 3904 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3905 break; 3906 case SND_SOC_DAPM_POST_PMD: 3907 /* 5ms sleep is required after PA is disabled as per 3908 * HW requirement 3909 */ 3910 usleep_range(5000, 5500); 3911 break; 3912 } 3913 3914 return 0; 3915} 3916 3917static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 3918 struct snd_kcontrol *kc, int event) 3919{ 3920 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3921 3922 switch (event) { 3923 case SND_SOC_DAPM_POST_PMU: 3924 /* 5ms sleep is required after PA is enabled as per 3925 * HW requirement 3926 */ 3927 usleep_range(5000, 5500); 3928 snd_soc_component_update_bits(comp, 3929 WCD9335_CDC_RX0_RX_PATH_CTL, 3930 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3931 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3932 /* Remove mix path mute if it is enabled */ 3933 if ((snd_soc_component_read(comp, 3934 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) & 3935 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3936 snd_soc_component_update_bits(comp, 3937 WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 3938 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3939 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3940 break; 3941 case SND_SOC_DAPM_POST_PMD: 3942 /* 5ms sleep is required after PA is disabled as per 3943 * HW requirement 3944 */ 3945 usleep_range(5000, 5500); 3946 3947 break; 3948 } 3949 3950 return 0; 3951} 3952 3953static irqreturn_t wcd9335_slimbus_irq(int irq, void *data) 3954{ 3955 struct wcd9335_codec *wcd = data; 3956 unsigned long status = 0; 3957 int i, j, port_id; 3958 unsigned int val, int_val = 0; 3959 irqreturn_t ret = IRQ_NONE; 3960 bool tx; 3961 unsigned short reg = 0; 3962 3963 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 3964 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 3965 regmap_read(wcd->if_regmap, i, &val); 3966 status |= ((u32)val << (8 * j)); 3967 } 3968 3969 for_each_set_bit(j, &status, 32) { 3970 tx = (j >= 16); 3971 port_id = (tx ? j - 16 : j); 3972 regmap_read(wcd->if_regmap, 3973 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 3974 if (val) { 3975 if (!tx) 3976 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 3977 (port_id / 8); 3978 else 3979 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 3980 (port_id / 8); 3981 regmap_read( 3982 wcd->if_regmap, reg, &int_val); 3983 /* 3984 * Ignore interrupts for ports for which the 3985 * interrupts are not specifically enabled. 3986 */ 3987 if (!(int_val & (1 << (port_id % 8)))) 3988 continue; 3989 } 3990 3991 if (val & WCD9335_SLIM_IRQ_OVERFLOW) 3992 dev_err_ratelimited(wcd->dev, 3993 "%s: overflow error on %s port %d, value %x\n", 3994 __func__, (tx ? "TX" : "RX"), port_id, val); 3995 3996 if (val & WCD9335_SLIM_IRQ_UNDERFLOW) 3997 dev_err_ratelimited(wcd->dev, 3998 "%s: underflow error on %s port %d, value %x\n", 3999 __func__, (tx ? "TX" : "RX"), port_id, val); 4000 4001 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) || 4002 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) { 4003 if (!tx) 4004 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 4005 (port_id / 8); 4006 else 4007 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 4008 (port_id / 8); 4009 regmap_read( 4010 wcd->if_regmap, reg, &int_val); 4011 if (int_val & (1 << (port_id % 8))) { 4012 int_val = int_val ^ (1 << (port_id % 8)); 4013 regmap_write(wcd->if_regmap, 4014 reg, int_val); 4015 } 4016 } 4017 4018 regmap_write(wcd->if_regmap, 4019 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 4020 BIT(j % 8)); 4021 ret = IRQ_HANDLED; 4022 } 4023 4024 return ret; 4025} 4026 4027static struct wcd9335_irq wcd9335_irqs[] = { 4028 { 4029 .irq = WCD9335_IRQ_SLIMBUS, 4030 .handler = wcd9335_slimbus_irq, 4031 .name = "SLIM Slave", 4032 }, 4033}; 4034 4035static int wcd9335_setup_irqs(struct wcd9335_codec *wcd) 4036{ 4037 int irq, ret, i; 4038 4039 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) { 4040 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq); 4041 if (irq < 0) { 4042 dev_err(wcd->dev, "Failed to get %s\n", 4043 wcd9335_irqs[i].name); 4044 return irq; 4045 } 4046 4047 ret = devm_request_threaded_irq(wcd->dev, irq, NULL, 4048 wcd9335_irqs[i].handler, 4049 IRQF_TRIGGER_RISING | 4050 IRQF_ONESHOT, 4051 wcd9335_irqs[i].name, wcd); 4052 if (ret) { 4053 dev_err(wcd->dev, "Failed to request %s\n", 4054 wcd9335_irqs[i].name); 4055 return ret; 4056 } 4057 } 4058 4059 /* enable interrupts on all slave ports */ 4060 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4061 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4062 0xFF); 4063 4064 return ret; 4065} 4066 4067static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd) 4068{ 4069 int i; 4070 4071 /* disable interrupts on all slave ports */ 4072 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4073 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4074 0x00); 4075} 4076 4077static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd, 4078 bool ccl_flag) 4079{ 4080 struct snd_soc_component *comp = wcd->component; 4081 4082 if (ccl_flag) { 4083 if (++wcd->sido_ccl_cnt == 1) 4084 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4085 WCD9335_SIDO_SIDO_CCL_DEF_VALUE); 4086 } else { 4087 if (wcd->sido_ccl_cnt == 0) { 4088 dev_err(wcd->dev, "sido_ccl already disabled\n"); 4089 return; 4090 } 4091 if (--wcd->sido_ccl_cnt == 0) 4092 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4093 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF); 4094 } 4095} 4096 4097static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd) 4098{ 4099 wcd->master_bias_users++; 4100 if (wcd->master_bias_users == 1) { 4101 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4102 WCD9335_ANA_BIAS_EN_MASK, 4103 WCD9335_ANA_BIAS_ENABLE); 4104 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4105 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4106 WCD9335_ANA_BIAS_PRECHRG_ENABLE); 4107 /* 4108 * 1ms delay is required after pre-charge is enabled 4109 * as per HW requirement 4110 */ 4111 usleep_range(1000, 1100); 4112 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4113 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4114 WCD9335_ANA_BIAS_PRECHRG_DISABLE); 4115 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4116 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4117 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4118 } 4119 4120 return 0; 4121} 4122 4123static int wcd9335_enable_mclk(struct wcd9335_codec *wcd) 4124{ 4125 /* Enable mclk requires master bias to be enabled first */ 4126 if (wcd->master_bias_users <= 0) 4127 return -EINVAL; 4128 4129 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || 4130 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { 4131 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n", 4132 wcd->clk_type); 4133 return -EINVAL; 4134 } 4135 4136 if (++wcd->clk_mclk_users == 1) { 4137 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4138 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4139 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE); 4140 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4141 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4142 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL); 4143 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4144 WCD9335_ANA_CLK_MCLK_EN_MASK, 4145 WCD9335_ANA_CLK_MCLK_ENABLE); 4146 regmap_update_bits(wcd->regmap, 4147 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 4148 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK, 4149 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE); 4150 regmap_update_bits(wcd->regmap, 4151 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL, 4152 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK, 4153 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE); 4154 /* 4155 * 10us sleep is required after clock is enabled 4156 * as per HW requirement 4157 */ 4158 usleep_range(10, 15); 4159 } 4160 4161 wcd->clk_type = WCD_CLK_MCLK; 4162 4163 return 0; 4164} 4165 4166static int wcd9335_disable_mclk(struct wcd9335_codec *wcd) 4167{ 4168 if (wcd->clk_mclk_users <= 0) 4169 return -EINVAL; 4170 4171 if (--wcd->clk_mclk_users == 0) { 4172 if (wcd->clk_rco_users > 0) { 4173 /* MCLK to RCO switch */ 4174 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4175 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4176 WCD9335_ANA_CLK_MCLK_SRC_RCO); 4177 wcd->clk_type = WCD_CLK_RCO; 4178 } else { 4179 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4180 WCD9335_ANA_CLK_MCLK_EN_MASK, 4181 WCD9335_ANA_CLK_MCLK_DISABLE); 4182 wcd->clk_type = WCD_CLK_OFF; 4183 } 4184 4185 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4186 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4187 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE); 4188 } 4189 4190 return 0; 4191} 4192 4193static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd) 4194{ 4195 if (wcd->master_bias_users <= 0) 4196 return -EINVAL; 4197 4198 wcd->master_bias_users--; 4199 if (wcd->master_bias_users == 0) { 4200 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4201 WCD9335_ANA_BIAS_EN_MASK, 4202 WCD9335_ANA_BIAS_DISABLE); 4203 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4204 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4205 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4206 } 4207 return 0; 4208} 4209 4210static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd, 4211 bool enable) 4212{ 4213 int ret = 0; 4214 4215 if (enable) { 4216 wcd9335_cdc_sido_ccl_enable(wcd, true); 4217 ret = clk_prepare_enable(wcd->mclk); 4218 if (ret) { 4219 dev_err(wcd->dev, "%s: ext clk enable failed\n", 4220 __func__); 4221 goto err; 4222 } 4223 /* get BG */ 4224 wcd9335_enable_master_bias(wcd); 4225 /* get MCLK */ 4226 wcd9335_enable_mclk(wcd); 4227 4228 } else { 4229 /* put MCLK */ 4230 wcd9335_disable_mclk(wcd); 4231 /* put BG */ 4232 wcd9335_disable_master_bias(wcd); 4233 clk_disable_unprepare(wcd->mclk); 4234 wcd9335_cdc_sido_ccl_enable(wcd, false); 4235 } 4236err: 4237 return ret; 4238} 4239 4240static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd, 4241 enum wcd9335_sido_voltage req_mv) 4242{ 4243 struct snd_soc_component *comp = wcd->component; 4244 int vout_d_val; 4245 4246 if (req_mv == wcd->sido_voltage) 4247 return; 4248 4249 /* compute the vout_d step value */ 4250 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) & 4251 WCD9335_ANA_BUCK_VOUT_MASK; 4252 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val); 4253 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4254 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4255 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE); 4256 4257 /* 1 msec sleep required after SIDO Vout_D voltage change */ 4258 usleep_range(1000, 1100); 4259 wcd->sido_voltage = req_mv; 4260 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4261 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4262 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE); 4263} 4264 4265static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd, 4266 enum wcd9335_sido_voltage req_mv) 4267{ 4268 int ret = 0; 4269 4270 /* enable mclk before setting SIDO voltage */ 4271 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4272 if (ret) { 4273 dev_err(wcd->dev, "Ext clk enable failed\n"); 4274 goto err; 4275 } 4276 4277 wcd9335_codec_apply_sido_voltage(wcd, req_mv); 4278 wcd9335_cdc_req_mclk_enable(wcd, false); 4279 4280err: 4281 return ret; 4282} 4283 4284static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component, 4285 int enable) 4286{ 4287 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4288 int ret; 4289 4290 if (enable) { 4291 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4292 if (ret) 4293 return ret; 4294 4295 wcd9335_codec_apply_sido_voltage(wcd, 4296 SIDO_VOLTAGE_NOMINAL_MV); 4297 } else { 4298 wcd9335_codec_update_sido_voltage(wcd, 4299 wcd->sido_voltage); 4300 wcd9335_cdc_req_mclk_enable(wcd, false); 4301 } 4302 4303 return 0; 4304} 4305 4306static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w, 4307 struct snd_kcontrol *kc, int event) 4308{ 4309 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4310 4311 switch (event) { 4312 case SND_SOC_DAPM_PRE_PMU: 4313 return _wcd9335_codec_enable_mclk(comp, true); 4314 case SND_SOC_DAPM_POST_PMD: 4315 return _wcd9335_codec_enable_mclk(comp, false); 4316 } 4317 4318 return 0; 4319} 4320 4321static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = { 4322 /* TODO SPK1 & SPK2 OUT*/ 4323 SND_SOC_DAPM_OUTPUT("EAR"), 4324 SND_SOC_DAPM_OUTPUT("HPHL"), 4325 SND_SOC_DAPM_OUTPUT("HPHR"), 4326 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 4327 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 4328 SND_SOC_DAPM_OUTPUT("LINEOUT3"), 4329 SND_SOC_DAPM_OUTPUT("LINEOUT4"), 4330 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 4331 AIF1_PB, 0, wcd9335_codec_enable_slim, 4332 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4333 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 4334 AIF2_PB, 0, wcd9335_codec_enable_slim, 4335 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4336 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 4337 AIF3_PB, 0, wcd9335_codec_enable_slim, 4338 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4339 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 4340 AIF4_PB, 0, wcd9335_codec_enable_slim, 4341 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4342 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0, 4343 &slim_rx_mux[WCD9335_RX0]), 4344 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0, 4345 &slim_rx_mux[WCD9335_RX1]), 4346 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0, 4347 &slim_rx_mux[WCD9335_RX2]), 4348 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0, 4349 &slim_rx_mux[WCD9335_RX3]), 4350 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0, 4351 &slim_rx_mux[WCD9335_RX4]), 4352 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0, 4353 &slim_rx_mux[WCD9335_RX5]), 4354 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0, 4355 &slim_rx_mux[WCD9335_RX6]), 4356 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0, 4357 &slim_rx_mux[WCD9335_RX7]), 4358 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 4359 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4360 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4361 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 4362 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 4363 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 4364 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 4365 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 4366 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 4367 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path, 4368 SND_SOC_DAPM_POST_PMU), 4369 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 4370 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path, 4371 SND_SOC_DAPM_POST_PMU), 4372 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 4373 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path, 4374 SND_SOC_DAPM_POST_PMU), 4375 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL, 4376 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path, 4377 SND_SOC_DAPM_POST_PMU), 4378 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL, 4379 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path, 4380 SND_SOC_DAPM_POST_PMU), 4381 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL, 4382 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path, 4383 SND_SOC_DAPM_POST_PMU), 4384 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL, 4385 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path, 4386 SND_SOC_DAPM_POST_PMU), 4387 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL, 4388 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path, 4389 SND_SOC_DAPM_POST_PMU), 4390 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL, 4391 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path, 4392 SND_SOC_DAPM_POST_PMU), 4393 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4394 &rx_int0_1_mix_inp0_mux), 4395 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4396 &rx_int0_1_mix_inp1_mux), 4397 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4398 &rx_int0_1_mix_inp2_mux), 4399 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4400 &rx_int1_1_mix_inp0_mux), 4401 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4402 &rx_int1_1_mix_inp1_mux), 4403 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4404 &rx_int1_1_mix_inp2_mux), 4405 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4406 &rx_int2_1_mix_inp0_mux), 4407 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4408 &rx_int2_1_mix_inp1_mux), 4409 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4410 &rx_int2_1_mix_inp2_mux), 4411 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4412 &rx_int3_1_mix_inp0_mux), 4413 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4414 &rx_int3_1_mix_inp1_mux), 4415 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4416 &rx_int3_1_mix_inp2_mux), 4417 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4418 &rx_int4_1_mix_inp0_mux), 4419 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4420 &rx_int4_1_mix_inp1_mux), 4421 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4422 &rx_int4_1_mix_inp2_mux), 4423 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4424 &rx_int5_1_mix_inp0_mux), 4425 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4426 &rx_int5_1_mix_inp1_mux), 4427 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4428 &rx_int5_1_mix_inp2_mux), 4429 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4430 &rx_int6_1_mix_inp0_mux), 4431 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4432 &rx_int6_1_mix_inp1_mux), 4433 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4434 &rx_int6_1_mix_inp2_mux), 4435 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4436 &rx_int7_1_mix_inp0_mux), 4437 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4438 &rx_int7_1_mix_inp1_mux), 4439 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4440 &rx_int7_1_mix_inp2_mux), 4441 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4442 &rx_int8_1_mix_inp0_mux), 4443 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4444 &rx_int8_1_mix_inp1_mux), 4445 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4446 &rx_int8_1_mix_inp2_mux), 4447 4448 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4449 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4450 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4451 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4452 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4453 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4454 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4455 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4456 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4457 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4458 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4459 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4460 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4461 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4462 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4463 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4464 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4465 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4466 4467 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4468 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4469 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4470 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4471 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4472 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4473 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4474 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4475 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4476 4477 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 4478 &rx_int0_dem_inp_mux), 4479 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 4480 &rx_int1_dem_inp_mux), 4481 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 4482 &rx_int2_dem_inp_mux), 4483 4484 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM, 4485 INTERP_EAR, 0, &rx_int0_interp_mux, 4486 wcd9335_codec_enable_interpolator, 4487 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4488 SND_SOC_DAPM_POST_PMD), 4489 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM, 4490 INTERP_HPHL, 0, &rx_int1_interp_mux, 4491 wcd9335_codec_enable_interpolator, 4492 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4493 SND_SOC_DAPM_POST_PMD), 4494 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM, 4495 INTERP_HPHR, 0, &rx_int2_interp_mux, 4496 wcd9335_codec_enable_interpolator, 4497 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4498 SND_SOC_DAPM_POST_PMD), 4499 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM, 4500 INTERP_LO1, 0, &rx_int3_interp_mux, 4501 wcd9335_codec_enable_interpolator, 4502 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4503 SND_SOC_DAPM_POST_PMD), 4504 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM, 4505 INTERP_LO2, 0, &rx_int4_interp_mux, 4506 wcd9335_codec_enable_interpolator, 4507 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4508 SND_SOC_DAPM_POST_PMD), 4509 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM, 4510 INTERP_LO3, 0, &rx_int5_interp_mux, 4511 wcd9335_codec_enable_interpolator, 4512 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4513 SND_SOC_DAPM_POST_PMD), 4514 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM, 4515 INTERP_LO4, 0, &rx_int6_interp_mux, 4516 wcd9335_codec_enable_interpolator, 4517 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4518 SND_SOC_DAPM_POST_PMD), 4519 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM, 4520 INTERP_SPKR1, 0, &rx_int7_interp_mux, 4521 wcd9335_codec_enable_interpolator, 4522 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4523 SND_SOC_DAPM_POST_PMD), 4524 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM, 4525 INTERP_SPKR2, 0, &rx_int8_interp_mux, 4526 wcd9335_codec_enable_interpolator, 4527 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4528 SND_SOC_DAPM_POST_PMD), 4529 4530 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 4531 0, 0, wcd9335_codec_ear_dac_event, 4532 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4533 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4534 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH, 4535 5, 0, wcd9335_codec_hphl_dac_event, 4536 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4537 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4538 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH, 4539 4, 0, wcd9335_codec_hphr_dac_event, 4540 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4541 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4542 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 4543 0, 0, wcd9335_codec_lineout_dac_event, 4544 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4545 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 4546 0, 0, wcd9335_codec_lineout_dac_event, 4547 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4548 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM, 4549 0, 0, wcd9335_codec_lineout_dac_event, 4550 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4551 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM, 4552 0, 0, wcd9335_codec_lineout_dac_event, 4553 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4554 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0, 4555 wcd9335_codec_enable_hphl_pa, 4556 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4557 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4558 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0, 4559 wcd9335_codec_enable_hphr_pa, 4560 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4561 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4562 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0, 4563 wcd9335_codec_enable_ear_pa, 4564 SND_SOC_DAPM_POST_PMU | 4565 SND_SOC_DAPM_POST_PMD), 4566 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0, 4567 wcd9335_codec_enable_lineout_pa, 4568 SND_SOC_DAPM_POST_PMU | 4569 SND_SOC_DAPM_POST_PMD), 4570 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0, 4571 wcd9335_codec_enable_lineout_pa, 4572 SND_SOC_DAPM_POST_PMU | 4573 SND_SOC_DAPM_POST_PMD), 4574 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0, 4575 wcd9335_codec_enable_lineout_pa, 4576 SND_SOC_DAPM_POST_PMU | 4577 SND_SOC_DAPM_POST_PMD), 4578 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0, 4579 wcd9335_codec_enable_lineout_pa, 4580 SND_SOC_DAPM_POST_PMU | 4581 SND_SOC_DAPM_POST_PMD), 4582 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0, 4583 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU | 4584 SND_SOC_DAPM_POST_PMD), 4585 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 4586 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU | 4587 SND_SOC_DAPM_POST_PMD), 4588 4589 /* TX */ 4590 SND_SOC_DAPM_INPUT("AMIC1"), 4591 SND_SOC_DAPM_INPUT("AMIC2"), 4592 SND_SOC_DAPM_INPUT("AMIC3"), 4593 SND_SOC_DAPM_INPUT("AMIC4"), 4594 SND_SOC_DAPM_INPUT("AMIC5"), 4595 SND_SOC_DAPM_INPUT("AMIC6"), 4596 4597 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 4598 AIF1_CAP, 0, wcd9335_codec_enable_slim, 4599 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4600 4601 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 4602 AIF2_CAP, 0, wcd9335_codec_enable_slim, 4603 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4604 4605 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 4606 AIF3_CAP, 0, wcd9335_codec_enable_slim, 4607 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4608 4609 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0, 4610 wcd9335_codec_enable_micbias, 4611 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4612 SND_SOC_DAPM_POST_PMD), 4613 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0, 4614 wcd9335_codec_enable_micbias, 4615 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4616 SND_SOC_DAPM_POST_PMD), 4617 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0, 4618 wcd9335_codec_enable_micbias, 4619 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4620 SND_SOC_DAPM_POST_PMD), 4621 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0, 4622 wcd9335_codec_enable_micbias, 4623 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4624 SND_SOC_DAPM_POST_PMD), 4625 4626 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0, 4627 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4628 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0, 4629 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4630 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0, 4631 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4632 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0, 4633 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4634 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0, 4635 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4636 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0, 4637 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4638 4639 /* Digital Mic Inputs */ 4640 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 4641 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4642 SND_SOC_DAPM_POST_PMD), 4643 4644 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 4645 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4646 SND_SOC_DAPM_POST_PMD), 4647 4648 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 4649 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4650 SND_SOC_DAPM_POST_PMD), 4651 4652 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 4653 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4654 SND_SOC_DAPM_POST_PMD), 4655 4656 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 4657 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4658 SND_SOC_DAPM_POST_PMD), 4659 4660 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 4661 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4662 SND_SOC_DAPM_POST_PMD), 4663 4664 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, 4665 &tx_dmic_mux0), 4666 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, 4667 &tx_dmic_mux1), 4668 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, 4669 &tx_dmic_mux2), 4670 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, 4671 &tx_dmic_mux3), 4672 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, 4673 &tx_dmic_mux4), 4674 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, 4675 &tx_dmic_mux5), 4676 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, 4677 &tx_dmic_mux6), 4678 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, 4679 &tx_dmic_mux7), 4680 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, 4681 &tx_dmic_mux8), 4682 4683 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, 4684 &tx_amic_mux0), 4685 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, 4686 &tx_amic_mux1), 4687 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, 4688 &tx_amic_mux2), 4689 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, 4690 &tx_amic_mux3), 4691 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, 4692 &tx_amic_mux4), 4693 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, 4694 &tx_amic_mux5), 4695 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, 4696 &tx_amic_mux6), 4697 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, 4698 &tx_amic_mux7), 4699 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, 4700 &tx_amic_mux8), 4701 4702 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 4703 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)), 4704 4705 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 4706 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)), 4707 4708 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 4709 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)), 4710 4711 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0, 4712 &sb_tx0_mux), 4713 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0, 4714 &sb_tx1_mux), 4715 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0, 4716 &sb_tx2_mux), 4717 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0, 4718 &sb_tx3_mux), 4719 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0, 4720 &sb_tx4_mux), 4721 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0, 4722 &sb_tx5_mux), 4723 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0, 4724 &sb_tx6_mux), 4725 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0, 4726 &sb_tx7_mux), 4727 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0, 4728 &sb_tx8_mux), 4729 4730 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0, 4731 &tx_adc_mux0, wcd9335_codec_enable_dec, 4732 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4733 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4734 4735 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0, 4736 &tx_adc_mux1, wcd9335_codec_enable_dec, 4737 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4738 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4739 4740 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0, 4741 &tx_adc_mux2, wcd9335_codec_enable_dec, 4742 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4743 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4744 4745 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0, 4746 &tx_adc_mux3, wcd9335_codec_enable_dec, 4747 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4748 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4749 4750 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0, 4751 &tx_adc_mux4, wcd9335_codec_enable_dec, 4752 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4753 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4754 4755 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0, 4756 &tx_adc_mux5, wcd9335_codec_enable_dec, 4757 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4758 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4759 4760 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0, 4761 &tx_adc_mux6, wcd9335_codec_enable_dec, 4762 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4763 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4764 4765 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0, 4766 &tx_adc_mux7, wcd9335_codec_enable_dec, 4767 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4768 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4769 4770 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0, 4771 &tx_adc_mux8, wcd9335_codec_enable_dec, 4772 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4773 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4774}; 4775 4776static void wcd9335_enable_sido_buck(struct snd_soc_component *component) 4777{ 4778 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4779 4780 snd_soc_component_update_bits(component, WCD9335_ANA_RCO, 4781 WCD9335_ANA_RCO_BG_EN_MASK, 4782 WCD9335_ANA_RCO_BG_ENABLE); 4783 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4784 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK, 4785 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT); 4786 /* 100us sleep needed after IREF settings */ 4787 usleep_range(100, 110); 4788 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4789 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK, 4790 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT); 4791 /* 100us sleep needed after VREF settings */ 4792 usleep_range(100, 110); 4793 wcd->sido_input_src = SIDO_SOURCE_RCO_BG; 4794} 4795 4796static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp) 4797{ 4798 _wcd9335_codec_enable_mclk(comp, true); 4799 snd_soc_component_update_bits(comp, 4800 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 4801 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK, 4802 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE); 4803 /* 4804 * 5ms sleep required after enabling efuse control 4805 * before checking the status. 4806 */ 4807 usleep_range(5000, 5500); 4808 4809 if (!(snd_soc_component_read(comp, 4810 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) & 4811 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK)) 4812 WARN(1, "%s: Efuse sense is not complete\n", __func__); 4813 4814 wcd9335_enable_sido_buck(comp); 4815 _wcd9335_codec_enable_mclk(comp, false); 4816 4817 return 0; 4818} 4819 4820static void wcd9335_codec_init(struct snd_soc_component *component) 4821{ 4822 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4823 int i; 4824 4825 /* ungate MCLK and set clk rate */ 4826 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE, 4827 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0); 4828 4829 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4830 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4831 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4832 4833 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++) 4834 snd_soc_component_update_bits(component, 4835 wcd9335_codec_reg_init[i].reg, 4836 wcd9335_codec_reg_init[i].mask, 4837 wcd9335_codec_reg_init[i].val); 4838 4839 wcd9335_enable_efuse_sensing(component); 4840} 4841 4842static int wcd9335_codec_probe(struct snd_soc_component *component) 4843{ 4844 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4845 int ret; 4846 int i; 4847 4848 snd_soc_component_init_regmap(component, wcd->regmap); 4849 /* Class-H Init*/ 4850 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335); 4851 if (IS_ERR(wcd->clsh_ctrl)) 4852 return PTR_ERR(wcd->clsh_ctrl); 4853 4854 /* Default HPH Mode to Class-H HiFi */ 4855 wcd->hph_mode = CLS_H_HIFI; 4856 wcd->component = component; 4857 4858 wcd9335_codec_init(component); 4859 4860 for (i = 0; i < NUM_CODEC_DAIS; i++) 4861 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 4862 4863 ret = wcd9335_setup_irqs(wcd); 4864 if (ret) 4865 goto free_clsh_ctrl; 4866 4867 return 0; 4868 4869free_clsh_ctrl: 4870 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4871 return ret; 4872} 4873 4874static void wcd9335_codec_remove(struct snd_soc_component *comp) 4875{ 4876 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4877 4878 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4879 wcd9335_teardown_irqs(wcd); 4880} 4881 4882static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp, 4883 int clk_id, int source, 4884 unsigned int freq, int dir) 4885{ 4886 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4887 4888 wcd->mclk_rate = freq; 4889 4890 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ) 4891 snd_soc_component_update_bits(comp, 4892 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4893 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4894 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ); 4895 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 4896 snd_soc_component_update_bits(comp, 4897 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4898 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4899 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4900 4901 return clk_set_rate(wcd->mclk, freq); 4902} 4903 4904static const struct snd_soc_component_driver wcd9335_component_drv = { 4905 .probe = wcd9335_codec_probe, 4906 .remove = wcd9335_codec_remove, 4907 .set_sysclk = wcd9335_codec_set_sysclk, 4908 .controls = wcd9335_snd_controls, 4909 .num_controls = ARRAY_SIZE(wcd9335_snd_controls), 4910 .dapm_widgets = wcd9335_dapm_widgets, 4911 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets), 4912 .dapm_routes = wcd9335_audio_map, 4913 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map), 4914 .endianness = 1, 4915}; 4916 4917static int wcd9335_probe(struct wcd9335_codec *wcd) 4918{ 4919 struct device *dev = wcd->dev; 4920 4921 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs)); 4922 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs)); 4923 4924 wcd->sido_input_src = SIDO_SOURCE_INTERNAL; 4925 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV; 4926 4927 return devm_snd_soc_register_component(dev, &wcd9335_component_drv, 4928 wcd9335_slim_dais, 4929 ARRAY_SIZE(wcd9335_slim_dais)); 4930} 4931 4932static const struct regmap_range_cfg wcd9335_ranges[] = { 4933 { 4934 .name = "WCD9335", 4935 .range_min = 0x0, 4936 .range_max = WCD9335_MAX_REGISTER, 4937 .selector_reg = WCD9335_SEL_REGISTER, 4938 .selector_mask = 0xff, 4939 .selector_shift = 0, 4940 .window_start = 0x800, 4941 .window_len = 0x100, 4942 }, 4943}; 4944 4945static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg) 4946{ 4947 switch (reg) { 4948 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3: 4949 case WCD9335_ANA_MBHC_RESULT_3: 4950 case WCD9335_ANA_MBHC_RESULT_2: 4951 case WCD9335_ANA_MBHC_RESULT_1: 4952 case WCD9335_ANA_MBHC_MECH: 4953 case WCD9335_ANA_MBHC_ELECT: 4954 case WCD9335_ANA_MBHC_ZDET: 4955 case WCD9335_ANA_MICB2: 4956 case WCD9335_ANA_RCO: 4957 case WCD9335_ANA_BIAS: 4958 return true; 4959 default: 4960 return false; 4961 } 4962} 4963 4964static struct regmap_config wcd9335_regmap_config = { 4965 .reg_bits = 16, 4966 .val_bits = 8, 4967 .cache_type = REGCACHE_MAPLE, 4968 .max_register = WCD9335_MAX_REGISTER, 4969 .can_multi_write = true, 4970 .ranges = wcd9335_ranges, 4971 .num_ranges = ARRAY_SIZE(wcd9335_ranges), 4972 .volatile_reg = wcd9335_is_volatile_register, 4973}; 4974 4975static const struct regmap_range_cfg wcd9335_ifc_ranges[] = { 4976 { 4977 .name = "WCD9335-IFC-DEV", 4978 .range_min = 0x0, 4979 .range_max = WCD9335_MAX_REGISTER, 4980 .selector_reg = WCD9335_SEL_REGISTER, 4981 .selector_mask = 0xfff, 4982 .selector_shift = 0, 4983 .window_start = 0x800, 4984 .window_len = 0x400, 4985 }, 4986}; 4987 4988static struct regmap_config wcd9335_ifc_regmap_config = { 4989 .reg_bits = 16, 4990 .val_bits = 8, 4991 .can_multi_write = true, 4992 .max_register = WCD9335_MAX_REGISTER, 4993 .ranges = wcd9335_ifc_ranges, 4994 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges), 4995}; 4996 4997static const struct regmap_irq wcd9335_codec_irqs[] = { 4998 /* INTR_REG 0 */ 4999 [WCD9335_IRQ_SLIMBUS] = { 5000 .reg_offset = 0, 5001 .mask = BIT(0), 5002 .type = { 5003 .type_reg_offset = 0, 5004 .types_supported = IRQ_TYPE_EDGE_BOTH, 5005 .type_reg_mask = BIT(0), 5006 }, 5007 }, 5008}; 5009 5010static const unsigned int wcd9335_config_regs[] = { 5011 WCD9335_INTR_LEVEL0, 5012}; 5013 5014static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = { 5015 .name = "wcd9335_pin1_irq", 5016 .status_base = WCD9335_INTR_PIN1_STATUS0, 5017 .mask_base = WCD9335_INTR_PIN1_MASK0, 5018 .ack_base = WCD9335_INTR_PIN1_CLEAR0, 5019 .num_regs = 4, 5020 .irqs = wcd9335_codec_irqs, 5021 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs), 5022 .config_base = wcd9335_config_regs, 5023 .num_config_bases = ARRAY_SIZE(wcd9335_config_regs), 5024 .num_config_regs = 4, 5025 .set_type_config = regmap_irq_set_type_config_simple, 5026}; 5027 5028static int wcd9335_parse_dt(struct wcd9335_codec *wcd) 5029{ 5030 struct device *dev = wcd->dev; 5031 struct device_node *np = dev->of_node; 5032 int ret; 5033 5034 wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0); 5035 if (wcd->reset_gpio < 0) { 5036 dev_err(dev, "Reset GPIO missing from DT\n"); 5037 return wcd->reset_gpio; 5038 } 5039 5040 wcd->mclk = devm_clk_get(dev, "mclk"); 5041 if (IS_ERR(wcd->mclk)) { 5042 dev_err(dev, "mclk not found\n"); 5043 return PTR_ERR(wcd->mclk); 5044 } 5045 5046 wcd->native_clk = devm_clk_get(dev, "slimbus"); 5047 if (IS_ERR(wcd->native_clk)) { 5048 dev_err(dev, "slimbus clock not found\n"); 5049 return PTR_ERR(wcd->native_clk); 5050 } 5051 5052 wcd->supplies[0].supply = "vdd-buck"; 5053 wcd->supplies[1].supply = "vdd-buck-sido"; 5054 wcd->supplies[2].supply = "vdd-tx"; 5055 wcd->supplies[3].supply = "vdd-rx"; 5056 wcd->supplies[4].supply = "vdd-io"; 5057 5058 ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies); 5059 if (ret) { 5060 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5061 return ret; 5062 } 5063 5064 return 0; 5065} 5066 5067static int wcd9335_power_on_reset(struct wcd9335_codec *wcd) 5068{ 5069 struct device *dev = wcd->dev; 5070 int ret; 5071 5072 ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies); 5073 if (ret) { 5074 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5075 return ret; 5076 } 5077 5078 /* 5079 * For WCD9335, it takes about 600us for the Vout_A and 5080 * Vout_D to be ready after BUCK_SIDO is powered up. 5081 * SYS_RST_N shouldn't be pulled high during this time 5082 * Toggle the reset line to make sure the reset pulse is 5083 * correctly applied 5084 */ 5085 usleep_range(600, 650); 5086 5087 gpio_direction_output(wcd->reset_gpio, 0); 5088 msleep(20); 5089 gpio_set_value(wcd->reset_gpio, 1); 5090 msleep(20); 5091 5092 return 0; 5093} 5094 5095static int wcd9335_bring_up(struct wcd9335_codec *wcd) 5096{ 5097 struct regmap *rm = wcd->regmap; 5098 int val, byte0; 5099 5100 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val); 5101 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0); 5102 5103 if ((val < 0) || (byte0 < 0)) { 5104 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n"); 5105 return -EINVAL; 5106 } 5107 5108 if (byte0 == 0x1) { 5109 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n"); 5110 wcd->version = WCD9335_VERSION_2_0; 5111 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01); 5112 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00); 5113 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F); 5114 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65); 5115 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); 5116 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); 5117 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); 5118 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3); 5119 } else { 5120 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n"); 5121 return -EINVAL; 5122 } 5123 5124 return 0; 5125} 5126 5127static int wcd9335_irq_init(struct wcd9335_codec *wcd) 5128{ 5129 int ret; 5130 5131 /* 5132 * INTR1 consists of all possible interrupt sources Ear OCP, 5133 * HPH OCP, MBHC, MAD, VBAT, and SVA 5134 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA 5135 */ 5136 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1"); 5137 if (wcd->intr1 < 0) 5138 return dev_err_probe(wcd->dev, wcd->intr1, 5139 "Unable to configure IRQ\n"); 5140 5141 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1, 5142 IRQF_TRIGGER_HIGH, 0, 5143 &wcd9335_regmap_irq1_chip, &wcd->irq_data); 5144 if (ret) 5145 return dev_err_probe(wcd->dev, ret, "Failed to register IRQ chip\n"); 5146 5147 return 0; 5148} 5149 5150static int wcd9335_slim_probe(struct slim_device *slim) 5151{ 5152 struct device *dev = &slim->dev; 5153 struct wcd9335_codec *wcd; 5154 int ret; 5155 5156 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5157 if (!wcd) 5158 return -ENOMEM; 5159 5160 wcd->dev = dev; 5161 ret = wcd9335_parse_dt(wcd); 5162 if (ret) { 5163 dev_err(dev, "Error parsing DT: %d\n", ret); 5164 return ret; 5165 } 5166 5167 ret = wcd9335_power_on_reset(wcd); 5168 if (ret) 5169 return ret; 5170 5171 dev_set_drvdata(dev, wcd); 5172 5173 return 0; 5174} 5175 5176static int wcd9335_slim_status(struct slim_device *sdev, 5177 enum slim_device_status status) 5178{ 5179 struct device *dev = &sdev->dev; 5180 struct device_node *ifc_dev_np; 5181 struct wcd9335_codec *wcd; 5182 int ret; 5183 5184 wcd = dev_get_drvdata(dev); 5185 5186 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5187 if (!ifc_dev_np) { 5188 dev_err(dev, "No Interface device found\n"); 5189 return -EINVAL; 5190 } 5191 5192 wcd->slim = sdev; 5193 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np); 5194 of_node_put(ifc_dev_np); 5195 if (!wcd->slim_ifc_dev) { 5196 dev_err(dev, "Unable to get SLIM Interface device\n"); 5197 return -EINVAL; 5198 } 5199 5200 slim_get_logical_addr(wcd->slim_ifc_dev); 5201 5202 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config); 5203 if (IS_ERR(wcd->regmap)) 5204 return dev_err_probe(dev, PTR_ERR(wcd->regmap), 5205 "Failed to allocate slim register map\n"); 5206 5207 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev, 5208 &wcd9335_ifc_regmap_config); 5209 if (IS_ERR(wcd->if_regmap)) 5210 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap), 5211 "Failed to allocate ifc register map\n"); 5212 5213 ret = wcd9335_bring_up(wcd); 5214 if (ret) { 5215 dev_err(dev, "Failed to bringup WCD9335\n"); 5216 return ret; 5217 } 5218 5219 ret = wcd9335_irq_init(wcd); 5220 if (ret) 5221 return ret; 5222 5223 wcd9335_probe(wcd); 5224 5225 return 0; 5226} 5227 5228static const struct slim_device_id wcd9335_slim_id[] = { 5229 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0}, 5230 {} 5231}; 5232MODULE_DEVICE_TABLE(slim, wcd9335_slim_id); 5233 5234static struct slim_driver wcd9335_slim_driver = { 5235 .driver = { 5236 .name = "wcd9335-slim", 5237 }, 5238 .probe = wcd9335_slim_probe, 5239 .device_status = wcd9335_slim_status, 5240 .id_table = wcd9335_slim_id, 5241}; 5242 5243module_slim_driver(wcd9335_slim_driver); 5244MODULE_DESCRIPTION("WCD9335 slim driver"); 5245MODULE_LICENSE("GPL v2"); 5246MODULE_ALIAS("slim:217:1a0:*"); 5247