1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * ALSA SoC TLV320AIC3X codec driver 4 * 5 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 6 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 7 */ 8 9#ifndef _AIC3X_H 10#define _AIC3X_H 11 12struct device; 13struct regmap_config; 14 15extern const struct regmap_config aic3x_regmap; 16int aic3x_probe(struct device *dev, struct regmap *regmap, kernel_ulong_t driver_data); 17void aic3x_remove(struct device *dev); 18 19#define AIC3X_MODEL_3X 0 20#define AIC3X_MODEL_33 1 21#define AIC3X_MODEL_3007 2 22#define AIC3X_MODEL_3104 3 23#define AIC3X_MODEL_3106 4 24 25/* AIC3X register space */ 26#define AIC3X_CACHEREGNUM 110 27 28/* Page select register */ 29#define AIC3X_PAGE_SELECT 0 30/* Software reset register */ 31#define AIC3X_RESET 1 32/* Codec Sample rate select register */ 33#define AIC3X_SAMPLE_RATE_SEL_REG 2 34/* PLL progrramming register A */ 35#define AIC3X_PLL_PROGA_REG 3 36/* PLL progrramming register B */ 37#define AIC3X_PLL_PROGB_REG 4 38/* PLL progrramming register C */ 39#define AIC3X_PLL_PROGC_REG 5 40/* PLL progrramming register D */ 41#define AIC3X_PLL_PROGD_REG 6 42/* Codec datapath setup register */ 43#define AIC3X_CODEC_DATAPATH_REG 7 44/* Audio serial data interface control register A */ 45#define AIC3X_ASD_INTF_CTRLA 8 46/* Audio serial data interface control register B */ 47#define AIC3X_ASD_INTF_CTRLB 9 48/* Audio serial data interface control register C */ 49#define AIC3X_ASD_INTF_CTRLC 10 50/* Audio overflow status and PLL R value programming register */ 51#define AIC3X_OVRF_STATUS_AND_PLLR_REG 11 52/* Audio codec digital filter control register */ 53#define AIC3X_CODEC_DFILT_CTRL 12 54/* Headset/button press detection register */ 55#define AIC3X_HEADSET_DETECT_CTRL_A 13 56#define AIC3X_HEADSET_DETECT_CTRL_B 14 57/* ADC PGA Gain control registers */ 58#define LADC_VOL 15 59#define RADC_VOL 16 60/* MIC3 control registers */ 61#define MIC3LR_2_LADC_CTRL 17 62#define MIC3LR_2_RADC_CTRL 18 63/* Line1 Input control registers */ 64#define LINE1L_2_LADC_CTRL 19 65#define LINE1R_2_LADC_CTRL 21 66#define LINE1R_2_RADC_CTRL 22 67#define LINE1L_2_RADC_CTRL 24 68/* Line2 Input control registers */ 69#define LINE2L_2_LADC_CTRL 20 70#define LINE2R_2_RADC_CTRL 23 71/* MICBIAS Control Register */ 72#define MICBIAS_CTRL 25 73 74/* AGC Control Registers A, B, C */ 75#define LAGC_CTRL_A 26 76#define LAGC_CTRL_B 27 77#define LAGC_CTRL_C 28 78#define RAGC_CTRL_A 29 79#define RAGC_CTRL_B 30 80#define RAGC_CTRL_C 31 81 82/* DAC Power and Left High Power Output control registers */ 83#define DAC_PWR 37 84#define HPLCOM_CFG 37 85/* Right High Power Output control registers */ 86#define HPRCOM_CFG 38 87/* High Power Output Stage Control Register */ 88#define HPOUT_SC 40 89/* DAC Output Switching control registers */ 90#define DAC_LINE_MUX 41 91/* High Power Output Driver Pop Reduction registers */ 92#define HPOUT_POP_REDUCTION 42 93/* DAC Digital control registers */ 94#define LDAC_VOL 43 95#define RDAC_VOL 44 96/* Left High Power Output control registers */ 97#define LINE2L_2_HPLOUT_VOL 45 98#define PGAL_2_HPLOUT_VOL 46 99#define DACL1_2_HPLOUT_VOL 47 100#define LINE2R_2_HPLOUT_VOL 48 101#define PGAR_2_HPLOUT_VOL 49 102#define DACR1_2_HPLOUT_VOL 50 103#define HPLOUT_CTRL 51 104/* Left High Power COM control registers */ 105#define LINE2L_2_HPLCOM_VOL 52 106#define PGAL_2_HPLCOM_VOL 53 107#define DACL1_2_HPLCOM_VOL 54 108#define LINE2R_2_HPLCOM_VOL 55 109#define PGAR_2_HPLCOM_VOL 56 110#define DACR1_2_HPLCOM_VOL 57 111#define HPLCOM_CTRL 58 112/* Right High Power Output control registers */ 113#define LINE2L_2_HPROUT_VOL 59 114#define PGAL_2_HPROUT_VOL 60 115#define DACL1_2_HPROUT_VOL 61 116#define LINE2R_2_HPROUT_VOL 62 117#define PGAR_2_HPROUT_VOL 63 118#define DACR1_2_HPROUT_VOL 64 119#define HPROUT_CTRL 65 120/* Right High Power COM control registers */ 121#define LINE2L_2_HPRCOM_VOL 66 122#define PGAL_2_HPRCOM_VOL 67 123#define DACL1_2_HPRCOM_VOL 68 124#define LINE2R_2_HPRCOM_VOL 69 125#define PGAR_2_HPRCOM_VOL 70 126#define DACR1_2_HPRCOM_VOL 71 127#define HPRCOM_CTRL 72 128/* Mono Line Output Plus/Minus control registers */ 129#define LINE2L_2_MONOLOPM_VOL 73 130#define PGAL_2_MONOLOPM_VOL 74 131#define DACL1_2_MONOLOPM_VOL 75 132#define LINE2R_2_MONOLOPM_VOL 76 133#define PGAR_2_MONOLOPM_VOL 77 134#define DACR1_2_MONOLOPM_VOL 78 135#define MONOLOPM_CTRL 79 136/* Class-D speaker driver on tlv320aic3007 */ 137#define CLASSD_CTRL 73 138/* Left Line Output Plus/Minus control registers */ 139#define LINE2L_2_LLOPM_VOL 80 140#define PGAL_2_LLOPM_VOL 81 141#define DACL1_2_LLOPM_VOL 82 142#define LINE2R_2_LLOPM_VOL 83 143#define PGAR_2_LLOPM_VOL 84 144#define DACR1_2_LLOPM_VOL 85 145#define LLOPM_CTRL 86 146/* Right Line Output Plus/Minus control registers */ 147#define LINE2L_2_RLOPM_VOL 87 148#define PGAL_2_RLOPM_VOL 88 149#define DACL1_2_RLOPM_VOL 89 150#define LINE2R_2_RLOPM_VOL 90 151#define PGAR_2_RLOPM_VOL 91 152#define DACR1_2_RLOPM_VOL 92 153#define RLOPM_CTRL 93 154/* GPIO/IRQ registers */ 155#define AIC3X_STICKY_IRQ_FLAGS_REG 96 156#define AIC3X_RT_IRQ_FLAGS_REG 97 157#define AIC3X_GPIO1_REG 98 158#define AIC3X_GPIO2_REG 99 159#define AIC3X_GPIOA_REG 100 160#define AIC3X_GPIOB_REG 101 161/* Clock generation control register */ 162#define AIC3X_CLKGEN_CTRL_REG 102 163/* New AGC registers */ 164#define LAGCN_ATTACK 103 165#define LAGCN_DECAY 104 166#define RAGCN_ATTACK 105 167#define RAGCN_DECAY 106 168/* New Programmable ADC Digital Path and I2C Bus Condition Register */ 169#define NEW_ADC_DIGITALPATH 107 170/* Passive Analog Signal Bypass Selection During Powerdown Register */ 171#define PASSIVE_BYPASS 108 172/* DAC Quiescent Current Adjustment Register */ 173#define DAC_ICC_ADJ 109 174 175/* Page select register bits */ 176#define PAGE0_SELECT 0 177#define PAGE1_SELECT 1 178 179/* Audio serial data interface control register A bits */ 180#define BIT_CLK_MASTER 0x80 181#define WORD_CLK_MASTER 0x40 182#define DOUT_TRISTATE 0x20 183 184/* Codec Datapath setup register 7 */ 185#define FSREF_44100 (1 << 7) 186#define FSREF_48000 (0 << 7) 187#define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) 188#define LDAC2LCH (0x1 << 3) 189#define RDAC2RCH (0x1 << 1) 190#define LDAC2RCH (0x2 << 3) 191#define RDAC2LCH (0x2 << 1) 192#define LDAC2MONOMIX (0x3 << 3) 193#define RDAC2MONOMIX (0x3 << 1) 194 195/* PLL registers bitfields */ 196#define PLLP_SHIFT 0 197#define PLLP_MASK 7 198#define PLLQ_SHIFT 3 199#define PLLR_SHIFT 0 200#define PLLJ_SHIFT 2 201#define PLLD_MSB_SHIFT 0 202#define PLLD_LSB_SHIFT 2 203 204/* Clock generation register bits */ 205#define CODEC_CLKIN_PLLDIV 0 206#define CODEC_CLKIN_CLKDIV 1 207#define PLL_CLKIN_SHIFT 4 208#define MCLK_SOURCE 0x0 209#define PLL_CLKDIV_SHIFT 0 210#define PLLCLK_IN_MASK 0x30 211#define PLLCLK_IN_SHIFT 4 212#define CLKDIV_IN_MASK 0xc0 213#define CLKDIV_IN_SHIFT 6 214/* clock in source */ 215#define CLKIN_MCLK 0 216#define CLKIN_GPIO2 1 217#define CLKIN_BCLK 2 218 219/* Software reset register bits */ 220#define SOFT_RESET 0x80 221 222/* PLL progrramming register A bits */ 223#define PLL_ENABLE 0x80 224 225/* Route bits */ 226#define ROUTE_ON 0x80 227 228/* Mute bits */ 229#define UNMUTE 0x08 230#define MUTE_ON 0x80 231 232/* Power bits */ 233#define LADC_PWR_ON 0x04 234#define RADC_PWR_ON 0x04 235#define LDAC_PWR_ON 0x80 236#define RDAC_PWR_ON 0x40 237#define HPLOUT_PWR_ON 0x01 238#define HPROUT_PWR_ON 0x01 239#define HPLCOM_PWR_ON 0x01 240#define HPRCOM_PWR_ON 0x01 241#define MONOLOPM_PWR_ON 0x01 242#define LLOPM_PWR_ON 0x01 243#define RLOPM_PWR_ON 0x01 244 245#define INVERT_VOL(val) (0x7f - val) 246 247/* Default output volume (inverted) */ 248#define DEFAULT_VOL INVERT_VOL(0x50) 249/* Default input volume */ 250#define DEFAULT_GAIN 0x20 251 252/* MICBIAS Control Register */ 253#define MICBIAS_LEVEL_SHIFT (6) 254#define MICBIAS_LEVEL_MASK (3 << 6) 255 256/* HPOUT_SC */ 257#define HPOUT_SC_OCMV_MASK (3 << 6) 258#define HPOUT_SC_OCMV_SHIFT (6) 259#define HPOUT_SC_OCMV_1_35V 0 260#define HPOUT_SC_OCMV_1_5V 1 261#define HPOUT_SC_OCMV_1_65V 2 262#define HPOUT_SC_OCMV_1_8V 3 263 264/* headset detection / button API */ 265 266/* The AIC3x supports detection of stereo headsets (GND + left + right signal) 267 * and cellular headsets (GND + speaker output + microphone input). 268 * It is recommended to enable MIC bias for this function to work properly. 269 * For more information, please refer to the datasheet. */ 270enum { 271 AIC3X_HEADSET_DETECT_OFF = 0, 272 AIC3X_HEADSET_DETECT_STEREO = 1, 273 AIC3X_HEADSET_DETECT_CELLULAR = 2, 274 AIC3X_HEADSET_DETECT_BOTH = 3 275}; 276 277enum { 278 AIC3X_HEADSET_DEBOUNCE_16MS = 0, 279 AIC3X_HEADSET_DEBOUNCE_32MS = 1, 280 AIC3X_HEADSET_DEBOUNCE_64MS = 2, 281 AIC3X_HEADSET_DEBOUNCE_128MS = 3, 282 AIC3X_HEADSET_DEBOUNCE_256MS = 4, 283 AIC3X_HEADSET_DEBOUNCE_512MS = 5 284}; 285 286enum { 287 AIC3X_BUTTON_DEBOUNCE_0MS = 0, 288 AIC3X_BUTTON_DEBOUNCE_8MS = 1, 289 AIC3X_BUTTON_DEBOUNCE_16MS = 2, 290 AIC3X_BUTTON_DEBOUNCE_32MS = 3 291}; 292 293#define AIC3X_HEADSET_DETECT_ENABLED 0x80 294#define AIC3X_HEADSET_DETECT_SHIFT 5 295#define AIC3X_HEADSET_DETECT_MASK 3 296#define AIC3X_HEADSET_DEBOUNCE_SHIFT 2 297#define AIC3X_HEADSET_DEBOUNCE_MASK 7 298#define AIC3X_BUTTON_DEBOUNCE_SHIFT 0 299#define AIC3X_BUTTON_DEBOUNCE_MASK 3 300 301/* GPIO API */ 302enum { 303 AIC3X_GPIO1_FUNC_DISABLED = 0, 304 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1, 305 AIC3X_GPIO1_FUNC_CLOCK_MUX = 2, 306 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3, 307 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4, 308 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5, 309 AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6, 310 AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7, 311 AIC3X_GPIO1_FUNC_INPUT = 8, 312 AIC3X_GPIO1_FUNC_OUTPUT = 9, 313 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10, 314 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11, 315 AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12, 316 AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13, 317 AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14, 318 AIC3X_GPIO1_FUNC_ALL_IRQ = 16 319}; 320 321enum { 322 AIC3X_GPIO2_FUNC_DISABLED = 0, 323 AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2, 324 AIC3X_GPIO2_FUNC_INPUT = 3, 325 AIC3X_GPIO2_FUNC_OUTPUT = 4, 326 AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5, 327 AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8, 328 AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9, 329 AIC3X_GPIO2_FUNC_ALL_IRQ = 10, 330 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11, 331 AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12, 332 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13, 333 AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14, 334 AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15 335}; 336 337enum aic3x_micbias_voltage { 338 AIC3X_MICBIAS_OFF = 0, 339 AIC3X_MICBIAS_2_0V = 1, 340 AIC3X_MICBIAS_2_5V = 2, 341 AIC3X_MICBIAS_AVDDV = 3, 342}; 343 344#endif /* _AIC3X_H */ 345