1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * RT1305.h -- RT1305 ALSA SoC amplifier component driver 4 * 5 * Copyright 2018 Realtek Semiconductor Corp. 6 * Author: Shuming Fan <shumingf@realtek.com> 7 */ 8 9#ifndef _RT1305_H_ 10#define _RT1305_H_ 11 12#define RT1305_DEVICE_ID_NUM 0x6251 13 14#define RT1305_RESET 0x00 15#define RT1305_CLK_1 0x04 16#define RT1305_CLK_2 0x05 17#define RT1305_CLK_3 0x06 18#define RT1305_DFLL_REG 0x07 19#define RT1305_CAL_EFUSE_CLOCK 0x08 20#define RT1305_PLL0_1 0x0a 21#define RT1305_PLL0_2 0x0b 22#define RT1305_PLL1_1 0x0c 23#define RT1305_PLL1_2 0x0d 24#define RT1305_MIXER_CTRL_1 0x10 25#define RT1305_MIXER_CTRL_2 0x11 26#define RT1305_DAC_SET_1 0x12 27#define RT1305_DAC_SET_2 0x14 28#define RT1305_ADC_SET_1 0x16 29#define RT1305_ADC_SET_2 0x17 30#define RT1305_ADC_SET_3 0x18 31#define RT1305_PATH_SET 0x20 32#define RT1305_SPDIF_IN_SET_1 0x22 33#define RT1305_SPDIF_IN_SET_2 0x24 34#define RT1305_SPDIF_IN_SET_3 0x26 35#define RT1305_SPDIF_OUT_SET_1 0x28 36#define RT1305_SPDIF_OUT_SET_2 0x2a 37#define RT1305_SPDIF_OUT_SET_3 0x2b 38#define RT1305_I2S_SET_1 0x2d 39#define RT1305_I2S_SET_2 0x2e 40#define RT1305_PBTL_MONO_MODE_SRC 0x2f 41#define RT1305_MANUALLY_I2C_DEVICE 0x32 42#define RT1305_POWER_STATUS 0x39 43#define RT1305_POWER_CTRL_1 0x3a 44#define RT1305_POWER_CTRL_2 0x3b 45#define RT1305_POWER_CTRL_3 0x3c 46#define RT1305_POWER_CTRL_4 0x3d 47#define RT1305_POWER_CTRL_5 0x3e 48#define RT1305_CLOCK_DETECT 0x3f 49#define RT1305_BIQUAD_SET_1 0x40 50#define RT1305_BIQUAD_SET_2 0x42 51#define RT1305_ADJUSTED_HPF_1 0x46 52#define RT1305_ADJUSTED_HPF_2 0x47 53#define RT1305_EQ_SET_1 0x4b 54#define RT1305_EQ_SET_2 0x4c 55#define RT1305_SPK_TEMP_PROTECTION_0 0x4f 56#define RT1305_SPK_TEMP_PROTECTION_1 0x50 57#define RT1305_SPK_TEMP_PROTECTION_2 0x51 58#define RT1305_SPK_TEMP_PROTECTION_3 0x52 59#define RT1305_SPK_DC_DETECT_1 0x53 60#define RT1305_SPK_DC_DETECT_2 0x54 61#define RT1305_LOUDNESS 0x58 62#define RT1305_THERMAL_FOLD_BACK_1 0x5e 63#define RT1305_THERMAL_FOLD_BACK_2 0x5f 64#define RT1305_SILENCE_DETECT 0x60 65#define RT1305_ALC_DRC_1 0x62 66#define RT1305_ALC_DRC_2 0x63 67#define RT1305_ALC_DRC_3 0x64 68#define RT1305_ALC_DRC_4 0x65 69#define RT1305_PRIV_INDEX 0x6a 70#define RT1305_PRIV_DATA 0x6c 71#define RT1305_SPK_EXCURSION_LIMITER_7 0x76 72#define RT1305_VERSION_ID 0x7a 73#define RT1305_VENDOR_ID 0x7c 74#define RT1305_DEVICE_ID 0x7e 75#define RT1305_EFUSE_1 0x80 76#define RT1305_EFUSE_2 0x81 77#define RT1305_EFUSE_3 0x82 78#define RT1305_DC_CALIB_1 0x90 79#define RT1305_DC_CALIB_2 0x91 80#define RT1305_DC_CALIB_3 0x92 81#define RT1305_DAC_OFFSET_1 0x93 82#define RT1305_DAC_OFFSET_2 0x94 83#define RT1305_DAC_OFFSET_3 0x95 84#define RT1305_DAC_OFFSET_4 0x96 85#define RT1305_DAC_OFFSET_5 0x97 86#define RT1305_DAC_OFFSET_6 0x98 87#define RT1305_DAC_OFFSET_7 0x99 88#define RT1305_DAC_OFFSET_8 0x9a 89#define RT1305_DAC_OFFSET_9 0x9b 90#define RT1305_DAC_OFFSET_10 0x9c 91#define RT1305_DAC_OFFSET_11 0x9d 92#define RT1305_DAC_OFFSET_12 0x9e 93#define RT1305_DAC_OFFSET_13 0x9f 94#define RT1305_DAC_OFFSET_14 0xa0 95#define RT1305_TRIM_1 0xb0 96#define RT1305_TRIM_2 0xb1 97#define RT1305_TUNE_INTERNAL_OSC 0xb2 98#define RT1305_BIQUAD1_H0_L_28_16 0xc0 99#define RT1305_BIQUAD3_A2_R_15_0 0xfb 100#define RT1305_MAX_REG 0xff 101 102/* CLOCK-1 (0x04) */ 103#define RT1305_SEL_PLL_SRC_2_MASK (0x1 << 15) 104#define RT1305_SEL_PLL_SRC_2_SFT 15 105#define RT1305_SEL_PLL_SRC_2_MCLK (0x0 << 15) 106#define RT1305_SEL_PLL_SRC_2_RCCLK (0x1 << 15) 107#define RT1305_DIV_PLL_SRC_2_MASK (0x3 << 13) 108#define RT1305_DIV_PLL_SRC_2_SFT 13 109#define RT1305_SEL_PLL_SRC_1_MASK (0x3 << 10) 110#define RT1305_SEL_PLL_SRC_1_SFT 10 111#define RT1305_SEL_PLL_SRC_1_PLL2 (0x0 << 10) 112#define RT1305_SEL_PLL_SRC_1_BCLK (0x1 << 10) 113#define RT1305_SEL_PLL_SRC_1_DFLL (0x2 << 10) 114#define RT1305_SEL_FS_SYS_PRE_MASK (0x3 << 8) 115#define RT1305_SEL_FS_SYS_PRE_SFT 8 116#define RT1305_SEL_FS_SYS_PRE_MCLK (0x0 << 8) 117#define RT1305_SEL_FS_SYS_PRE_PLL (0x1 << 8) 118#define RT1305_SEL_FS_SYS_PRE_RCCLK (0x2 << 8) 119#define RT1305_DIV_FS_SYS_MASK (0x7 << 4) 120#define RT1305_DIV_FS_SYS_SFT 4 121 122/* PLL1M/N/K Code-1 (0x0c) */ 123#define RT1305_PLL_1_M_SFT 12 124#define RT1305_PLL_1_M_BYPASS_MASK (0x1 << 11) 125#define RT1305_PLL_1_M_BYPASS_SFT 11 126#define RT1305_PLL_1_M_BYPASS (0x1 << 11) 127#define RT1305_PLL_1_N_MASK (0x1ff << 0) 128 129/* DAC Setting (0x14) */ 130#define RT1305_DVOL_MUTE_L_EN_SFT 15 131#define RT1305_DVOL_MUTE_R_EN_SFT 14 132 133/* I2S Setting-1 (0x2d) */ 134#define RT1305_SEL_I2S_OUT_MODE_MASK (0x1 << 15) 135#define RT1305_SEL_I2S_OUT_MODE_SFT 15 136#define RT1305_SEL_I2S_OUT_MODE_S (0x0 << 15) 137#define RT1305_SEL_I2S_OUT_MODE_M (0x1 << 15) 138 139/* I2S Setting-2 (0x2e) */ 140#define RT1305_I2S_DF_SEL_MASK (0x3 << 12) 141#define RT1305_I2S_DF_SEL_SFT 12 142#define RT1305_I2S_DF_SEL_I2S (0x0 << 12) 143#define RT1305_I2S_DF_SEL_LEFT (0x1 << 12) 144#define RT1305_I2S_DF_SEL_PCM_A (0x2 << 12) 145#define RT1305_I2S_DF_SEL_PCM_B (0x3 << 12) 146#define RT1305_I2S_DL_SEL_MASK (0x3 << 10) 147#define RT1305_I2S_DL_SEL_SFT 10 148#define RT1305_I2S_DL_SEL_16B (0x0 << 10) 149#define RT1305_I2S_DL_SEL_20B (0x1 << 10) 150#define RT1305_I2S_DL_SEL_24B (0x2 << 10) 151#define RT1305_I2S_DL_SEL_8B (0x3 << 10) 152#define RT1305_I2S_BCLK_MASK (0x1 << 9) 153#define RT1305_I2S_BCLK_SFT 9 154#define RT1305_I2S_BCLK_NORMAL (0x0 << 9) 155#define RT1305_I2S_BCLK_INV (0x1 << 9) 156 157/* Power Control-1 (0x3a) */ 158#define RT1305_POW_PDB_JD_MASK (0x1 << 12) 159#define RT1305_POW_PDB_JD (0x1 << 12) 160#define RT1305_POW_PDB_JD_BIT 12 161#define RT1305_POW_PLL0_EN (0x1 << 11) 162#define RT1305_POW_PLL0_EN_BIT 11 163#define RT1305_POW_PLL1_EN (0x1 << 10) 164#define RT1305_POW_PLL1_EN_BIT 10 165#define RT1305_POW_PDB_JD_POLARITY (0x1 << 9) 166#define RT1305_POW_PDB_JD_POLARITY_BIT 9 167#define RT1305_POW_MBIAS_LV (0x1 << 8) 168#define RT1305_POW_MBIAS_LV_BIT 8 169#define RT1305_POW_BG_MBIAS_LV (0x1 << 7) 170#define RT1305_POW_BG_MBIAS_LV_BIT 7 171#define RT1305_POW_LDO2 (0x1 << 6) 172#define RT1305_POW_LDO2_BIT 6 173#define RT1305_POW_BG2 (0x1 << 5) 174#define RT1305_POW_BG2_BIT 5 175#define RT1305_POW_LDO2_IB2 (0x1 << 4) 176#define RT1305_POW_LDO2_IB2_BIT 4 177#define RT1305_POW_VREF (0x1 << 3) 178#define RT1305_POW_VREF_BIT 3 179#define RT1305_POW_VREF1 (0x1 << 2) 180#define RT1305_POW_VREF1_BIT 2 181#define RT1305_POW_VREF2 (0x1 << 1) 182#define RT1305_POW_VREF2_BIT 1 183 184/* Power Control-2 (0x3b) */ 185#define RT1305_POW_DISC_VREF (1 << 15) 186#define RT1305_POW_DISC_VREF_BIT 15 187#define RT1305_POW_FASTB_VREF (1 << 14) 188#define RT1305_POW_FASTB_VREF_BIT 14 189#define RT1305_POW_ULTRA_FAST_VREF (1 << 13) 190#define RT1305_POW_ULTRA_FAST_VREF_BIT 13 191#define RT1305_POW_CKXEN_DAC (1 << 12) 192#define RT1305_POW_CKXEN_DAC_BIT 12 193#define RT1305_POW_EN_CKGEN_DAC (1 << 11) 194#define RT1305_POW_EN_CKGEN_DAC_BIT 11 195#define RT1305_POW_DAC1_L (1 << 10) 196#define RT1305_POW_DAC1_L_BIT 10 197#define RT1305_POW_DAC1_R (1 << 9) 198#define RT1305_POW_DAC1_R_BIT 9 199#define RT1305_POW_CLAMP (1 << 8) 200#define RT1305_POW_CLAMP_BIT 8 201#define RT1305_POW_BUFL (1 << 7) 202#define RT1305_POW_BUFL_BIT 7 203#define RT1305_POW_BUFR (1 << 6) 204#define RT1305_POW_BUFR_BIT 6 205#define RT1305_POW_EN_CKGEN_ADC (1 << 5) 206#define RT1305_POW_EN_CKGEN_ADC_BIT 5 207#define RT1305_POW_ADC3_L (1 << 4) 208#define RT1305_POW_ADC3_L_BIT 4 209#define RT1305_POW_ADC3_R (1 << 3) 210#define RT1305_POW_ADC3_R_BIT 3 211#define RT1305_POW_TRIOSC (1 << 2) 212#define RT1305_POW_TRIOSC_BIT 2 213#define RT1305_POR_AVDD1 (1 << 1) 214#define RT1305_POR_AVDD1_BIT 1 215#define RT1305_POR_AVDD2 (1 << 0) 216#define RT1305_POR_AVDD2_BIT 0 217 218/* Power Control-3 (0x3c) */ 219#define RT1305_POW_VSENSE_RCH (1 << 15) 220#define RT1305_POW_VSENSE_RCH_BIT 15 221#define RT1305_POW_VSENSE_LCH (1 << 14) 222#define RT1305_POW_VSENSE_LCH_BIT 14 223#define RT1305_POW_ISENSE_RCH (1 << 13) 224#define RT1305_POW_ISENSE_RCH_BIT 13 225#define RT1305_POW_ISENSE_LCH (1 << 12) 226#define RT1305_POW_ISENSE_LCH_BIT 12 227#define RT1305_POW_POR_AVDD1 (1 << 11) 228#define RT1305_POW_POR_AVDD1_BIT 11 229#define RT1305_POW_POR_AVDD2 (1 << 10) 230#define RT1305_POW_POR_AVDD2_BIT 10 231#define RT1305_EN_K_HV (1 << 9) 232#define RT1305_EN_K_HV_BIT 9 233#define RT1305_EN_PRE_K_HV (1 << 8) 234#define RT1305_EN_PRE_K_HV_BIT 8 235#define RT1305_EN_EFUSE_1P8V (1 << 7) 236#define RT1305_EN_EFUSE_1P8V_BIT 7 237#define RT1305_EN_EFUSE_5V (1 << 6) 238#define RT1305_EN_EFUSE_5V_BIT 6 239#define RT1305_EN_VCM_6172 (1 << 5) 240#define RT1305_EN_VCM_6172_BIT 5 241#define RT1305_POR_EFUSE (1 << 4) 242#define RT1305_POR_EFUSE_BIT 4 243 244/* Clock Detect (0x3f) */ 245#define RT1305_SEL_CLK_DET_SRC_MASK (0x1 << 12) 246#define RT1305_SEL_CLK_DET_SRC_SFT 12 247#define RT1305_SEL_CLK_DET_SRC_MCLK (0x0 << 12) 248#define RT1305_SEL_CLK_DET_SRC_BCLK (0x1 << 12) 249 250 251/* System Clock Source */ 252enum { 253 RT1305_FS_SYS_PRE_S_MCLK, 254 RT1305_FS_SYS_PRE_S_PLL1, 255 RT1305_FS_SYS_PRE_S_RCCLK, /* 98.304M Hz */ 256}; 257 258/* PLL Source 1/2 */ 259enum { 260 RT1305_PLL1_S_BCLK, 261 RT1305_PLL2_S_MCLK, 262 RT1305_PLL2_S_RCCLK, /* 98.304M Hz */ 263}; 264 265enum { 266 RT1305_AIF1, 267 RT1305_AIFS 268}; 269 270#define R0_UPPER 0x2E8BA2 //5.5 ohm 271#define R0_LOWER 0x666666 //2.5 ohm 272 273#endif /* end of _RT1305_H_ */ 274