1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * PCM3060 codec driver
4 *
5 * Copyright (C) 2018 Kirill Marinushkin <kmarinushkin@birdec.com>
6 */
7
8#ifndef _SND_SOC_PCM3060_H
9#define _SND_SOC_PCM3060_H
10
11#include <linux/device.h>
12#include <linux/regmap.h>
13
14extern const struct regmap_config pcm3060_regmap;
15
16#define PCM3060_DAI_ID_DAC	0
17#define PCM3060_DAI_ID_ADC	1
18#define PCM3060_DAI_IDS_NUM	2
19
20/* ADC and DAC can be clocked from separate or same sources CLK1 and CLK2 */
21#define PCM3060_CLK_DEF	0 /* default: CLK1->ADC, CLK2->DAC */
22#define PCM3060_CLK1		1
23#define PCM3060_CLK2		2
24
25struct pcm3060_priv_dai {
26	bool is_provider;
27	unsigned int sclk_freq;
28};
29
30struct pcm3060_priv {
31	struct regmap *regmap;
32	struct pcm3060_priv_dai dai[PCM3060_DAI_IDS_NUM];
33	u8 out_se: 1;
34};
35
36int pcm3060_probe(struct device *dev);
37int pcm3060_remove(struct device *dev);
38
39/* registers */
40
41#define PCM3060_REG64			0x40
42#define PCM3060_REG_MRST		0x80
43#define PCM3060_REG_SRST		0x40
44#define PCM3060_REG_ADPSV		0x20
45#define PCM3060_REG_SHIFT_ADPSV	0x05
46#define PCM3060_REG_DAPSV		0x10
47#define PCM3060_REG_SHIFT_DAPSV	0x04
48#define PCM3060_REG_SE			0x01
49
50#define PCM3060_REG65			0x41
51#define PCM3060_REG66			0x42
52#define PCM3060_REG_AT2_MIN		0x36
53#define PCM3060_REG_AT2_MAX		0xFF
54
55#define PCM3060_REG67			0x43
56#define PCM3060_REG72			0x48
57#define PCM3060_REG_CSEL		0x80
58#define PCM3060_REG_MASK_MS		0x70
59#define PCM3060_REG_MS_S		0x00
60#define PCM3060_REG_MS_M768		(0x01 << 4)
61#define PCM3060_REG_MS_M512		(0x02 << 4)
62#define PCM3060_REG_MS_M384		(0x03 << 4)
63#define PCM3060_REG_MS_M256		(0x04 << 4)
64#define PCM3060_REG_MS_M192		(0x05 << 4)
65#define PCM3060_REG_MS_M128		(0x06 << 4)
66#define PCM3060_REG_MASK_FMT		0x03
67#define PCM3060_REG_FMT_I2S		0x00
68#define PCM3060_REG_FMT_LJ		0x01
69#define PCM3060_REG_FMT_RJ		0x02
70
71#define PCM3060_REG68			0x44
72#define PCM3060_REG_OVER		0x40
73#define PCM3060_REG_DREV2		0x04
74#define PCM3060_REG_SHIFT_MUT21	0x00
75#define PCM3060_REG_SHIFT_MUT22	0x01
76
77#define PCM3060_REG69			0x45
78#define PCM3060_REG_FLT		0x80
79#define PCM3060_REG_MASK_DMF		0x60
80#define PCM3060_REG_DMC		0x10
81#define PCM3060_REG_ZREV		0x02
82#define PCM3060_REG_AZRO		0x01
83
84#define PCM3060_REG70			0x46
85#define PCM3060_REG71			0x47
86#define PCM3060_REG_AT1_MIN		0x0E
87#define PCM3060_REG_AT1_MAX		0xFF
88
89#define PCM3060_REG73			0x49
90#define PCM3060_REG_ZCDD		0x10
91#define PCM3060_REG_BYP		0x08
92#define PCM3060_REG_DREV1		0x04
93#define PCM3060_REG_SHIFT_MUT11	0x00
94#define PCM3060_REG_SHIFT_MUT12	0x01
95
96#endif /* _SND_SOC_PCM3060_H */
97