1// SPDX-License-Identifier: GPL-2.0-only 2// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4#include <linux/module.h> 5#include <linux/init.h> 6#include <linux/clk.h> 7#include <linux/io.h> 8#include <linux/platform_device.h> 9#include <linux/pm_runtime.h> 10#include <linux/regmap.h> 11#include <sound/soc.h> 12#include <sound/soc-dapm.h> 13#include <sound/tlv.h> 14#include <linux/of_clk.h> 15#include <linux/clk-provider.h> 16 17#include "lpass-macro-common.h" 18 19#define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 20#define CDC_TX_MCLK_EN_MASK BIT(0) 21#define CDC_TX_MCLK_ENABLE BIT(0) 22#define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 23#define CDC_TX_FS_CNT_EN_MASK BIT(0) 24#define CDC_TX_FS_CNT_ENABLE BIT(0) 25#define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008) 26#define CDC_TX_SWR_RESET_MASK BIT(1) 27#define CDC_TX_SWR_RESET_ENABLE BIT(1) 28#define CDC_TX_SWR_CLK_EN_MASK BIT(0) 29#define CDC_TX_SWR_CLK_ENABLE BIT(0) 30#define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080) 31#define CDC_TX_TOP_CSR_ANC_CFG (0x0084) 32#define CDC_TX_TOP_CSR_SWR_CTRL (0x0088) 33#define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090) 34#define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094) 35#define CDC_TX_TOP_CSR_DEBUG_EN (0x0098) 36#define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4) 37#define CDC_TX_TOP_CSR_I2S_CLK (0x00A8) 38#define CDC_TX_TOP_CSR_I2S_RESET (0x00AC) 39#define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4) 40#define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0) 41/* Default divider for AMIC and DMIC clock: DIV2 */ 42#define CDC_TX_SWR_MIC_CLK_DEFAULT 0 43#define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1) 44#define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4) 45#define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8) 46#define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC) 47#define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0) 48#define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4) 49#define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n) 50#define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0) 51#define CDC_TX_MACRO_DMIC_MUX_SEL_MASK GENMASK(7, 4) 52#define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100) 53#define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n) 54#define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104) 55#define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108) 56#define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C) 57#define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110) 58#define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114) 59#define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118) 60#define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C) 61#define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120) 62#define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124) 63#define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128) 64#define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C) 65#define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130) 66#define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134) 67#define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138) 68#define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C) 69#define CDC_TX_ANC0_CLK_RESET_CTL (0x0200) 70#define CDC_TX_ANC0_MODE_1_CTL (0x0204) 71#define CDC_TX_ANC0_MODE_2_CTL (0x0208) 72#define CDC_TX_ANC0_FF_SHIFT (0x020C) 73#define CDC_TX_ANC0_FB_SHIFT (0x0210) 74#define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214) 75#define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218) 76#define CDC_TX_ANC0_LPF_FB_CTL (0x021C) 77#define CDC_TX_ANC0_SMLPF_CTL (0x0220) 78#define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224) 79#define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228) 80#define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C) 81#define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230) 82#define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234) 83#define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238) 84#define CDC_TX_ANC0_FB_GAIN_CTL (0x023C) 85#define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n) 86#define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0) 87#define CDC_TXn_PGA_MUTE_MASK BIT(4) 88#define CDC_TXn_CLK_EN_MASK BIT(5) 89#define CDC_TX0_TX_PATH_CTL (0x0400) 90#define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n) 91#define CDC_TX0_TX_PATH_CFG0 (0x0404) 92#define CDC_TXn_PH_EN_MASK BIT(0) 93#define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1) 94#define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5) 95#define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7) 96#define CDC_TX0_TX_PATH_CFG1 (0x0408) 97#define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n) 98#define CDC_TX0_TX_VOL_CTL (0x040C) 99#define CDC_TX0_TX_PATH_SEC0 (0x0410) 100#define CDC_TX0_TX_PATH_SEC1 (0x0414) 101#define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n) 102#define CDC_TXn_HPF_F_CHANGE_MASK BIT(1) 103#define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0) 104#define CDC_TX0_TX_PATH_SEC2 (0x0418) 105#define CDC_TX0_TX_PATH_SEC3 (0x041C) 106#define CDC_TX0_TX_PATH_SEC4 (0x0420) 107#define CDC_TX0_TX_PATH_SEC5 (0x0424) 108#define CDC_TX0_TX_PATH_SEC6 (0x0428) 109#define CDC_TX0_TX_PATH_SEC7 (0x042C) 110#define CDC_TX0_MBHC_CTL_EN_MASK BIT(6) 111#define CDC_TX1_TX_PATH_CTL (0x0480) 112#define CDC_TX1_TX_PATH_CFG0 (0x0484) 113#define CDC_TX1_TX_PATH_CFG1 (0x0488) 114#define CDC_TX1_TX_VOL_CTL (0x048C) 115#define CDC_TX1_TX_PATH_SEC0 (0x0490) 116#define CDC_TX1_TX_PATH_SEC1 (0x0494) 117#define CDC_TX1_TX_PATH_SEC2 (0x0498) 118#define CDC_TX1_TX_PATH_SEC3 (0x049C) 119#define CDC_TX1_TX_PATH_SEC4 (0x04A0) 120#define CDC_TX1_TX_PATH_SEC5 (0x04A4) 121#define CDC_TX1_TX_PATH_SEC6 (0x04A8) 122#define CDC_TX2_TX_PATH_CTL (0x0500) 123#define CDC_TX2_TX_PATH_CFG0 (0x0504) 124#define CDC_TX2_TX_PATH_CFG1 (0x0508) 125#define CDC_TX2_TX_VOL_CTL (0x050C) 126#define CDC_TX2_TX_PATH_SEC0 (0x0510) 127#define CDC_TX2_TX_PATH_SEC1 (0x0514) 128#define CDC_TX2_TX_PATH_SEC2 (0x0518) 129#define CDC_TX2_TX_PATH_SEC3 (0x051C) 130#define CDC_TX2_TX_PATH_SEC4 (0x0520) 131#define CDC_TX2_TX_PATH_SEC5 (0x0524) 132#define CDC_TX2_TX_PATH_SEC6 (0x0528) 133#define CDC_TX3_TX_PATH_CTL (0x0580) 134#define CDC_TX3_TX_PATH_CFG0 (0x0584) 135#define CDC_TX3_TX_PATH_CFG1 (0x0588) 136#define CDC_TX3_TX_VOL_CTL (0x058C) 137#define CDC_TX3_TX_PATH_SEC0 (0x0590) 138#define CDC_TX3_TX_PATH_SEC1 (0x0594) 139#define CDC_TX3_TX_PATH_SEC2 (0x0598) 140#define CDC_TX3_TX_PATH_SEC3 (0x059C) 141#define CDC_TX3_TX_PATH_SEC4 (0x05A0) 142#define CDC_TX3_TX_PATH_SEC5 (0x05A4) 143#define CDC_TX3_TX_PATH_SEC6 (0x05A8) 144#define CDC_TX4_TX_PATH_CTL (0x0600) 145#define CDC_TX4_TX_PATH_CFG0 (0x0604) 146#define CDC_TX4_TX_PATH_CFG1 (0x0608) 147#define CDC_TX4_TX_VOL_CTL (0x060C) 148#define CDC_TX4_TX_PATH_SEC0 (0x0610) 149#define CDC_TX4_TX_PATH_SEC1 (0x0614) 150#define CDC_TX4_TX_PATH_SEC2 (0x0618) 151#define CDC_TX4_TX_PATH_SEC3 (0x061C) 152#define CDC_TX4_TX_PATH_SEC4 (0x0620) 153#define CDC_TX4_TX_PATH_SEC5 (0x0624) 154#define CDC_TX4_TX_PATH_SEC6 (0x0628) 155#define CDC_TX5_TX_PATH_CTL (0x0680) 156#define CDC_TX5_TX_PATH_CFG0 (0x0684) 157#define CDC_TX5_TX_PATH_CFG1 (0x0688) 158#define CDC_TX5_TX_VOL_CTL (0x068C) 159#define CDC_TX5_TX_PATH_SEC0 (0x0690) 160#define CDC_TX5_TX_PATH_SEC1 (0x0694) 161#define CDC_TX5_TX_PATH_SEC2 (0x0698) 162#define CDC_TX5_TX_PATH_SEC3 (0x069C) 163#define CDC_TX5_TX_PATH_SEC4 (0x06A0) 164#define CDC_TX5_TX_PATH_SEC5 (0x06A4) 165#define CDC_TX5_TX_PATH_SEC6 (0x06A8) 166#define CDC_TX6_TX_PATH_CTL (0x0700) 167#define CDC_TX6_TX_PATH_CFG0 (0x0704) 168#define CDC_TX6_TX_PATH_CFG1 (0x0708) 169#define CDC_TX6_TX_VOL_CTL (0x070C) 170#define CDC_TX6_TX_PATH_SEC0 (0x0710) 171#define CDC_TX6_TX_PATH_SEC1 (0x0714) 172#define CDC_TX6_TX_PATH_SEC2 (0x0718) 173#define CDC_TX6_TX_PATH_SEC3 (0x071C) 174#define CDC_TX6_TX_PATH_SEC4 (0x0720) 175#define CDC_TX6_TX_PATH_SEC5 (0x0724) 176#define CDC_TX6_TX_PATH_SEC6 (0x0728) 177#define CDC_TX7_TX_PATH_CTL (0x0780) 178#define CDC_TX7_TX_PATH_CFG0 (0x0784) 179#define CDC_TX7_TX_PATH_CFG1 (0x0788) 180#define CDC_TX7_TX_VOL_CTL (0x078C) 181#define CDC_TX7_TX_PATH_SEC0 (0x0790) 182#define CDC_TX7_TX_PATH_SEC1 (0x0794) 183#define CDC_TX7_TX_PATH_SEC2 (0x0798) 184#define CDC_TX7_TX_PATH_SEC3 (0x079C) 185#define CDC_TX7_TX_PATH_SEC4 (0x07A0) 186#define CDC_TX7_TX_PATH_SEC5 (0x07A4) 187#define CDC_TX7_TX_PATH_SEC6 (0x07A8) 188#define TX_MAX_OFFSET (0x07A8) 189 190#define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 191 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 192 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 193#define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 194 SNDRV_PCM_FMTBIT_S24_LE |\ 195 SNDRV_PCM_FMTBIT_S24_3LE) 196 197#define CF_MIN_3DB_4HZ 0x0 198#define CF_MIN_3DB_75HZ 0x1 199#define CF_MIN_3DB_150HZ 0x2 200#define TX_ADC_MAX 5 201#define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2) 202#define NUM_DECIMATORS 8 203#define TX_NUM_CLKS_MAX 5 204#define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40 205#define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100 206#define TX_MACRO_DMIC_HPF_DELAY_MS 300 207#define TX_MACRO_AMIC_HPF_DELAY_MS 300 208#define MCLK_FREQ 19200000 209 210enum { 211 TX_MACRO_AIF_INVALID = 0, 212 TX_MACRO_AIF1_CAP, 213 TX_MACRO_AIF2_CAP, 214 TX_MACRO_AIF3_CAP, 215 TX_MACRO_MAX_DAIS 216}; 217 218enum { 219 TX_MACRO_DEC0, 220 TX_MACRO_DEC1, 221 TX_MACRO_DEC2, 222 TX_MACRO_DEC3, 223 TX_MACRO_DEC4, 224 TX_MACRO_DEC5, 225 TX_MACRO_DEC6, 226 TX_MACRO_DEC7, 227 TX_MACRO_DEC_MAX, 228}; 229 230enum { 231 TX_MACRO_CLK_DIV_2, 232 TX_MACRO_CLK_DIV_3, 233 TX_MACRO_CLK_DIV_4, 234 TX_MACRO_CLK_DIV_6, 235 TX_MACRO_CLK_DIV_8, 236 TX_MACRO_CLK_DIV_16, 237}; 238 239enum { 240 MSM_DMIC, 241 SWR_MIC, 242 ANC_FB_TUNE1 243}; 244 245struct tx_mute_work { 246 struct tx_macro *tx; 247 u8 decimator; 248 struct delayed_work dwork; 249}; 250 251struct hpf_work { 252 struct tx_macro *tx; 253 u8 decimator; 254 u8 hpf_cut_off_freq; 255 struct delayed_work dwork; 256}; 257 258struct tx_macro_data { 259 unsigned int flags; 260 unsigned int ver; 261 const struct snd_soc_dapm_widget *extra_widgets; 262 size_t extra_widgets_num; 263 const struct snd_soc_dapm_route *extra_routes; 264 size_t extra_routes_num; 265}; 266 267struct tx_macro { 268 struct device *dev; 269 const struct tx_macro_data *data; 270 struct snd_soc_component *component; 271 struct hpf_work tx_hpf_work[NUM_DECIMATORS]; 272 struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS]; 273 unsigned long active_ch_mask[TX_MACRO_MAX_DAIS]; 274 unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS]; 275 int active_decimator[TX_MACRO_MAX_DAIS]; 276 struct regmap *regmap; 277 struct clk *mclk; 278 struct clk *npl; 279 struct clk *macro; 280 struct clk *dcodec; 281 struct clk *fsgen; 282 struct clk_hw hw; 283 bool dec_active[NUM_DECIMATORS]; 284 int tx_mclk_users; 285 bool bcs_enable; 286 int dec_mode[NUM_DECIMATORS]; 287 struct lpass_macro *pds; 288 bool bcs_clk_en; 289}; 290#define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw) 291 292static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 293 294static struct reg_default tx_defaults[] = { 295 /* TX Macro */ 296 { CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 }, 297 { CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 }, 298 { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 299 { CDC_TX_TOP_CSR_TOP_CFG0, 0x00}, 300 { CDC_TX_TOP_CSR_ANC_CFG, 0x00}, 301 { CDC_TX_TOP_CSR_SWR_CTRL, 0x00}, 302 { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00}, 303 { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00}, 304 { CDC_TX_TOP_CSR_DEBUG_EN, 0x00}, 305 { CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C}, 306 { CDC_TX_TOP_CSR_I2S_CLK, 0x00}, 307 { CDC_TX_TOP_CSR_I2S_RESET, 0x00}, 308 { CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00}, 309 { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00}, 310 { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00}, 311 { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00}, 312 { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00}, 313 { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00}, 314 { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00}, 315 { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00}, 316 { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00}, 317 { CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00}, 318 { CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00}, 319 { CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00}, 320 { CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00}, 321 { CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00}, 322 { CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00}, 323 { CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00}, 324 { CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00}, 325 { CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00}, 326 { CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00}, 327 { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00}, 328 { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00}, 329 { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00}, 330 { CDC_TX_ANC0_CLK_RESET_CTL, 0x00}, 331 { CDC_TX_ANC0_MODE_1_CTL, 0x00}, 332 { CDC_TX_ANC0_MODE_2_CTL, 0x00}, 333 { CDC_TX_ANC0_FF_SHIFT, 0x00}, 334 { CDC_TX_ANC0_FB_SHIFT, 0x00}, 335 { CDC_TX_ANC0_LPF_FF_A_CTL, 0x00}, 336 { CDC_TX_ANC0_LPF_FF_B_CTL, 0x00}, 337 { CDC_TX_ANC0_LPF_FB_CTL, 0x00}, 338 { CDC_TX_ANC0_SMLPF_CTL, 0x00}, 339 { CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00}, 340 { CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00}, 341 { CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00}, 342 { CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00}, 343 { CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00}, 344 { CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00}, 345 { CDC_TX_ANC0_FB_GAIN_CTL, 0x00}, 346 { CDC_TX0_TX_PATH_CTL, 0x04}, 347 { CDC_TX0_TX_PATH_CFG0, 0x10}, 348 { CDC_TX0_TX_PATH_CFG1, 0x0B}, 349 { CDC_TX0_TX_VOL_CTL, 0x00}, 350 { CDC_TX0_TX_PATH_SEC0, 0x00}, 351 { CDC_TX0_TX_PATH_SEC1, 0x00}, 352 { CDC_TX0_TX_PATH_SEC2, 0x01}, 353 { CDC_TX0_TX_PATH_SEC3, 0x3C}, 354 { CDC_TX0_TX_PATH_SEC4, 0x20}, 355 { CDC_TX0_TX_PATH_SEC5, 0x00}, 356 { CDC_TX0_TX_PATH_SEC6, 0x00}, 357 { CDC_TX0_TX_PATH_SEC7, 0x25}, 358 { CDC_TX1_TX_PATH_CTL, 0x04}, 359 { CDC_TX1_TX_PATH_CFG0, 0x10}, 360 { CDC_TX1_TX_PATH_CFG1, 0x0B}, 361 { CDC_TX1_TX_VOL_CTL, 0x00}, 362 { CDC_TX1_TX_PATH_SEC0, 0x00}, 363 { CDC_TX1_TX_PATH_SEC1, 0x00}, 364 { CDC_TX1_TX_PATH_SEC2, 0x01}, 365 { CDC_TX1_TX_PATH_SEC3, 0x3C}, 366 { CDC_TX1_TX_PATH_SEC4, 0x20}, 367 { CDC_TX1_TX_PATH_SEC5, 0x00}, 368 { CDC_TX1_TX_PATH_SEC6, 0x00}, 369 { CDC_TX2_TX_PATH_CTL, 0x04}, 370 { CDC_TX2_TX_PATH_CFG0, 0x10}, 371 { CDC_TX2_TX_PATH_CFG1, 0x0B}, 372 { CDC_TX2_TX_VOL_CTL, 0x00}, 373 { CDC_TX2_TX_PATH_SEC0, 0x00}, 374 { CDC_TX2_TX_PATH_SEC1, 0x00}, 375 { CDC_TX2_TX_PATH_SEC2, 0x01}, 376 { CDC_TX2_TX_PATH_SEC3, 0x3C}, 377 { CDC_TX2_TX_PATH_SEC4, 0x20}, 378 { CDC_TX2_TX_PATH_SEC5, 0x00}, 379 { CDC_TX2_TX_PATH_SEC6, 0x00}, 380 { CDC_TX3_TX_PATH_CTL, 0x04}, 381 { CDC_TX3_TX_PATH_CFG0, 0x10}, 382 { CDC_TX3_TX_PATH_CFG1, 0x0B}, 383 { CDC_TX3_TX_VOL_CTL, 0x00}, 384 { CDC_TX3_TX_PATH_SEC0, 0x00}, 385 { CDC_TX3_TX_PATH_SEC1, 0x00}, 386 { CDC_TX3_TX_PATH_SEC2, 0x01}, 387 { CDC_TX3_TX_PATH_SEC3, 0x3C}, 388 { CDC_TX3_TX_PATH_SEC4, 0x20}, 389 { CDC_TX3_TX_PATH_SEC5, 0x00}, 390 { CDC_TX3_TX_PATH_SEC6, 0x00}, 391 { CDC_TX4_TX_PATH_CTL, 0x04}, 392 { CDC_TX4_TX_PATH_CFG0, 0x10}, 393 { CDC_TX4_TX_PATH_CFG1, 0x0B}, 394 { CDC_TX4_TX_VOL_CTL, 0x00}, 395 { CDC_TX4_TX_PATH_SEC0, 0x00}, 396 { CDC_TX4_TX_PATH_SEC1, 0x00}, 397 { CDC_TX4_TX_PATH_SEC2, 0x01}, 398 { CDC_TX4_TX_PATH_SEC3, 0x3C}, 399 { CDC_TX4_TX_PATH_SEC4, 0x20}, 400 { CDC_TX4_TX_PATH_SEC5, 0x00}, 401 { CDC_TX4_TX_PATH_SEC6, 0x00}, 402 { CDC_TX5_TX_PATH_CTL, 0x04}, 403 { CDC_TX5_TX_PATH_CFG0, 0x10}, 404 { CDC_TX5_TX_PATH_CFG1, 0x0B}, 405 { CDC_TX5_TX_VOL_CTL, 0x00}, 406 { CDC_TX5_TX_PATH_SEC0, 0x00}, 407 { CDC_TX5_TX_PATH_SEC1, 0x00}, 408 { CDC_TX5_TX_PATH_SEC2, 0x01}, 409 { CDC_TX5_TX_PATH_SEC3, 0x3C}, 410 { CDC_TX5_TX_PATH_SEC4, 0x20}, 411 { CDC_TX5_TX_PATH_SEC5, 0x00}, 412 { CDC_TX5_TX_PATH_SEC6, 0x00}, 413 { CDC_TX6_TX_PATH_CTL, 0x04}, 414 { CDC_TX6_TX_PATH_CFG0, 0x10}, 415 { CDC_TX6_TX_PATH_CFG1, 0x0B}, 416 { CDC_TX6_TX_VOL_CTL, 0x00}, 417 { CDC_TX6_TX_PATH_SEC0, 0x00}, 418 { CDC_TX6_TX_PATH_SEC1, 0x00}, 419 { CDC_TX6_TX_PATH_SEC2, 0x01}, 420 { CDC_TX6_TX_PATH_SEC3, 0x3C}, 421 { CDC_TX6_TX_PATH_SEC4, 0x20}, 422 { CDC_TX6_TX_PATH_SEC5, 0x00}, 423 { CDC_TX6_TX_PATH_SEC6, 0x00}, 424 { CDC_TX7_TX_PATH_CTL, 0x04}, 425 { CDC_TX7_TX_PATH_CFG0, 0x10}, 426 { CDC_TX7_TX_PATH_CFG1, 0x0B}, 427 { CDC_TX7_TX_VOL_CTL, 0x00}, 428 { CDC_TX7_TX_PATH_SEC0, 0x00}, 429 { CDC_TX7_TX_PATH_SEC1, 0x00}, 430 { CDC_TX7_TX_PATH_SEC2, 0x01}, 431 { CDC_TX7_TX_PATH_SEC3, 0x3C}, 432 { CDC_TX7_TX_PATH_SEC4, 0x20}, 433 { CDC_TX7_TX_PATH_SEC5, 0x00}, 434 { CDC_TX7_TX_PATH_SEC6, 0x00}, 435}; 436 437static bool tx_is_volatile_register(struct device *dev, unsigned int reg) 438{ 439 /* Update volatile list for tx/tx macros */ 440 switch (reg) { 441 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL: 442 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL: 443 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL: 444 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL: 445 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: 446 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: 447 return true; 448 } 449 return false; 450} 451 452static bool tx_is_rw_register(struct device *dev, unsigned int reg) 453{ 454 switch (reg) { 455 case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL: 456 case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL: 457 case CDC_TX_CLK_RST_CTRL_SWR_CONTROL: 458 case CDC_TX_TOP_CSR_TOP_CFG0: 459 case CDC_TX_TOP_CSR_ANC_CFG: 460 case CDC_TX_TOP_CSR_SWR_CTRL: 461 case CDC_TX_TOP_CSR_FREQ_MCLK: 462 case CDC_TX_TOP_CSR_DEBUG_BUS: 463 case CDC_TX_TOP_CSR_DEBUG_EN: 464 case CDC_TX_TOP_CSR_TX_I2S_CTL: 465 case CDC_TX_TOP_CSR_I2S_CLK: 466 case CDC_TX_TOP_CSR_I2S_RESET: 467 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL: 468 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL: 469 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL: 470 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL: 471 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: 472 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: 473 case CDC_TX_ANC0_CLK_RESET_CTL: 474 case CDC_TX_ANC0_MODE_1_CTL: 475 case CDC_TX_ANC0_MODE_2_CTL: 476 case CDC_TX_ANC0_FF_SHIFT: 477 case CDC_TX_ANC0_FB_SHIFT: 478 case CDC_TX_ANC0_LPF_FF_A_CTL: 479 case CDC_TX_ANC0_LPF_FF_B_CTL: 480 case CDC_TX_ANC0_LPF_FB_CTL: 481 case CDC_TX_ANC0_SMLPF_CTL: 482 case CDC_TX_ANC0_DCFLT_SHIFT_CTL: 483 case CDC_TX_ANC0_IIR_ADAPT_CTL: 484 case CDC_TX_ANC0_IIR_COEFF_1_CTL: 485 case CDC_TX_ANC0_IIR_COEFF_2_CTL: 486 case CDC_TX_ANC0_FF_A_GAIN_CTL: 487 case CDC_TX_ANC0_FF_B_GAIN_CTL: 488 case CDC_TX_ANC0_FB_GAIN_CTL: 489 case CDC_TX_INP_MUX_ADC_MUX0_CFG0: 490 case CDC_TX_INP_MUX_ADC_MUX0_CFG1: 491 case CDC_TX_INP_MUX_ADC_MUX1_CFG0: 492 case CDC_TX_INP_MUX_ADC_MUX1_CFG1: 493 case CDC_TX_INP_MUX_ADC_MUX2_CFG0: 494 case CDC_TX_INP_MUX_ADC_MUX2_CFG1: 495 case CDC_TX_INP_MUX_ADC_MUX3_CFG0: 496 case CDC_TX_INP_MUX_ADC_MUX3_CFG1: 497 case CDC_TX_INP_MUX_ADC_MUX4_CFG0: 498 case CDC_TX_INP_MUX_ADC_MUX4_CFG1: 499 case CDC_TX_INP_MUX_ADC_MUX5_CFG0: 500 case CDC_TX_INP_MUX_ADC_MUX5_CFG1: 501 case CDC_TX_INP_MUX_ADC_MUX6_CFG0: 502 case CDC_TX_INP_MUX_ADC_MUX6_CFG1: 503 case CDC_TX_INP_MUX_ADC_MUX7_CFG0: 504 case CDC_TX_INP_MUX_ADC_MUX7_CFG1: 505 case CDC_TX0_TX_PATH_CTL: 506 case CDC_TX0_TX_PATH_CFG0: 507 case CDC_TX0_TX_PATH_CFG1: 508 case CDC_TX0_TX_VOL_CTL: 509 case CDC_TX0_TX_PATH_SEC0: 510 case CDC_TX0_TX_PATH_SEC1: 511 case CDC_TX0_TX_PATH_SEC2: 512 case CDC_TX0_TX_PATH_SEC3: 513 case CDC_TX0_TX_PATH_SEC4: 514 case CDC_TX0_TX_PATH_SEC5: 515 case CDC_TX0_TX_PATH_SEC6: 516 case CDC_TX0_TX_PATH_SEC7: 517 case CDC_TX1_TX_PATH_CTL: 518 case CDC_TX1_TX_PATH_CFG0: 519 case CDC_TX1_TX_PATH_CFG1: 520 case CDC_TX1_TX_VOL_CTL: 521 case CDC_TX1_TX_PATH_SEC0: 522 case CDC_TX1_TX_PATH_SEC1: 523 case CDC_TX1_TX_PATH_SEC2: 524 case CDC_TX1_TX_PATH_SEC3: 525 case CDC_TX1_TX_PATH_SEC4: 526 case CDC_TX1_TX_PATH_SEC5: 527 case CDC_TX1_TX_PATH_SEC6: 528 case CDC_TX2_TX_PATH_CTL: 529 case CDC_TX2_TX_PATH_CFG0: 530 case CDC_TX2_TX_PATH_CFG1: 531 case CDC_TX2_TX_VOL_CTL: 532 case CDC_TX2_TX_PATH_SEC0: 533 case CDC_TX2_TX_PATH_SEC1: 534 case CDC_TX2_TX_PATH_SEC2: 535 case CDC_TX2_TX_PATH_SEC3: 536 case CDC_TX2_TX_PATH_SEC4: 537 case CDC_TX2_TX_PATH_SEC5: 538 case CDC_TX2_TX_PATH_SEC6: 539 case CDC_TX3_TX_PATH_CTL: 540 case CDC_TX3_TX_PATH_CFG0: 541 case CDC_TX3_TX_PATH_CFG1: 542 case CDC_TX3_TX_VOL_CTL: 543 case CDC_TX3_TX_PATH_SEC0: 544 case CDC_TX3_TX_PATH_SEC1: 545 case CDC_TX3_TX_PATH_SEC2: 546 case CDC_TX3_TX_PATH_SEC3: 547 case CDC_TX3_TX_PATH_SEC4: 548 case CDC_TX3_TX_PATH_SEC5: 549 case CDC_TX3_TX_PATH_SEC6: 550 case CDC_TX4_TX_PATH_CTL: 551 case CDC_TX4_TX_PATH_CFG0: 552 case CDC_TX4_TX_PATH_CFG1: 553 case CDC_TX4_TX_VOL_CTL: 554 case CDC_TX4_TX_PATH_SEC0: 555 case CDC_TX4_TX_PATH_SEC1: 556 case CDC_TX4_TX_PATH_SEC2: 557 case CDC_TX4_TX_PATH_SEC3: 558 case CDC_TX4_TX_PATH_SEC4: 559 case CDC_TX4_TX_PATH_SEC5: 560 case CDC_TX4_TX_PATH_SEC6: 561 case CDC_TX5_TX_PATH_CTL: 562 case CDC_TX5_TX_PATH_CFG0: 563 case CDC_TX5_TX_PATH_CFG1: 564 case CDC_TX5_TX_VOL_CTL: 565 case CDC_TX5_TX_PATH_SEC0: 566 case CDC_TX5_TX_PATH_SEC1: 567 case CDC_TX5_TX_PATH_SEC2: 568 case CDC_TX5_TX_PATH_SEC3: 569 case CDC_TX5_TX_PATH_SEC4: 570 case CDC_TX5_TX_PATH_SEC5: 571 case CDC_TX5_TX_PATH_SEC6: 572 case CDC_TX6_TX_PATH_CTL: 573 case CDC_TX6_TX_PATH_CFG0: 574 case CDC_TX6_TX_PATH_CFG1: 575 case CDC_TX6_TX_VOL_CTL: 576 case CDC_TX6_TX_PATH_SEC0: 577 case CDC_TX6_TX_PATH_SEC1: 578 case CDC_TX6_TX_PATH_SEC2: 579 case CDC_TX6_TX_PATH_SEC3: 580 case CDC_TX6_TX_PATH_SEC4: 581 case CDC_TX6_TX_PATH_SEC5: 582 case CDC_TX6_TX_PATH_SEC6: 583 case CDC_TX7_TX_PATH_CTL: 584 case CDC_TX7_TX_PATH_CFG0: 585 case CDC_TX7_TX_PATH_CFG1: 586 case CDC_TX7_TX_VOL_CTL: 587 case CDC_TX7_TX_PATH_SEC0: 588 case CDC_TX7_TX_PATH_SEC1: 589 case CDC_TX7_TX_PATH_SEC2: 590 case CDC_TX7_TX_PATH_SEC3: 591 case CDC_TX7_TX_PATH_SEC4: 592 case CDC_TX7_TX_PATH_SEC5: 593 case CDC_TX7_TX_PATH_SEC6: 594 return true; 595 } 596 597 return false; 598} 599 600static const struct regmap_config tx_regmap_config = { 601 .name = "tx_macro", 602 .reg_bits = 16, 603 .val_bits = 32, 604 .reg_stride = 4, 605 .cache_type = REGCACHE_FLAT, 606 .max_register = TX_MAX_OFFSET, 607 .reg_defaults = tx_defaults, 608 .num_reg_defaults = ARRAY_SIZE(tx_defaults), 609 .writeable_reg = tx_is_rw_register, 610 .volatile_reg = tx_is_volatile_register, 611 .readable_reg = tx_is_rw_register, 612}; 613 614static int tx_macro_mclk_enable(struct tx_macro *tx, 615 bool mclk_enable) 616{ 617 struct regmap *regmap = tx->regmap; 618 619 if (mclk_enable) { 620 if (tx->tx_mclk_users == 0) { 621 /* 9.6MHz MCLK, set value 0x00 if other frequency */ 622 regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01); 623 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 624 CDC_TX_MCLK_EN_MASK, 625 CDC_TX_MCLK_ENABLE); 626 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 627 CDC_TX_FS_CNT_EN_MASK, 628 CDC_TX_FS_CNT_ENABLE); 629 regcache_mark_dirty(regmap); 630 regcache_sync(regmap); 631 } 632 tx->tx_mclk_users++; 633 } else { 634 if (tx->tx_mclk_users <= 0) { 635 dev_err(tx->dev, "clock already disabled\n"); 636 tx->tx_mclk_users = 0; 637 goto exit; 638 } 639 tx->tx_mclk_users--; 640 if (tx->tx_mclk_users == 0) { 641 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 642 CDC_TX_FS_CNT_EN_MASK, 0x0); 643 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 644 CDC_TX_MCLK_EN_MASK, 0x0); 645 } 646 } 647exit: 648 return 0; 649} 650 651static bool is_amic_enabled(struct snd_soc_component *component, 652 struct tx_macro *tx, u8 decimator) 653{ 654 u16 adc_mux_reg, adc_reg, adc_n; 655 656 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator); 657 658 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { 659 if (tx->data->ver > LPASS_VER_9_0_0) 660 return true; 661 662 /* else: LPASS <= v9.0.0 */ 663 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator); 664 adc_n = snd_soc_component_read_field(component, adc_reg, 665 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK); 666 if (adc_n < TX_ADC_MAX) 667 return true; 668 } 669 670 return false; 671} 672 673static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 674{ 675 struct delayed_work *hpf_delayed_work; 676 struct hpf_work *hpf_work; 677 struct tx_macro *tx; 678 struct snd_soc_component *component; 679 u16 dec_cfg_reg, hpf_gate_reg; 680 u8 hpf_cut_off_freq; 681 682 hpf_delayed_work = to_delayed_work(work); 683 hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); 684 tx = hpf_work->tx; 685 component = tx->component; 686 hpf_cut_off_freq = hpf_work->hpf_cut_off_freq; 687 688 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator); 689 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator); 690 691 if (is_amic_enabled(component, tx, hpf_work->decimator)) { 692 snd_soc_component_write_field(component, 693 dec_cfg_reg, 694 CDC_TXn_HPF_CUT_FREQ_MASK, 695 hpf_cut_off_freq); 696 snd_soc_component_update_bits(component, hpf_gate_reg, 697 CDC_TXn_HPF_F_CHANGE_MASK | 698 CDC_TXn_HPF_ZERO_GATE_MASK, 699 0x02); 700 snd_soc_component_update_bits(component, hpf_gate_reg, 701 CDC_TXn_HPF_F_CHANGE_MASK | 702 CDC_TXn_HPF_ZERO_GATE_MASK, 703 0x01); 704 } else { 705 snd_soc_component_write_field(component, dec_cfg_reg, 706 CDC_TXn_HPF_CUT_FREQ_MASK, 707 hpf_cut_off_freq); 708 snd_soc_component_write_field(component, hpf_gate_reg, 709 CDC_TXn_HPF_F_CHANGE_MASK, 0x1); 710 /* Minimum 1 clk cycle delay is required as per HW spec */ 711 usleep_range(1000, 1010); 712 snd_soc_component_write_field(component, hpf_gate_reg, 713 CDC_TXn_HPF_F_CHANGE_MASK, 0x0); 714 } 715} 716 717static void tx_macro_mute_update_callback(struct work_struct *work) 718{ 719 struct tx_mute_work *tx_mute_dwork; 720 struct snd_soc_component *component; 721 struct tx_macro *tx; 722 struct delayed_work *delayed_work; 723 u8 decimator; 724 725 delayed_work = to_delayed_work(work); 726 tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork); 727 tx = tx_mute_dwork->tx; 728 component = tx->component; 729 decimator = tx_mute_dwork->decimator; 730 731 snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator), 732 CDC_TXn_PGA_MUTE_MASK, 0x0); 733} 734 735static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w, 736 struct snd_kcontrol *kcontrol, int event) 737{ 738 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 739 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 740 741 switch (event) { 742 case SND_SOC_DAPM_PRE_PMU: 743 tx_macro_mclk_enable(tx, true); 744 break; 745 case SND_SOC_DAPM_POST_PMD: 746 tx_macro_mclk_enable(tx, false); 747 break; 748 default: 749 break; 750 } 751 752 return 0; 753} 754 755static void tx_macro_update_smic_sel_v9(struct snd_soc_component *component, 756 struct snd_soc_dapm_widget *widget, 757 struct tx_macro *tx, u16 mic_sel_reg, 758 unsigned int val) 759{ 760 unsigned int dmic; 761 u16 dmic_clk_reg; 762 763 if (val < 5) { 764 snd_soc_component_write_field(component, mic_sel_reg, 765 CDC_TXn_ADC_DMIC_SEL_MASK, 0); 766 } else { 767 snd_soc_component_write_field(component, mic_sel_reg, 768 CDC_TXn_ADC_DMIC_SEL_MASK, 1); 769 dmic = TX_ADC_TO_DMIC(val); 770 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); 771 snd_soc_component_write_field(component, dmic_clk_reg, 772 CDC_TX_SWR_DMIC_CLK_SEL_MASK, 773 CDC_TX_SWR_MIC_CLK_DEFAULT); 774 } 775} 776 777static void tx_macro_update_smic_sel_v9_2(struct snd_soc_component *component, 778 struct snd_soc_dapm_widget *widget, 779 struct tx_macro *tx, u16 mic_sel_reg, 780 unsigned int val) 781{ 782 unsigned int dmic; 783 u16 dmic_clk_reg; 784 785 if (widget->shift) { 786 /* MSM DMIC */ 787 snd_soc_component_write_field(component, mic_sel_reg, 788 CDC_TXn_ADC_DMIC_SEL_MASK, 1); 789 790 dmic = TX_ADC_TO_DMIC(val); 791 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); 792 snd_soc_component_write_field(component, dmic_clk_reg, 793 CDC_TX_SWR_DMIC_CLK_SEL_MASK, 794 CDC_TX_SWR_MIC_CLK_DEFAULT); 795 } else { 796 snd_soc_component_write_field(component, mic_sel_reg, 797 CDC_TXn_ADC_DMIC_SEL_MASK, 0); 798 } 799} 800 801static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, 802 struct snd_ctl_elem_value *ucontrol) 803{ 804 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 805 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 806 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 807 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 808 unsigned int val; 809 u16 mic_sel_reg; 810 811 val = ucontrol->value.enumerated.item[0]; 812 if (val >= e->items) 813 return -EINVAL; 814 815 switch (e->reg) { 816 case CDC_TX_INP_MUX_ADC_MUX0_CFG0: 817 mic_sel_reg = CDC_TX0_TX_PATH_CFG0; 818 break; 819 case CDC_TX_INP_MUX_ADC_MUX1_CFG0: 820 mic_sel_reg = CDC_TX1_TX_PATH_CFG0; 821 break; 822 case CDC_TX_INP_MUX_ADC_MUX2_CFG0: 823 mic_sel_reg = CDC_TX2_TX_PATH_CFG0; 824 break; 825 case CDC_TX_INP_MUX_ADC_MUX3_CFG0: 826 mic_sel_reg = CDC_TX3_TX_PATH_CFG0; 827 break; 828 case CDC_TX_INP_MUX_ADC_MUX4_CFG0: 829 mic_sel_reg = CDC_TX4_TX_PATH_CFG0; 830 break; 831 case CDC_TX_INP_MUX_ADC_MUX5_CFG0: 832 mic_sel_reg = CDC_TX5_TX_PATH_CFG0; 833 break; 834 case CDC_TX_INP_MUX_ADC_MUX6_CFG0: 835 mic_sel_reg = CDC_TX6_TX_PATH_CFG0; 836 break; 837 case CDC_TX_INP_MUX_ADC_MUX7_CFG0: 838 mic_sel_reg = CDC_TX7_TX_PATH_CFG0; 839 break; 840 default: 841 dev_err(component->dev, "Error in configuration!!\n"); 842 return -EINVAL; 843 } 844 845 if (val != 0) { 846 if (widget->shift) /* MSM DMIC */ 847 snd_soc_component_write_field(component, mic_sel_reg, 848 CDC_TXn_ADC_DMIC_SEL_MASK, 1); 849 else if (tx->data->ver <= LPASS_VER_9_0_0) 850 tx_macro_update_smic_sel_v9(component, widget, tx, 851 mic_sel_reg, val); 852 else 853 tx_macro_update_smic_sel_v9_2(component, widget, tx, 854 mic_sel_reg, val); 855 } 856 857 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 858} 859 860static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol, 861 struct snd_ctl_elem_value *ucontrol) 862{ 863 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 864 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 865 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; 866 u32 dai_id = widget->shift; 867 u32 dec_id = mc->shift; 868 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 869 870 if (test_bit(dec_id, &tx->active_ch_mask[dai_id])) 871 ucontrol->value.integer.value[0] = 1; 872 else 873 ucontrol->value.integer.value[0] = 0; 874 875 return 0; 876} 877 878static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, 879 struct snd_ctl_elem_value *ucontrol) 880{ 881 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 882 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 883 struct snd_soc_dapm_update *update = NULL; 884 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; 885 u32 dai_id = widget->shift; 886 u32 dec_id = mc->shift; 887 u32 enable = ucontrol->value.integer.value[0]; 888 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 889 890 if (enable) { 891 if (tx->active_decimator[dai_id] == dec_id) 892 return 0; 893 894 set_bit(dec_id, &tx->active_ch_mask[dai_id]); 895 tx->active_ch_cnt[dai_id]++; 896 tx->active_decimator[dai_id] = dec_id; 897 } else { 898 if (tx->active_decimator[dai_id] == -1) 899 return 0; 900 901 tx->active_ch_cnt[dai_id]--; 902 clear_bit(dec_id, &tx->active_ch_mask[dai_id]); 903 tx->active_decimator[dai_id] = -1; 904 } 905 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); 906 907 return 1; 908} 909 910static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 911 struct snd_kcontrol *kcontrol, int event) 912{ 913 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 914 u8 decimator; 915 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg; 916 u8 hpf_cut_off_freq; 917 int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS; 918 int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS; 919 u16 adc_mux_reg, adc_reg, adc_n, dmic; 920 u16 dmic_clk_reg; 921 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 922 923 decimator = w->shift; 924 tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator); 925 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator); 926 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator); 927 tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator); 928 929 switch (event) { 930 case SND_SOC_DAPM_PRE_PMU: 931 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator); 932 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { 933 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator); 934 adc_n = snd_soc_component_read(component, adc_reg) & 935 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK; 936 if (adc_n >= TX_ADC_MAX) { 937 dmic = TX_ADC_TO_DMIC(adc_n); 938 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); 939 940 snd_soc_component_write_field(component, dmic_clk_reg, 941 CDC_TX_SWR_DMIC_CLK_SEL_MASK, 942 CDC_TX_SWR_MIC_CLK_DEFAULT); 943 } 944 } 945 snd_soc_component_write_field(component, dec_cfg_reg, 946 CDC_TXn_ADC_MODE_MASK, 947 tx->dec_mode[decimator]); 948 /* Enable TX PGA Mute */ 949 snd_soc_component_write_field(component, tx_vol_ctl_reg, 950 CDC_TXn_PGA_MUTE_MASK, 0x1); 951 break; 952 case SND_SOC_DAPM_POST_PMU: 953 snd_soc_component_write_field(component, tx_vol_ctl_reg, 954 CDC_TXn_CLK_EN_MASK, 0x1); 955 if (!is_amic_enabled(component, tx, decimator)) { 956 snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00); 957 /* Minimum 1 clk cycle delay is required as per HW spec */ 958 usleep_range(1000, 1010); 959 } 960 hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg, 961 CDC_TXn_HPF_CUT_FREQ_MASK); 962 963 tx->tx_hpf_work[decimator].hpf_cut_off_freq = 964 hpf_cut_off_freq; 965 966 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) 967 snd_soc_component_write_field(component, dec_cfg_reg, 968 CDC_TXn_HPF_CUT_FREQ_MASK, 969 CF_MIN_3DB_150HZ); 970 971 if (is_amic_enabled(component, tx, decimator)) { 972 hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS; 973 unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS; 974 } 975 /* schedule work queue to Remove Mute */ 976 queue_delayed_work(system_freezable_wq, 977 &tx->tx_mute_dwork[decimator].dwork, 978 msecs_to_jiffies(unmute_delay)); 979 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 980 queue_delayed_work(system_freezable_wq, 981 &tx->tx_hpf_work[decimator].dwork, 982 msecs_to_jiffies(hpf_delay)); 983 snd_soc_component_update_bits(component, hpf_gate_reg, 984 CDC_TXn_HPF_F_CHANGE_MASK | 985 CDC_TXn_HPF_ZERO_GATE_MASK, 986 0x02); 987 if (!is_amic_enabled(component, tx, decimator)) 988 snd_soc_component_update_bits(component, hpf_gate_reg, 989 CDC_TXn_HPF_F_CHANGE_MASK | 990 CDC_TXn_HPF_ZERO_GATE_MASK, 991 0x00); 992 snd_soc_component_update_bits(component, hpf_gate_reg, 993 CDC_TXn_HPF_F_CHANGE_MASK | 994 CDC_TXn_HPF_ZERO_GATE_MASK, 995 0x01); 996 997 /* 998 * 6ms delay is required as per HW spec 999 */ 1000 usleep_range(6000, 6010); 1001 } 1002 /* apply gain after decimator is enabled */ 1003 snd_soc_component_write(component, tx_gain_ctl_reg, 1004 snd_soc_component_read(component, 1005 tx_gain_ctl_reg)); 1006 if (tx->bcs_enable) { 1007 snd_soc_component_update_bits(component, dec_cfg_reg, 1008 0x01, 0x01); 1009 tx->bcs_clk_en = true; 1010 } 1011 break; 1012 case SND_SOC_DAPM_PRE_PMD: 1013 hpf_cut_off_freq = 1014 tx->tx_hpf_work[decimator].hpf_cut_off_freq; 1015 snd_soc_component_write_field(component, tx_vol_ctl_reg, 1016 CDC_TXn_PGA_MUTE_MASK, 0x1); 1017 if (cancel_delayed_work_sync( 1018 &tx->tx_hpf_work[decimator].dwork)) { 1019 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 1020 snd_soc_component_write_field( 1021 component, dec_cfg_reg, 1022 CDC_TXn_HPF_CUT_FREQ_MASK, 1023 hpf_cut_off_freq); 1024 if (is_amic_enabled(component, tx, decimator)) 1025 snd_soc_component_update_bits(component, 1026 hpf_gate_reg, 1027 CDC_TXn_HPF_F_CHANGE_MASK | 1028 CDC_TXn_HPF_ZERO_GATE_MASK, 1029 0x02); 1030 else 1031 snd_soc_component_update_bits(component, 1032 hpf_gate_reg, 1033 CDC_TXn_HPF_F_CHANGE_MASK | 1034 CDC_TXn_HPF_ZERO_GATE_MASK, 1035 0x03); 1036 1037 /* 1038 * Minimum 1 clk cycle delay is required 1039 * as per HW spec 1040 */ 1041 usleep_range(1000, 1010); 1042 snd_soc_component_update_bits(component, hpf_gate_reg, 1043 CDC_TXn_HPF_F_CHANGE_MASK | 1044 CDC_TXn_HPF_ZERO_GATE_MASK, 1045 0x1); 1046 } 1047 } 1048 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork); 1049 break; 1050 case SND_SOC_DAPM_POST_PMD: 1051 snd_soc_component_write_field(component, tx_vol_ctl_reg, 1052 CDC_TXn_CLK_EN_MASK, 0x0); 1053 snd_soc_component_write_field(component, dec_cfg_reg, 1054 CDC_TXn_ADC_MODE_MASK, 0x0); 1055 snd_soc_component_write_field(component, tx_vol_ctl_reg, 1056 CDC_TXn_PGA_MUTE_MASK, 0x0); 1057 if (tx->bcs_enable) { 1058 snd_soc_component_write_field(component, dec_cfg_reg, 1059 CDC_TXn_PH_EN_MASK, 0x0); 1060 snd_soc_component_write_field(component, 1061 CDC_TX0_TX_PATH_SEC7, 1062 CDC_TX0_MBHC_CTL_EN_MASK, 1063 0x0); 1064 tx->bcs_clk_en = false; 1065 } 1066 break; 1067 } 1068 return 0; 1069} 1070 1071static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol, 1072 struct snd_ctl_elem_value *ucontrol) 1073{ 1074 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1075 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1076 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1077 int path = e->shift_l; 1078 1079 ucontrol->value.integer.value[0] = tx->dec_mode[path]; 1080 1081 return 0; 1082} 1083 1084static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol, 1085 struct snd_ctl_elem_value *ucontrol) 1086{ 1087 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1088 int value = ucontrol->value.integer.value[0]; 1089 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1090 int path = e->shift_l; 1091 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1092 1093 if (tx->dec_mode[path] == value) 1094 return 0; 1095 1096 tx->dec_mode[path] = value; 1097 1098 return 1; 1099} 1100 1101static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol, 1102 struct snd_ctl_elem_value *ucontrol) 1103{ 1104 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1105 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1106 1107 ucontrol->value.integer.value[0] = tx->bcs_enable; 1108 1109 return 0; 1110} 1111 1112static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol, 1113 struct snd_ctl_elem_value *ucontrol) 1114{ 1115 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1116 int value = ucontrol->value.integer.value[0]; 1117 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1118 1119 tx->bcs_enable = value; 1120 1121 return 0; 1122} 1123 1124static int tx_macro_hw_params(struct snd_pcm_substream *substream, 1125 struct snd_pcm_hw_params *params, 1126 struct snd_soc_dai *dai) 1127{ 1128 struct snd_soc_component *component = dai->component; 1129 u32 sample_rate; 1130 u8 decimator; 1131 int tx_fs_rate; 1132 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1133 1134 sample_rate = params_rate(params); 1135 switch (sample_rate) { 1136 case 8000: 1137 tx_fs_rate = 0; 1138 break; 1139 case 16000: 1140 tx_fs_rate = 1; 1141 break; 1142 case 32000: 1143 tx_fs_rate = 3; 1144 break; 1145 case 48000: 1146 tx_fs_rate = 4; 1147 break; 1148 case 96000: 1149 tx_fs_rate = 5; 1150 break; 1151 case 192000: 1152 tx_fs_rate = 6; 1153 break; 1154 case 384000: 1155 tx_fs_rate = 7; 1156 break; 1157 default: 1158 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n", 1159 __func__, params_rate(params)); 1160 return -EINVAL; 1161 } 1162 1163 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX) 1164 snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator), 1165 CDC_TXn_PCM_RATE_MASK, 1166 tx_fs_rate); 1167 return 0; 1168} 1169 1170static int tx_macro_get_channel_map(struct snd_soc_dai *dai, 1171 unsigned int *tx_num, unsigned int *tx_slot, 1172 unsigned int *rx_num, unsigned int *rx_slot) 1173{ 1174 struct snd_soc_component *component = dai->component; 1175 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1176 1177 switch (dai->id) { 1178 case TX_MACRO_AIF1_CAP: 1179 case TX_MACRO_AIF2_CAP: 1180 case TX_MACRO_AIF3_CAP: 1181 *tx_slot = tx->active_ch_mask[dai->id]; 1182 *tx_num = tx->active_ch_cnt[dai->id]; 1183 break; 1184 default: 1185 break; 1186 } 1187 return 0; 1188} 1189 1190static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 1191{ 1192 struct snd_soc_component *component = dai->component; 1193 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1194 u8 decimator; 1195 1196 /* active decimator not set yet */ 1197 if (tx->active_decimator[dai->id] == -1) 1198 return 0; 1199 1200 decimator = tx->active_decimator[dai->id]; 1201 1202 if (mute) 1203 snd_soc_component_write_field(component, 1204 CDC_TXn_TX_PATH_CTL(decimator), 1205 CDC_TXn_PGA_MUTE_MASK, 0x1); 1206 else 1207 snd_soc_component_update_bits(component, 1208 CDC_TXn_TX_PATH_CTL(decimator), 1209 CDC_TXn_PGA_MUTE_MASK, 0x0); 1210 1211 return 0; 1212} 1213 1214static const struct snd_soc_dai_ops tx_macro_dai_ops = { 1215 .hw_params = tx_macro_hw_params, 1216 .get_channel_map = tx_macro_get_channel_map, 1217 .mute_stream = tx_macro_digital_mute, 1218}; 1219 1220static struct snd_soc_dai_driver tx_macro_dai[] = { 1221 { 1222 .name = "tx_macro_tx1", 1223 .id = TX_MACRO_AIF1_CAP, 1224 .capture = { 1225 .stream_name = "TX_AIF1 Capture", 1226 .rates = TX_MACRO_RATES, 1227 .formats = TX_MACRO_FORMATS, 1228 .rate_max = 192000, 1229 .rate_min = 8000, 1230 .channels_min = 1, 1231 .channels_max = 8, 1232 }, 1233 .ops = &tx_macro_dai_ops, 1234 }, 1235 { 1236 .name = "tx_macro_tx2", 1237 .id = TX_MACRO_AIF2_CAP, 1238 .capture = { 1239 .stream_name = "TX_AIF2 Capture", 1240 .rates = TX_MACRO_RATES, 1241 .formats = TX_MACRO_FORMATS, 1242 .rate_max = 192000, 1243 .rate_min = 8000, 1244 .channels_min = 1, 1245 .channels_max = 8, 1246 }, 1247 .ops = &tx_macro_dai_ops, 1248 }, 1249 { 1250 .name = "tx_macro_tx3", 1251 .id = TX_MACRO_AIF3_CAP, 1252 .capture = { 1253 .stream_name = "TX_AIF3 Capture", 1254 .rates = TX_MACRO_RATES, 1255 .formats = TX_MACRO_FORMATS, 1256 .rate_max = 192000, 1257 .rate_min = 8000, 1258 .channels_min = 1, 1259 .channels_max = 8, 1260 }, 1261 .ops = &tx_macro_dai_ops, 1262 }, 1263}; 1264 1265static const char * const adc_mux_text[] = { 1266 "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1" 1267}; 1268 1269static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1, 1270 0, adc_mux_text); 1271static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1, 1272 0, adc_mux_text); 1273static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1, 1274 0, adc_mux_text); 1275static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1, 1276 0, adc_mux_text); 1277static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1, 1278 0, adc_mux_text); 1279static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1, 1280 0, adc_mux_text); 1281static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1, 1282 0, adc_mux_text); 1283static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1, 1284 0, adc_mux_text); 1285 1286static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum); 1287static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum); 1288static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum); 1289static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum); 1290static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum); 1291static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum); 1292static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum); 1293static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum); 1294 1295static const char * const dmic_mux_text[] = { 1296 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", 1297 "DMIC4", "DMIC5", "DMIC6", "DMIC7" 1298}; 1299 1300static SOC_ENUM_SINGLE_DECL(tx_dmic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0, 1301 4, dmic_mux_text); 1302 1303static SOC_ENUM_SINGLE_DECL(tx_dmic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0, 1304 4, dmic_mux_text); 1305 1306static SOC_ENUM_SINGLE_DECL(tx_dmic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0, 1307 4, dmic_mux_text); 1308 1309static SOC_ENUM_SINGLE_DECL(tx_dmic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0, 1310 4, dmic_mux_text); 1311 1312static SOC_ENUM_SINGLE_DECL(tx_dmic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0, 1313 4, dmic_mux_text); 1314 1315static SOC_ENUM_SINGLE_DECL(tx_dmic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0, 1316 4, dmic_mux_text); 1317 1318static SOC_ENUM_SINGLE_DECL(tx_dmic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0, 1319 4, dmic_mux_text); 1320 1321static SOC_ENUM_SINGLE_DECL(tx_dmic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0, 1322 4, dmic_mux_text); 1323 1324static const struct snd_kcontrol_new tx_dmic0_mux = SOC_DAPM_ENUM_EXT("tx_dmic0", tx_dmic0_enum, 1325 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1326static const struct snd_kcontrol_new tx_dmic1_mux = SOC_DAPM_ENUM_EXT("tx_dmic1", tx_dmic1_enum, 1327 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1328static const struct snd_kcontrol_new tx_dmic2_mux = SOC_DAPM_ENUM_EXT("tx_dmic2", tx_dmic2_enum, 1329 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1330static const struct snd_kcontrol_new tx_dmic3_mux = SOC_DAPM_ENUM_EXT("tx_dmic3", tx_dmic3_enum, 1331 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1332static const struct snd_kcontrol_new tx_dmic4_mux = SOC_DAPM_ENUM_EXT("tx_dmic4", tx_dmic4_enum, 1333 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1334static const struct snd_kcontrol_new tx_dmic5_mux = SOC_DAPM_ENUM_EXT("tx_dmic5", tx_dmic5_enum, 1335 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1336static const struct snd_kcontrol_new tx_dmic6_mux = SOC_DAPM_ENUM_EXT("tx_dmic6", tx_dmic6_enum, 1337 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1338static const struct snd_kcontrol_new tx_dmic7_mux = SOC_DAPM_ENUM_EXT("tx_dmic7", tx_dmic7_enum, 1339 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1340 1341static const char * const dec_mode_mux_text[] = { 1342 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF", 1343}; 1344 1345static const struct soc_enum dec_mode_mux_enum[] = { 1346 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text), 1347 dec_mode_mux_text), 1348 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text), 1349 dec_mode_mux_text), 1350 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text), 1351 dec_mode_mux_text), 1352 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text), 1353 dec_mode_mux_text), 1354 SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text), 1355 dec_mode_mux_text), 1356 SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text), 1357 dec_mode_mux_text), 1358 SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text), 1359 dec_mode_mux_text), 1360 SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text), 1361 dec_mode_mux_text), 1362}; 1363 1364static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = { 1365 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1366 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1367 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1368 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1369 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1370 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1371 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1372 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1373 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1374 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1375 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1376 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1377 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1378 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1379 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1380 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1381}; 1382 1383static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = { 1384 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1385 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1386 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1387 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1388 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1389 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1390 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1391 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1392 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1393 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1394 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1395 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1396 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1397 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1398 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1399 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1400}; 1401 1402static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = { 1403 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1404 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1405 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1406 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1407 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1408 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1409 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1410 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1411 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1412 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1413 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1414 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1415 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1416 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1417 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1418 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1419}; 1420 1421static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = { 1422 SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0, 1423 SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0), 1424 1425 SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0, 1426 SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0), 1427 1428 SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0, 1429 SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0), 1430 1431 SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0, 1432 tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)), 1433 1434 SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0, 1435 tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)), 1436 1437 SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0, 1438 tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)), 1439 1440 SND_SOC_DAPM_MUX("TX DMIC MUX0", SND_SOC_NOPM, 4, 0, &tx_dmic0_mux), 1441 SND_SOC_DAPM_MUX("TX DMIC MUX1", SND_SOC_NOPM, 4, 0, &tx_dmic1_mux), 1442 SND_SOC_DAPM_MUX("TX DMIC MUX2", SND_SOC_NOPM, 4, 0, &tx_dmic2_mux), 1443 SND_SOC_DAPM_MUX("TX DMIC MUX3", SND_SOC_NOPM, 4, 0, &tx_dmic3_mux), 1444 SND_SOC_DAPM_MUX("TX DMIC MUX4", SND_SOC_NOPM, 4, 0, &tx_dmic4_mux), 1445 SND_SOC_DAPM_MUX("TX DMIC MUX5", SND_SOC_NOPM, 4, 0, &tx_dmic5_mux), 1446 SND_SOC_DAPM_MUX("TX DMIC MUX6", SND_SOC_NOPM, 4, 0, &tx_dmic6_mux), 1447 SND_SOC_DAPM_MUX("TX DMIC MUX7", SND_SOC_NOPM, 4, 0, &tx_dmic7_mux), 1448 1449 SND_SOC_DAPM_INPUT("TX DMIC0"), 1450 SND_SOC_DAPM_INPUT("TX DMIC1"), 1451 SND_SOC_DAPM_INPUT("TX DMIC2"), 1452 SND_SOC_DAPM_INPUT("TX DMIC3"), 1453 SND_SOC_DAPM_INPUT("TX DMIC4"), 1454 SND_SOC_DAPM_INPUT("TX DMIC5"), 1455 SND_SOC_DAPM_INPUT("TX DMIC6"), 1456 SND_SOC_DAPM_INPUT("TX DMIC7"), 1457 1458 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, 1459 TX_MACRO_DEC0, 0, 1460 &tx_dec0_mux, tx_macro_enable_dec, 1461 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1462 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1463 1464 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM, 1465 TX_MACRO_DEC1, 0, 1466 &tx_dec1_mux, tx_macro_enable_dec, 1467 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1468 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1469 1470 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM, 1471 TX_MACRO_DEC2, 0, 1472 &tx_dec2_mux, tx_macro_enable_dec, 1473 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1474 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1475 1476 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM, 1477 TX_MACRO_DEC3, 0, 1478 &tx_dec3_mux, tx_macro_enable_dec, 1479 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1480 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1481 1482 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM, 1483 TX_MACRO_DEC4, 0, 1484 &tx_dec4_mux, tx_macro_enable_dec, 1485 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1486 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1487 1488 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM, 1489 TX_MACRO_DEC5, 0, 1490 &tx_dec5_mux, tx_macro_enable_dec, 1491 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1492 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1493 1494 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM, 1495 TX_MACRO_DEC6, 0, 1496 &tx_dec6_mux, tx_macro_enable_dec, 1497 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1498 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1499 1500 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM, 1501 TX_MACRO_DEC7, 0, 1502 &tx_dec7_mux, tx_macro_enable_dec, 1503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1504 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1505 1506 SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, 1507 tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1508 1509 SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0), 1510 1511 SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, 1512 NULL, 0), 1513}; 1514 1515static const struct snd_soc_dapm_route tx_audio_map[] = { 1516 {"TX_AIF1 CAP", NULL, "TX_MCLK"}, 1517 {"TX_AIF2 CAP", NULL, "TX_MCLK"}, 1518 {"TX_AIF3 CAP", NULL, "TX_MCLK"}, 1519 1520 {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"}, 1521 {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"}, 1522 {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"}, 1523 1524 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1525 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1526 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1527 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1528 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1529 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1530 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1531 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1532 1533 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1534 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1535 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1536 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1537 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1538 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1539 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1540 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1541 1542 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1543 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1544 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1545 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1546 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1547 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1548 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1549 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1550 1551 {"TX DEC0 MUX", NULL, "TX_MCLK"}, 1552 {"TX DEC1 MUX", NULL, "TX_MCLK"}, 1553 {"TX DEC2 MUX", NULL, "TX_MCLK"}, 1554 {"TX DEC3 MUX", NULL, "TX_MCLK"}, 1555 {"TX DEC4 MUX", NULL, "TX_MCLK"}, 1556 {"TX DEC5 MUX", NULL, "TX_MCLK"}, 1557 {"TX DEC6 MUX", NULL, "TX_MCLK"}, 1558 {"TX DEC7 MUX", NULL, "TX_MCLK"}, 1559 1560 {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"}, 1561 {"TX DMIC MUX0", "DMIC0", "TX DMIC0"}, 1562 {"TX DMIC MUX0", "DMIC1", "TX DMIC1"}, 1563 {"TX DMIC MUX0", "DMIC2", "TX DMIC2"}, 1564 {"TX DMIC MUX0", "DMIC3", "TX DMIC3"}, 1565 {"TX DMIC MUX0", "DMIC4", "TX DMIC4"}, 1566 {"TX DMIC MUX0", "DMIC5", "TX DMIC5"}, 1567 {"TX DMIC MUX0", "DMIC6", "TX DMIC6"}, 1568 {"TX DMIC MUX0", "DMIC7", "TX DMIC7"}, 1569 1570 {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"}, 1571 {"TX DMIC MUX1", "DMIC0", "TX DMIC0"}, 1572 {"TX DMIC MUX1", "DMIC1", "TX DMIC1"}, 1573 {"TX DMIC MUX1", "DMIC2", "TX DMIC2"}, 1574 {"TX DMIC MUX1", "DMIC3", "TX DMIC3"}, 1575 {"TX DMIC MUX1", "DMIC4", "TX DMIC4"}, 1576 {"TX DMIC MUX1", "DMIC5", "TX DMIC5"}, 1577 {"TX DMIC MUX1", "DMIC6", "TX DMIC6"}, 1578 {"TX DMIC MUX1", "DMIC7", "TX DMIC7"}, 1579 1580 {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"}, 1581 {"TX DMIC MUX2", "DMIC0", "TX DMIC0"}, 1582 {"TX DMIC MUX2", "DMIC1", "TX DMIC1"}, 1583 {"TX DMIC MUX2", "DMIC2", "TX DMIC2"}, 1584 {"TX DMIC MUX2", "DMIC3", "TX DMIC3"}, 1585 {"TX DMIC MUX2", "DMIC4", "TX DMIC4"}, 1586 {"TX DMIC MUX2", "DMIC5", "TX DMIC5"}, 1587 {"TX DMIC MUX2", "DMIC6", "TX DMIC6"}, 1588 {"TX DMIC MUX2", "DMIC7", "TX DMIC7"}, 1589 1590 {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"}, 1591 {"TX DMIC MUX3", "DMIC0", "TX DMIC0"}, 1592 {"TX DMIC MUX3", "DMIC1", "TX DMIC1"}, 1593 {"TX DMIC MUX3", "DMIC2", "TX DMIC2"}, 1594 {"TX DMIC MUX3", "DMIC3", "TX DMIC3"}, 1595 {"TX DMIC MUX3", "DMIC4", "TX DMIC4"}, 1596 {"TX DMIC MUX3", "DMIC5", "TX DMIC5"}, 1597 {"TX DMIC MUX3", "DMIC6", "TX DMIC6"}, 1598 {"TX DMIC MUX3", "DMIC7", "TX DMIC7"}, 1599 1600 {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"}, 1601 {"TX DMIC MUX4", "DMIC0", "TX DMIC0"}, 1602 {"TX DMIC MUX4", "DMIC1", "TX DMIC1"}, 1603 {"TX DMIC MUX4", "DMIC2", "TX DMIC2"}, 1604 {"TX DMIC MUX4", "DMIC3", "TX DMIC3"}, 1605 {"TX DMIC MUX4", "DMIC4", "TX DMIC4"}, 1606 {"TX DMIC MUX4", "DMIC5", "TX DMIC5"}, 1607 {"TX DMIC MUX4", "DMIC6", "TX DMIC6"}, 1608 {"TX DMIC MUX4", "DMIC7", "TX DMIC7"}, 1609 1610 {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"}, 1611 {"TX DMIC MUX5", "DMIC0", "TX DMIC0"}, 1612 {"TX DMIC MUX5", "DMIC1", "TX DMIC1"}, 1613 {"TX DMIC MUX5", "DMIC2", "TX DMIC2"}, 1614 {"TX DMIC MUX5", "DMIC3", "TX DMIC3"}, 1615 {"TX DMIC MUX5", "DMIC4", "TX DMIC4"}, 1616 {"TX DMIC MUX5", "DMIC5", "TX DMIC5"}, 1617 {"TX DMIC MUX5", "DMIC6", "TX DMIC6"}, 1618 {"TX DMIC MUX5", "DMIC7", "TX DMIC7"}, 1619 1620 {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"}, 1621 {"TX DMIC MUX6", "DMIC0", "TX DMIC0"}, 1622 {"TX DMIC MUX6", "DMIC1", "TX DMIC1"}, 1623 {"TX DMIC MUX6", "DMIC2", "TX DMIC2"}, 1624 {"TX DMIC MUX6", "DMIC3", "TX DMIC3"}, 1625 {"TX DMIC MUX6", "DMIC4", "TX DMIC4"}, 1626 {"TX DMIC MUX6", "DMIC5", "TX DMIC5"}, 1627 {"TX DMIC MUX6", "DMIC6", "TX DMIC6"}, 1628 {"TX DMIC MUX6", "DMIC7", "TX DMIC7"}, 1629 1630 {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"}, 1631 {"TX DMIC MUX7", "DMIC0", "TX DMIC0"}, 1632 {"TX DMIC MUX7", "DMIC1", "TX DMIC1"}, 1633 {"TX DMIC MUX7", "DMIC2", "TX DMIC2"}, 1634 {"TX DMIC MUX7", "DMIC3", "TX DMIC3"}, 1635 {"TX DMIC MUX7", "DMIC4", "TX DMIC4"}, 1636 {"TX DMIC MUX7", "DMIC5", "TX DMIC5"}, 1637 {"TX DMIC MUX7", "DMIC6", "TX DMIC6"}, 1638 {"TX DMIC MUX7", "DMIC7", "TX DMIC7"}, 1639}; 1640 1641/* Controls and routes specific to LPASS <= v9.0.0 */ 1642static const char * const smic_mux_text_v9[] = { 1643 "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0", 1644 "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4", 1645 "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7" 1646}; 1647 1648static SOC_ENUM_SINGLE_DECL(tx_smic0_enum_v9, CDC_TX_INP_MUX_ADC_MUX0_CFG0, 1649 0, smic_mux_text_v9); 1650 1651static SOC_ENUM_SINGLE_DECL(tx_smic1_enum_v9, CDC_TX_INP_MUX_ADC_MUX1_CFG0, 1652 0, smic_mux_text_v9); 1653 1654static SOC_ENUM_SINGLE_DECL(tx_smic2_enum_v9, CDC_TX_INP_MUX_ADC_MUX2_CFG0, 1655 0, smic_mux_text_v9); 1656 1657static SOC_ENUM_SINGLE_DECL(tx_smic3_enum_v9, CDC_TX_INP_MUX_ADC_MUX3_CFG0, 1658 0, smic_mux_text_v9); 1659 1660static SOC_ENUM_SINGLE_DECL(tx_smic4_enum_v9, CDC_TX_INP_MUX_ADC_MUX4_CFG0, 1661 0, smic_mux_text_v9); 1662 1663static SOC_ENUM_SINGLE_DECL(tx_smic5_enum_v9, CDC_TX_INP_MUX_ADC_MUX5_CFG0, 1664 0, smic_mux_text_v9); 1665 1666static SOC_ENUM_SINGLE_DECL(tx_smic6_enum_v9, CDC_TX_INP_MUX_ADC_MUX6_CFG0, 1667 0, smic_mux_text_v9); 1668 1669static SOC_ENUM_SINGLE_DECL(tx_smic7_enum_v9, CDC_TX_INP_MUX_ADC_MUX7_CFG0, 1670 0, smic_mux_text_v9); 1671 1672static const struct snd_kcontrol_new tx_smic0_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum_v9, 1673 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1674static const struct snd_kcontrol_new tx_smic1_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum_v9, 1675 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1676static const struct snd_kcontrol_new tx_smic2_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum_v9, 1677 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1678static const struct snd_kcontrol_new tx_smic3_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum_v9, 1679 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1680static const struct snd_kcontrol_new tx_smic4_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum_v9, 1681 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1682static const struct snd_kcontrol_new tx_smic5_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum_v9, 1683 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1684static const struct snd_kcontrol_new tx_smic6_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum_v9, 1685 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1686static const struct snd_kcontrol_new tx_smic7_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum_v9, 1687 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1688 1689static const struct snd_soc_dapm_widget tx_macro_dapm_widgets_v9[] = { 1690 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9), 1691 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9), 1692 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9), 1693 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9), 1694 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9), 1695 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9), 1696 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9), 1697 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9), 1698 1699 SND_SOC_DAPM_INPUT("TX SWR_ADC0"), 1700 SND_SOC_DAPM_INPUT("TX SWR_ADC1"), 1701 SND_SOC_DAPM_INPUT("TX SWR_ADC2"), 1702 SND_SOC_DAPM_INPUT("TX SWR_ADC3"), 1703 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"), 1704 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"), 1705 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"), 1706 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"), 1707 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"), 1708 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"), 1709 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"), 1710 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"), 1711}; 1712 1713static const struct snd_soc_dapm_route tx_audio_map_v9[] = { 1714 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, 1715 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, 1716 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"}, 1717 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"}, 1718 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"}, 1719 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"}, 1720 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"}, 1721 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"}, 1722 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"}, 1723 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"}, 1724 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"}, 1725 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"}, 1726 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"}, 1727 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"}, 1728 1729 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, 1730 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, 1731 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"}, 1732 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"}, 1733 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"}, 1734 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"}, 1735 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"}, 1736 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"}, 1737 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"}, 1738 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"}, 1739 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"}, 1740 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"}, 1741 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"}, 1742 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"}, 1743 1744 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, 1745 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, 1746 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"}, 1747 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"}, 1748 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"}, 1749 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"}, 1750 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"}, 1751 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"}, 1752 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"}, 1753 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"}, 1754 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"}, 1755 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"}, 1756 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"}, 1757 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"}, 1758 1759 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, 1760 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, 1761 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"}, 1762 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"}, 1763 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"}, 1764 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"}, 1765 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"}, 1766 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"}, 1767 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"}, 1768 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"}, 1769 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"}, 1770 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"}, 1771 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"}, 1772 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"}, 1773 1774 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, 1775 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, 1776 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"}, 1777 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"}, 1778 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"}, 1779 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"}, 1780 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"}, 1781 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"}, 1782 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"}, 1783 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"}, 1784 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"}, 1785 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"}, 1786 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"}, 1787 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"}, 1788 1789 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, 1790 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, 1791 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"}, 1792 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"}, 1793 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"}, 1794 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"}, 1795 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"}, 1796 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"}, 1797 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"}, 1798 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"}, 1799 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"}, 1800 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"}, 1801 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"}, 1802 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"}, 1803 1804 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, 1805 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, 1806 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"}, 1807 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"}, 1808 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"}, 1809 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"}, 1810 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"}, 1811 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"}, 1812 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"}, 1813 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"}, 1814 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"}, 1815 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"}, 1816 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"}, 1817 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"}, 1818 1819 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, 1820 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, 1821 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"}, 1822 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"}, 1823 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"}, 1824 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"}, 1825 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"}, 1826 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"}, 1827 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"}, 1828 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"}, 1829 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"}, 1830 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"}, 1831 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"}, 1832 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"}, 1833}; 1834 1835/* Controls and routes specific to LPASS >= v9.2.0 */ 1836static const char * const smic_mux_text_v9_2[] = { 1837 "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3", 1838 "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7", 1839 "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11" 1840}; 1841 1842static SOC_ENUM_SINGLE_DECL(tx_smic0_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX0_CFG0, 1843 0, smic_mux_text_v9_2); 1844 1845static SOC_ENUM_SINGLE_DECL(tx_smic1_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX1_CFG0, 1846 0, smic_mux_text_v9_2); 1847 1848static SOC_ENUM_SINGLE_DECL(tx_smic2_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX2_CFG0, 1849 0, smic_mux_text_v9_2); 1850 1851static SOC_ENUM_SINGLE_DECL(tx_smic3_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX3_CFG0, 1852 0, smic_mux_text_v9_2); 1853 1854static SOC_ENUM_SINGLE_DECL(tx_smic4_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX4_CFG0, 1855 0, smic_mux_text_v9_2); 1856 1857static SOC_ENUM_SINGLE_DECL(tx_smic5_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX5_CFG0, 1858 0, smic_mux_text_v9_2); 1859 1860static SOC_ENUM_SINGLE_DECL(tx_smic6_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX6_CFG0, 1861 0, smic_mux_text_v9_2); 1862 1863static SOC_ENUM_SINGLE_DECL(tx_smic7_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX7_CFG0, 1864 0, smic_mux_text_v9_2); 1865 1866static const struct snd_kcontrol_new tx_smic0_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum_v9_2, 1867 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1868static const struct snd_kcontrol_new tx_smic1_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum_v9_2, 1869 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1870static const struct snd_kcontrol_new tx_smic2_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum_v9_2, 1871 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1872static const struct snd_kcontrol_new tx_smic3_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum_v9_2, 1873 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1874static const struct snd_kcontrol_new tx_smic4_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum_v9_2, 1875 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1876static const struct snd_kcontrol_new tx_smic5_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum_v9_2, 1877 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1878static const struct snd_kcontrol_new tx_smic6_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum_v9_2, 1879 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1880static const struct snd_kcontrol_new tx_smic7_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum_v9_2, 1881 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1882 1883static const struct snd_soc_dapm_widget tx_macro_dapm_widgets_v9_2[] = { 1884 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9_2), 1885 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9_2), 1886 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9_2), 1887 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9_2), 1888 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9_2), 1889 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9_2), 1890 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9_2), 1891 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9_2), 1892 1893 SND_SOC_DAPM_INPUT("TX SWR_INPUT0"), 1894 SND_SOC_DAPM_INPUT("TX SWR_INPUT1"), 1895 SND_SOC_DAPM_INPUT("TX SWR_INPUT2"), 1896 SND_SOC_DAPM_INPUT("TX SWR_INPUT3"), 1897 SND_SOC_DAPM_INPUT("TX SWR_INPUT4"), 1898 SND_SOC_DAPM_INPUT("TX SWR_INPUT5"), 1899 SND_SOC_DAPM_INPUT("TX SWR_INPUT6"), 1900 SND_SOC_DAPM_INPUT("TX SWR_INPUT7"), 1901 SND_SOC_DAPM_INPUT("TX SWR_INPUT8"), 1902 SND_SOC_DAPM_INPUT("TX SWR_INPUT9"), 1903 SND_SOC_DAPM_INPUT("TX SWR_INPUT10"), 1904 SND_SOC_DAPM_INPUT("TX SWR_INPUT11"), 1905}; 1906 1907static const struct snd_soc_dapm_route tx_audio_map_v9_2[] = { 1908 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, 1909 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, 1910 {"TX SMIC MUX0", "SWR_MIC0", "TX SWR_INPUT0"}, 1911 {"TX SMIC MUX0", "SWR_MIC1", "TX SWR_INPUT1"}, 1912 {"TX SMIC MUX0", "SWR_MIC2", "TX SWR_INPUT2"}, 1913 {"TX SMIC MUX0", "SWR_MIC3", "TX SWR_INPUT3"}, 1914 {"TX SMIC MUX0", "SWR_MIC4", "TX SWR_INPUT4"}, 1915 {"TX SMIC MUX0", "SWR_MIC5", "TX SWR_INPUT5"}, 1916 {"TX SMIC MUX0", "SWR_MIC6", "TX SWR_INPUT6"}, 1917 {"TX SMIC MUX0", "SWR_MIC7", "TX SWR_INPUT7"}, 1918 {"TX SMIC MUX0", "SWR_MIC8", "TX SWR_INPUT8"}, 1919 {"TX SMIC MUX0", "SWR_MIC9", "TX SWR_INPUT9"}, 1920 {"TX SMIC MUX0", "SWR_MIC10", "TX SWR_INPUT11"}, 1921 {"TX SMIC MUX0", "SWR_MIC11", "TX SWR_INPUT10"}, 1922 1923 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, 1924 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, 1925 {"TX SMIC MUX1", "SWR_MIC0", "TX SWR_INPUT0"}, 1926 {"TX SMIC MUX1", "SWR_MIC1", "TX SWR_INPUT1"}, 1927 {"TX SMIC MUX1", "SWR_MIC2", "TX SWR_INPUT2"}, 1928 {"TX SMIC MUX1", "SWR_MIC3", "TX SWR_INPUT3"}, 1929 {"TX SMIC MUX1", "SWR_MIC4", "TX SWR_INPUT4"}, 1930 {"TX SMIC MUX1", "SWR_MIC5", "TX SWR_INPUT5"}, 1931 {"TX SMIC MUX1", "SWR_MIC6", "TX SWR_INPUT6"}, 1932 {"TX SMIC MUX1", "SWR_MIC7", "TX SWR_INPUT7"}, 1933 {"TX SMIC MUX1", "SWR_MIC8", "TX SWR_INPUT8"}, 1934 {"TX SMIC MUX1", "SWR_MIC9", "TX SWR_INPUT9"}, 1935 {"TX SMIC MUX1", "SWR_MIC10", "TX SWR_INPUT10"}, 1936 {"TX SMIC MUX1", "SWR_MIC11", "TX SWR_INPUT11"}, 1937 1938 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, 1939 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, 1940 {"TX SMIC MUX2", "SWR_MIC0", "TX SWR_INPUT0"}, 1941 {"TX SMIC MUX2", "SWR_MIC1", "TX SWR_INPUT1"}, 1942 {"TX SMIC MUX2", "SWR_MIC2", "TX SWR_INPUT2"}, 1943 {"TX SMIC MUX2", "SWR_MIC3", "TX SWR_INPUT3"}, 1944 {"TX SMIC MUX2", "SWR_MIC4", "TX SWR_INPUT4"}, 1945 {"TX SMIC MUX2", "SWR_MIC5", "TX SWR_INPUT5"}, 1946 {"TX SMIC MUX2", "SWR_MIC6", "TX SWR_INPUT6"}, 1947 {"TX SMIC MUX2", "SWR_MIC7", "TX SWR_INPUT7"}, 1948 {"TX SMIC MUX2", "SWR_MIC8", "TX SWR_INPUT8"}, 1949 {"TX SMIC MUX2", "SWR_MIC9", "TX SWR_INPUT9"}, 1950 {"TX SMIC MUX2", "SWR_MIC10", "TX SWR_INPUT10"}, 1951 {"TX SMIC MUX2", "SWR_MIC11", "TX SWR_INPUT11"}, 1952 1953 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, 1954 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, 1955 {"TX SMIC MUX3", "SWR_MIC0", "TX SWR_INPUT0"}, 1956 {"TX SMIC MUX3", "SWR_MIC1", "TX SWR_INPUT1"}, 1957 {"TX SMIC MUX3", "SWR_MIC2", "TX SWR_INPUT2"}, 1958 {"TX SMIC MUX3", "SWR_MIC3", "TX SWR_INPUT3"}, 1959 {"TX SMIC MUX3", "SWR_MIC4", "TX SWR_INPUT4"}, 1960 {"TX SMIC MUX3", "SWR_MIC5", "TX SWR_INPUT5"}, 1961 {"TX SMIC MUX3", "SWR_MIC6", "TX SWR_INPUT6"}, 1962 {"TX SMIC MUX3", "SWR_MIC7", "TX SWR_INPUT7"}, 1963 {"TX SMIC MUX3", "SWR_MIC8", "TX SWR_INPUT8"}, 1964 {"TX SMIC MUX3", "SWR_MIC9", "TX SWR_INPUT9"}, 1965 {"TX SMIC MUX3", "SWR_MIC10", "TX SWR_INPUT10"}, 1966 {"TX SMIC MUX3", "SWR_MIC11", "TX SWR_INPUT11"}, 1967 1968 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, 1969 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, 1970 {"TX SMIC MUX4", "SWR_MIC0", "TX SWR_INPUT0"}, 1971 {"TX SMIC MUX4", "SWR_MIC1", "TX SWR_INPUT1"}, 1972 {"TX SMIC MUX4", "SWR_MIC2", "TX SWR_INPUT2"}, 1973 {"TX SMIC MUX4", "SWR_MIC3", "TX SWR_INPUT3"}, 1974 {"TX SMIC MUX4", "SWR_MIC4", "TX SWR_INPUT4"}, 1975 {"TX SMIC MUX4", "SWR_MIC5", "TX SWR_INPUT5"}, 1976 {"TX SMIC MUX4", "SWR_MIC6", "TX SWR_INPUT6"}, 1977 {"TX SMIC MUX4", "SWR_MIC7", "TX SWR_INPUT7"}, 1978 {"TX SMIC MUX4", "SWR_MIC8", "TX SWR_INPUT8"}, 1979 {"TX SMIC MUX4", "SWR_MIC9", "TX SWR_INPUT9"}, 1980 {"TX SMIC MUX4", "SWR_MIC10", "TX SWR_INPUT10"}, 1981 {"TX SMIC MUX4", "SWR_MIC11", "TX SWR_INPUT11"}, 1982 1983 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, 1984 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, 1985 {"TX SMIC MUX5", "SWR_MIC0", "TX SWR_INPUT0"}, 1986 {"TX SMIC MUX5", "SWR_MIC1", "TX SWR_INPUT1"}, 1987 {"TX SMIC MUX5", "SWR_MIC2", "TX SWR_INPUT2"}, 1988 {"TX SMIC MUX5", "SWR_MIC3", "TX SWR_INPUT3"}, 1989 {"TX SMIC MUX5", "SWR_MIC4", "TX SWR_INPUT4"}, 1990 {"TX SMIC MUX5", "SWR_MIC5", "TX SWR_INPUT5"}, 1991 {"TX SMIC MUX5", "SWR_MIC6", "TX SWR_INPUT6"}, 1992 {"TX SMIC MUX5", "SWR_MIC7", "TX SWR_INPUT7"}, 1993 {"TX SMIC MUX5", "SWR_MIC8", "TX SWR_INPUT8"}, 1994 {"TX SMIC MUX5", "SWR_MIC9", "TX SWR_INPUT9"}, 1995 {"TX SMIC MUX5", "SWR_MIC10", "TX SWR_INPUT10"}, 1996 {"TX SMIC MUX5", "SWR_MIC11", "TX SWR_INPUT11"}, 1997 1998 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, 1999 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, 2000 {"TX SMIC MUX6", "SWR_MIC0", "TX SWR_INPUT0"}, 2001 {"TX SMIC MUX6", "SWR_MIC1", "TX SWR_INPUT1"}, 2002 {"TX SMIC MUX6", "SWR_MIC2", "TX SWR_INPUT2"}, 2003 {"TX SMIC MUX6", "SWR_MIC3", "TX SWR_INPUT3"}, 2004 {"TX SMIC MUX6", "SWR_MIC4", "TX SWR_INPUT4"}, 2005 {"TX SMIC MUX6", "SWR_MIC5", "TX SWR_INPUT5"}, 2006 {"TX SMIC MUX6", "SWR_MIC6", "TX SWR_INPUT6"}, 2007 {"TX SMIC MUX6", "SWR_MIC7", "TX SWR_INPUT7"}, 2008 {"TX SMIC MUX6", "SWR_MIC8", "TX SWR_INPUT8"}, 2009 {"TX SMIC MUX6", "SWR_MIC9", "TX SWR_INPUT9"}, 2010 {"TX SMIC MUX6", "SWR_MIC10", "TX SWR_INPUT10"}, 2011 {"TX SMIC MUX6", "SWR_MIC11", "TX SWR_INPUT11"}, 2012 2013 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, 2014 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, 2015 {"TX SMIC MUX7", "SWR_MIC0", "TX SWR_INPUT0"}, 2016 {"TX SMIC MUX7", "SWR_MIC1", "TX SWR_INPUT1"}, 2017 {"TX SMIC MUX7", "SWR_MIC2", "TX SWR_INPUT2"}, 2018 {"TX SMIC MUX7", "SWR_MIC3", "TX SWR_INPUT3"}, 2019 {"TX SMIC MUX7", "SWR_MIC4", "TX SWR_INPUT4"}, 2020 {"TX SMIC MUX7", "SWR_MIC5", "TX SWR_INPUT5"}, 2021 {"TX SMIC MUX7", "SWR_MIC6", "TX SWR_INPUT6"}, 2022 {"TX SMIC MUX7", "SWR_MIC7", "TX SWR_INPUT7"}, 2023 {"TX SMIC MUX7", "SWR_MIC8", "TX SWR_INPUT8"}, 2024 {"TX SMIC MUX7", "SWR_MIC9", "TX SWR_INPUT9"}, 2025 {"TX SMIC MUX7", "SWR_MIC10", "TX SWR_INPUT10"}, 2026 {"TX SMIC MUX7", "SWR_MIC11", "TX SWR_INPUT11"}, 2027}; 2028 2029static const struct snd_kcontrol_new tx_macro_snd_controls[] = { 2030 SOC_SINGLE_S8_TLV("TX_DEC0 Volume", 2031 CDC_TX0_TX_VOL_CTL, 2032 -84, 40, digital_gain), 2033 SOC_SINGLE_S8_TLV("TX_DEC1 Volume", 2034 CDC_TX1_TX_VOL_CTL, 2035 -84, 40, digital_gain), 2036 SOC_SINGLE_S8_TLV("TX_DEC2 Volume", 2037 CDC_TX2_TX_VOL_CTL, 2038 -84, 40, digital_gain), 2039 SOC_SINGLE_S8_TLV("TX_DEC3 Volume", 2040 CDC_TX3_TX_VOL_CTL, 2041 -84, 40, digital_gain), 2042 SOC_SINGLE_S8_TLV("TX_DEC4 Volume", 2043 CDC_TX4_TX_VOL_CTL, 2044 -84, 40, digital_gain), 2045 SOC_SINGLE_S8_TLV("TX_DEC5 Volume", 2046 CDC_TX5_TX_VOL_CTL, 2047 -84, 40, digital_gain), 2048 SOC_SINGLE_S8_TLV("TX_DEC6 Volume", 2049 CDC_TX6_TX_VOL_CTL, 2050 -84, 40, digital_gain), 2051 SOC_SINGLE_S8_TLV("TX_DEC7 Volume", 2052 CDC_TX7_TX_VOL_CTL, 2053 -84, 40, digital_gain), 2054 2055 SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0], 2056 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2057 2058 SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1], 2059 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2060 2061 SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2], 2062 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2063 2064 SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3], 2065 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2066 2067 SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4], 2068 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2069 2070 SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5], 2071 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2072 2073 SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6], 2074 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2075 2076 SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7], 2077 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 2078 2079 SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0, 2080 tx_macro_get_bcs, tx_macro_set_bcs), 2081}; 2082 2083static int tx_macro_component_extend(struct snd_soc_component *comp) 2084{ 2085 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(comp); 2086 struct tx_macro *tx = snd_soc_component_get_drvdata(comp); 2087 int ret; 2088 2089 if (tx->data->extra_widgets_num) { 2090 ret = snd_soc_dapm_new_controls(dapm, tx->data->extra_widgets, 2091 tx->data->extra_widgets_num); 2092 if (ret) { 2093 dev_err(tx->dev, "failed to add extra widgets: %d\n", ret); 2094 return ret; 2095 } 2096 } 2097 2098 if (tx->data->extra_routes_num) { 2099 ret = snd_soc_dapm_add_routes(dapm, tx->data->extra_routes, 2100 tx->data->extra_routes_num); 2101 if (ret) { 2102 dev_err(tx->dev, "failed to add extra routes: %d\n", ret); 2103 return ret; 2104 } 2105 } 2106 2107 return 0; 2108} 2109 2110static int tx_macro_component_probe(struct snd_soc_component *comp) 2111{ 2112 struct tx_macro *tx = snd_soc_component_get_drvdata(comp); 2113 int i, ret; 2114 2115 ret = tx_macro_component_extend(comp); 2116 if (ret) 2117 return ret; 2118 2119 snd_soc_component_init_regmap(comp, tx->regmap); 2120 2121 for (i = 0; i < NUM_DECIMATORS; i++) { 2122 tx->tx_hpf_work[i].tx = tx; 2123 tx->tx_hpf_work[i].decimator = i; 2124 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork, 2125 tx_macro_tx_hpf_corner_freq_callback); 2126 } 2127 2128 for (i = 0; i < NUM_DECIMATORS; i++) { 2129 tx->tx_mute_dwork[i].tx = tx; 2130 tx->tx_mute_dwork[i].decimator = i; 2131 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork, 2132 tx_macro_mute_update_callback); 2133 } 2134 tx->component = comp; 2135 2136 snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F, 2137 0x0A); 2138 /* Enable swr mic0 and mic1 clock */ 2139 snd_soc_component_write(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 2140 CDC_TX_SWR_MIC_CLK_DEFAULT); 2141 snd_soc_component_write(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 2142 CDC_TX_SWR_MIC_CLK_DEFAULT); 2143 2144 return 0; 2145} 2146 2147static int swclk_gate_enable(struct clk_hw *hw) 2148{ 2149 struct tx_macro *tx = to_tx_macro(hw); 2150 struct regmap *regmap = tx->regmap; 2151 int ret; 2152 2153 ret = clk_prepare_enable(tx->mclk); 2154 if (ret) { 2155 dev_err(tx->dev, "failed to enable mclk\n"); 2156 return ret; 2157 } 2158 2159 tx_macro_mclk_enable(tx, true); 2160 2161 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 2162 CDC_TX_SWR_CLK_EN_MASK, 2163 CDC_TX_SWR_CLK_ENABLE); 2164 return 0; 2165} 2166 2167static void swclk_gate_disable(struct clk_hw *hw) 2168{ 2169 struct tx_macro *tx = to_tx_macro(hw); 2170 struct regmap *regmap = tx->regmap; 2171 2172 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 2173 CDC_TX_SWR_CLK_EN_MASK, 0x0); 2174 2175 tx_macro_mclk_enable(tx, false); 2176 clk_disable_unprepare(tx->mclk); 2177} 2178 2179static int swclk_gate_is_enabled(struct clk_hw *hw) 2180{ 2181 struct tx_macro *tx = to_tx_macro(hw); 2182 int ret, val; 2183 2184 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val); 2185 ret = val & BIT(0); 2186 2187 return ret; 2188} 2189 2190static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2191 unsigned long parent_rate) 2192{ 2193 return parent_rate / 2; 2194} 2195 2196static const struct clk_ops swclk_gate_ops = { 2197 .prepare = swclk_gate_enable, 2198 .unprepare = swclk_gate_disable, 2199 .is_enabled = swclk_gate_is_enabled, 2200 .recalc_rate = swclk_recalc_rate, 2201 2202}; 2203 2204static int tx_macro_register_mclk_output(struct tx_macro *tx) 2205{ 2206 struct device *dev = tx->dev; 2207 const char *parent_clk_name = NULL; 2208 const char *clk_name = "lpass-tx-mclk"; 2209 struct clk_hw *hw; 2210 struct clk_init_data init; 2211 int ret; 2212 2213 if (tx->npl) 2214 parent_clk_name = __clk_get_name(tx->npl); 2215 else 2216 parent_clk_name = __clk_get_name(tx->mclk); 2217 2218 init.name = clk_name; 2219 init.ops = &swclk_gate_ops; 2220 init.flags = 0; 2221 init.parent_names = &parent_clk_name; 2222 init.num_parents = 1; 2223 tx->hw.init = &init; 2224 hw = &tx->hw; 2225 ret = devm_clk_hw_register(dev, hw); 2226 if (ret) 2227 return ret; 2228 2229 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 2230} 2231 2232static const struct snd_soc_component_driver tx_macro_component_drv = { 2233 .name = "RX-MACRO", 2234 .probe = tx_macro_component_probe, 2235 .controls = tx_macro_snd_controls, 2236 .num_controls = ARRAY_SIZE(tx_macro_snd_controls), 2237 .dapm_widgets = tx_macro_dapm_widgets, 2238 .num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets), 2239 .dapm_routes = tx_audio_map, 2240 .num_dapm_routes = ARRAY_SIZE(tx_audio_map), 2241}; 2242 2243static int tx_macro_probe(struct platform_device *pdev) 2244{ 2245 struct device *dev = &pdev->dev; 2246 struct device_node *np = dev->of_node; 2247 struct tx_macro *tx; 2248 void __iomem *base; 2249 int ret, reg; 2250 2251 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL); 2252 if (!tx) 2253 return -ENOMEM; 2254 2255 tx->data = device_get_match_data(dev); 2256 2257 tx->macro = devm_clk_get_optional(dev, "macro"); 2258 if (IS_ERR(tx->macro)) 2259 return dev_err_probe(dev, PTR_ERR(tx->macro), "unable to get macro clock\n"); 2260 2261 tx->dcodec = devm_clk_get_optional(dev, "dcodec"); 2262 if (IS_ERR(tx->dcodec)) 2263 return dev_err_probe(dev, PTR_ERR(tx->dcodec), "unable to get dcodec clock\n"); 2264 2265 tx->mclk = devm_clk_get(dev, "mclk"); 2266 if (IS_ERR(tx->mclk)) 2267 return dev_err_probe(dev, PTR_ERR(tx->mclk), "unable to get mclk clock\n"); 2268 2269 if (tx->data->flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) { 2270 tx->npl = devm_clk_get(dev, "npl"); 2271 if (IS_ERR(tx->npl)) 2272 return dev_err_probe(dev, PTR_ERR(tx->npl), "unable to get npl clock\n"); 2273 } 2274 2275 tx->fsgen = devm_clk_get(dev, "fsgen"); 2276 if (IS_ERR(tx->fsgen)) 2277 return dev_err_probe(dev, PTR_ERR(tx->fsgen), "unable to get fsgen clock\n"); 2278 2279 tx->pds = lpass_macro_pds_init(dev); 2280 if (IS_ERR(tx->pds)) 2281 return PTR_ERR(tx->pds); 2282 2283 base = devm_platform_ioremap_resource(pdev, 0); 2284 if (IS_ERR(base)) { 2285 ret = PTR_ERR(base); 2286 goto err; 2287 } 2288 2289 /* Update defaults for lpass sc7280 */ 2290 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) { 2291 for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) { 2292 switch (tx_defaults[reg].reg) { 2293 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: 2294 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: 2295 tx_defaults[reg].def = 0x0E; 2296 break; 2297 default: 2298 break; 2299 } 2300 } 2301 } 2302 2303 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config); 2304 if (IS_ERR(tx->regmap)) { 2305 ret = PTR_ERR(tx->regmap); 2306 goto err; 2307 } 2308 2309 dev_set_drvdata(dev, tx); 2310 2311 tx->dev = dev; 2312 2313 /* Set active_decimator default value */ 2314 tx->active_decimator[TX_MACRO_AIF1_CAP] = -1; 2315 tx->active_decimator[TX_MACRO_AIF2_CAP] = -1; 2316 tx->active_decimator[TX_MACRO_AIF3_CAP] = -1; 2317 2318 /* set MCLK and NPL rates */ 2319 clk_set_rate(tx->mclk, MCLK_FREQ); 2320 clk_set_rate(tx->npl, MCLK_FREQ); 2321 2322 ret = clk_prepare_enable(tx->macro); 2323 if (ret) 2324 goto err; 2325 2326 ret = clk_prepare_enable(tx->dcodec); 2327 if (ret) 2328 goto err_dcodec; 2329 2330 ret = clk_prepare_enable(tx->mclk); 2331 if (ret) 2332 goto err_mclk; 2333 2334 ret = clk_prepare_enable(tx->npl); 2335 if (ret) 2336 goto err_npl; 2337 2338 ret = clk_prepare_enable(tx->fsgen); 2339 if (ret) 2340 goto err_fsgen; 2341 2342 2343 /* reset soundwire block */ 2344 if (tx->data->flags & LPASS_MACRO_FLAG_RESET_SWR) 2345 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 2346 CDC_TX_SWR_RESET_MASK, CDC_TX_SWR_RESET_ENABLE); 2347 2348 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 2349 CDC_TX_SWR_CLK_EN_MASK, 2350 CDC_TX_SWR_CLK_ENABLE); 2351 2352 if (tx->data->flags & LPASS_MACRO_FLAG_RESET_SWR) 2353 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 2354 CDC_TX_SWR_RESET_MASK, 0x0); 2355 2356 ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv, 2357 tx_macro_dai, 2358 ARRAY_SIZE(tx_macro_dai)); 2359 if (ret) 2360 goto err_clkout; 2361 2362 pm_runtime_set_autosuspend_delay(dev, 3000); 2363 pm_runtime_use_autosuspend(dev); 2364 pm_runtime_mark_last_busy(dev); 2365 pm_runtime_set_active(dev); 2366 pm_runtime_enable(dev); 2367 2368 ret = tx_macro_register_mclk_output(tx); 2369 if (ret) 2370 goto err_clkout; 2371 2372 return 0; 2373 2374err_clkout: 2375 clk_disable_unprepare(tx->fsgen); 2376err_fsgen: 2377 clk_disable_unprepare(tx->npl); 2378err_npl: 2379 clk_disable_unprepare(tx->mclk); 2380err_mclk: 2381 clk_disable_unprepare(tx->dcodec); 2382err_dcodec: 2383 clk_disable_unprepare(tx->macro); 2384err: 2385 lpass_macro_pds_exit(tx->pds); 2386 2387 return ret; 2388} 2389 2390static void tx_macro_remove(struct platform_device *pdev) 2391{ 2392 struct tx_macro *tx = dev_get_drvdata(&pdev->dev); 2393 2394 clk_disable_unprepare(tx->macro); 2395 clk_disable_unprepare(tx->dcodec); 2396 clk_disable_unprepare(tx->mclk); 2397 clk_disable_unprepare(tx->npl); 2398 clk_disable_unprepare(tx->fsgen); 2399 2400 lpass_macro_pds_exit(tx->pds); 2401} 2402 2403static int __maybe_unused tx_macro_runtime_suspend(struct device *dev) 2404{ 2405 struct tx_macro *tx = dev_get_drvdata(dev); 2406 2407 regcache_cache_only(tx->regmap, true); 2408 regcache_mark_dirty(tx->regmap); 2409 2410 clk_disable_unprepare(tx->fsgen); 2411 clk_disable_unprepare(tx->npl); 2412 clk_disable_unprepare(tx->mclk); 2413 2414 return 0; 2415} 2416 2417static int __maybe_unused tx_macro_runtime_resume(struct device *dev) 2418{ 2419 struct tx_macro *tx = dev_get_drvdata(dev); 2420 int ret; 2421 2422 ret = clk_prepare_enable(tx->mclk); 2423 if (ret) { 2424 dev_err(dev, "unable to prepare mclk\n"); 2425 return ret; 2426 } 2427 2428 ret = clk_prepare_enable(tx->npl); 2429 if (ret) { 2430 dev_err(dev, "unable to prepare npl\n"); 2431 goto err_npl; 2432 } 2433 2434 ret = clk_prepare_enable(tx->fsgen); 2435 if (ret) { 2436 dev_err(dev, "unable to prepare fsgen\n"); 2437 goto err_fsgen; 2438 } 2439 2440 regcache_cache_only(tx->regmap, false); 2441 regcache_sync(tx->regmap); 2442 2443 return 0; 2444err_fsgen: 2445 clk_disable_unprepare(tx->npl); 2446err_npl: 2447 clk_disable_unprepare(tx->mclk); 2448 2449 return ret; 2450} 2451 2452static const struct dev_pm_ops tx_macro_pm_ops = { 2453 SET_RUNTIME_PM_OPS(tx_macro_runtime_suspend, tx_macro_runtime_resume, NULL) 2454}; 2455 2456static const struct tx_macro_data lpass_ver_9 = { 2457 .flags = LPASS_MACRO_FLAG_HAS_NPL_CLOCK | 2458 LPASS_MACRO_FLAG_RESET_SWR, 2459 .ver = LPASS_VER_9_0_0, 2460 .extra_widgets = tx_macro_dapm_widgets_v9, 2461 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9), 2462 .extra_routes = tx_audio_map_v9, 2463 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9), 2464}; 2465 2466static const struct tx_macro_data lpass_ver_9_2 = { 2467 .flags = LPASS_MACRO_FLAG_HAS_NPL_CLOCK | 2468 LPASS_MACRO_FLAG_RESET_SWR, 2469 .ver = LPASS_VER_9_2_0, 2470 .extra_widgets = tx_macro_dapm_widgets_v9_2, 2471 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9_2), 2472 .extra_routes = tx_audio_map_v9_2, 2473 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9_2), 2474}; 2475 2476static const struct tx_macro_data lpass_ver_10_sm6115 = { 2477 .flags = LPASS_MACRO_FLAG_HAS_NPL_CLOCK, 2478 .ver = LPASS_VER_10_0_0, 2479 .extra_widgets = tx_macro_dapm_widgets_v9_2, 2480 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9_2), 2481 .extra_routes = tx_audio_map_v9_2, 2482 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9_2), 2483}; 2484 2485static const struct tx_macro_data lpass_ver_11 = { 2486 .flags = LPASS_MACRO_FLAG_RESET_SWR, 2487 .ver = LPASS_VER_11_0_0, 2488 .extra_widgets = tx_macro_dapm_widgets_v9_2, 2489 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9_2), 2490 .extra_routes = tx_audio_map_v9_2, 2491 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9_2), 2492}; 2493 2494static const struct of_device_id tx_macro_dt_match[] = { 2495 { 2496 /* 2497 * The block is actually LPASS v9.4, but keep LPASS v9 match 2498 * data and audio widgets, due to compatibility reasons. 2499 * Microphones are working on SC7280 fine, so apparently the fix 2500 * is not necessary. 2501 */ 2502 .compatible = "qcom,sc7280-lpass-tx-macro", 2503 .data = &lpass_ver_9, 2504 }, { 2505 .compatible = "qcom,sm6115-lpass-tx-macro", 2506 .data = &lpass_ver_10_sm6115, 2507 }, { 2508 .compatible = "qcom,sm8250-lpass-tx-macro", 2509 .data = &lpass_ver_9, 2510 }, { 2511 .compatible = "qcom,sm8450-lpass-tx-macro", 2512 .data = &lpass_ver_9_2, 2513 }, { 2514 .compatible = "qcom,sm8550-lpass-tx-macro", 2515 .data = &lpass_ver_11, 2516 }, { 2517 .compatible = "qcom,sc8280xp-lpass-tx-macro", 2518 /* 2519 * The block is actually LPASS v9.3, but keep LPASS v9 match 2520 * data and audio widgets, due to compatibility reasons. 2521 * Microphones are working on SC8280xp fine, so apparently the 2522 * fix is not necessary. 2523 */ 2524 .data = &lpass_ver_9, 2525 }, 2526 { } 2527}; 2528MODULE_DEVICE_TABLE(of, tx_macro_dt_match); 2529static struct platform_driver tx_macro_driver = { 2530 .driver = { 2531 .name = "tx_macro", 2532 .of_match_table = tx_macro_dt_match, 2533 .suppress_bind_attrs = true, 2534 .pm = &tx_macro_pm_ops, 2535 }, 2536 .probe = tx_macro_probe, 2537 .remove_new = tx_macro_remove, 2538}; 2539 2540module_platform_driver(tx_macro_driver); 2541 2542MODULE_DESCRIPTION("TX macro driver"); 2543MODULE_LICENSE("GPL"); 2544