1/* 2 * P2020/P2010 Silicon/SoC Device Tree Source (post include) 3 * 4 * Copyright 2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35&lbc { 36 #address-cells = <2>; 37 #size-cells = <1>; 38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus"; 39 interrupts = <19 2 0 0>; 40}; 41 42/* controller at 0xa000 */ 43&pci0 { 44 compatible = "fsl,mpc8548-pcie"; 45 device_type = "pci"; 46 #size-cells = <2>; 47 #address-cells = <3>; 48 bus-range = <0 255>; 49 clock-frequency = <33333333>; 50 interrupts = <26 2 0 0>; 51 law_trgt_if = <2>; 52 53 pcie@0 { 54 reg = <0 0 0 0 0>; 55 #interrupt-cells = <1>; 56 #size-cells = <2>; 57 #address-cells = <3>; 58 device_type = "pci"; 59 interrupts = <26 2 0 0>; 60 interrupt-map-mask = <0xf800 0 0 7>; 61 interrupt-map = < 62 /* IDSEL 0x0 */ 63 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 64 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 65 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 66 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 67 >; 68 }; 69}; 70 71/* controller at 0x9000 */ 72&pci1 { 73 compatible = "fsl,mpc8548-pcie"; 74 device_type = "pci"; 75 #size-cells = <2>; 76 #address-cells = <3>; 77 bus-range = <0 255>; 78 clock-frequency = <33333333>; 79 interrupts = <25 2 0 0>; 80 law_trgt_if = <1>; 81 82 pcie@0 { 83 reg = <0 0 0 0 0>; 84 #interrupt-cells = <1>; 85 #size-cells = <2>; 86 #address-cells = <3>; 87 device_type = "pci"; 88 interrupts = <25 2 0 0>; 89 interrupt-map-mask = <0xf800 0 0 7>; 90 91 interrupt-map = < 92 /* IDSEL 0x0 */ 93 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 94 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 95 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 96 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 97 >; 98 }; 99}; 100 101/* controller at 0x8000 */ 102&pci2 { 103 compatible = "fsl,mpc8548-pcie"; 104 device_type = "pci"; 105 #size-cells = <2>; 106 #address-cells = <3>; 107 bus-range = <0 255>; 108 clock-frequency = <33333333>; 109 interrupts = <24 2 0 0>; 110 law_trgt_if = <0>; 111 112 pcie@0 { 113 reg = <0 0 0 0 0>; 114 #interrupt-cells = <1>; 115 #size-cells = <2>; 116 #address-cells = <3>; 117 device_type = "pci"; 118 interrupts = <24 2 0 0>; 119 interrupt-map-mask = <0xf800 0 0 7>; 120 121 interrupt-map = < 122 /* IDSEL 0x0 */ 123 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 124 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 125 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 126 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 127 >; 128 }; 129}; 130 131&soc { 132 #address-cells = <1>; 133 #size-cells = <1>; 134 device_type = "soc"; 135 compatible = "fsl,p2020-immr", "simple-bus"; 136 bus-frequency = <0>; // Filled out by uboot. 137 138 ecm-law@0 { 139 compatible = "fsl,ecm-law"; 140 reg = <0x0 0x1000>; 141 fsl,num-laws = <12>; 142 }; 143 144 ecm@1000 { 145 compatible = "fsl,p2020-ecm", "fsl,ecm"; 146 reg = <0x1000 0x1000>; 147 interrupts = <17 2 0 0>; 148 }; 149 150 memory-controller@2000 { 151 compatible = "fsl,p2020-memory-controller"; 152 reg = <0x2000 0x1000>; 153 interrupts = <18 2 0 0>; 154 }; 155 156/include/ "pq3-i2c-0.dtsi" 157/include/ "pq3-i2c-1.dtsi" 158/include/ "pq3-duart-0.dtsi" 159/include/ "pq3-espi-0.dtsi" 160 spi0: spi@7000 { 161 fsl,espi-num-chipselects = <4>; 162 }; 163 164/include/ "pq3-dma-1.dtsi" 165/include/ "pq3-gpio-0.dtsi" 166 167 L2: l2-cache-controller@20000 { 168 compatible = "fsl,p2020-l2-cache-controller"; 169 reg = <0x20000 0x1000>; 170 cache-line-size = <32>; // 32 bytes 171 cache-size = <0x80000>; // L2,512K 172 interrupts = <16 2 0 0>; 173 }; 174 175/include/ "pq3-dma-0.dtsi" 176/include/ "pq3-usb2-dr-0.dtsi" 177 usb@22000 { 178 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; 179 }; 180/include/ "pq3-etsec1-0.dtsi" 181 enet0: ethernet@24000 { 182 fsl,pmc-handle = <&etsec1_clk>; 183 184 }; 185/include/ "pq3-etsec1-timer-0.dtsi" 186 187 ptp_clock@24e00 { 188 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>; 189 }; 190 191 192/include/ "pq3-etsec1-1.dtsi" 193 enet1: ethernet@25000 { 194 fsl,pmc-handle = <&etsec2_clk>; 195 }; 196 197/include/ "pq3-etsec1-2.dtsi" 198 enet2: ethernet@26000 { 199 fsl,pmc-handle = <&etsec3_clk>; 200 }; 201 202/include/ "pq3-esdhc-0.dtsi" 203 sdhc@2e000 { 204 compatible = "fsl,p2020-esdhc", "fsl,esdhc"; 205 }; 206 207/include/ "pq3-sec3.1-0.dtsi" 208/include/ "pq3-mpic.dtsi" 209/include/ "pq3-mpic-timer-B.dtsi" 210 211 global-utilities@e0000 { 212 compatible = "fsl,p2020-guts"; 213 reg = <0xe0000 0x1000>; 214 fsl,has-rstcr; 215 }; 216 217/include/ "pq3-power.dtsi" 218}; 219