1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * P2020 RDB Device Tree Source
4 *
5 * Copyright 2009-2012 Freescale Semiconductor Inc.
6 */
7
8/include/ "p2020si-pre.dtsi"
9
10/ {
11	model = "fsl,P2020RDB";
12	compatible = "fsl,P2020RDB";
13
14	aliases {
15		ethernet0 = &enet0;
16		ethernet1 = &enet1;
17		ethernet2 = &enet2;
18		serial0 = &serial0;
19		serial1 = &serial1;
20		pci0 = &pci0;
21		pci1 = &pci1;
22	};
23
24	memory {
25		device_type = "memory";
26	};
27
28	lbc: localbus@ffe05000 {
29		reg = <0 0xffe05000 0 0x1000>;
30
31		/* NOR and NAND Flashes */
32		ranges = <0x0 0x0 0x0 0xef000000 0x01000000
33			  0x1 0x0 0x0 0xffa00000 0x00040000
34			  0x2 0x0 0x0 0xffb00000 0x00020000>;
35
36		nor@0,0 {
37			#address-cells = <1>;
38			#size-cells = <1>;
39			compatible = "cfi-flash";
40			reg = <0x0 0x0 0x1000000>;
41			bank-width = <2>;
42			device-width = <1>;
43
44			partition@0 {
45				/* This location must not be altered  */
46				/* 256KB for Vitesse 7385 Switch firmware */
47				reg = <0x0 0x00040000>;
48				label = "NOR (RO) Vitesse-7385 Firmware";
49				read-only;
50			};
51
52			partition@40000 {
53				/* 256KB for DTB Image */
54				reg = <0x00040000 0x00040000>;
55				label = "NOR (RO) DTB Image";
56				read-only;
57			};
58
59			partition@80000 {
60				/* 3.5 MB for Linux Kernel Image */
61				reg = <0x00080000 0x00380000>;
62				label = "NOR (RO) Linux Kernel Image";
63				read-only;
64			};
65
66			partition@400000 {
67				/* 11MB for JFFS2 based Root file System */
68				reg = <0x00400000 0x00b00000>;
69				label = "NOR (RW) JFFS2 Root File System";
70			};
71
72			partition@f00000 {
73				/* This location must not be altered  */
74				/* 512KB for u-boot Bootloader Image */
75				/* 512KB for u-boot Environment Variables */
76				reg = <0x00f00000 0x00100000>;
77				label = "NOR (RO) U-Boot Image";
78				read-only;
79			};
80		};
81
82		nand@1,0 {
83			#address-cells = <1>;
84			#size-cells = <1>;
85			compatible = "fsl,p2020-fcm-nand",
86				     "fsl,elbc-fcm-nand";
87			reg = <0x1 0x0 0x40000>;
88
89			partition@0 {
90				/* This location must not be altered  */
91				/* 1MB for u-boot Bootloader Image */
92				reg = <0x0 0x00100000>;
93				label = "NAND (RO) U-Boot Image";
94				read-only;
95			};
96
97			partition@100000 {
98				/* 1MB for DTB Image */
99				reg = <0x00100000 0x00100000>;
100				label = "NAND (RO) DTB Image";
101				read-only;
102			};
103
104			partition@200000 {
105				/* 4MB for Linux Kernel Image */
106				reg = <0x00200000 0x00400000>;
107				label = "NAND (RO) Linux Kernel Image";
108				read-only;
109			};
110
111			partition@600000 {
112				/* 4MB for Compressed Root file System Image */
113				reg = <0x00600000 0x00400000>;
114				label = "NAND (RO) Compressed RFS Image";
115				read-only;
116			};
117
118			partition@a00000 {
119				/* 7MB for JFFS2 based Root file System */
120				reg = <0x00a00000 0x00700000>;
121				label = "NAND (RW) JFFS2 Root File System";
122			};
123
124			partition@1100000 {
125				/* 15MB for JFFS2 based Root file System */
126				reg = <0x01100000 0x00f00000>;
127				label = "NAND (RW) Writable User area";
128			};
129		};
130
131		L2switch@2,0 {
132			#address-cells = <1>;
133			#size-cells = <1>;
134			compatible = "vitesse-7385";
135			reg = <0x2 0x0 0x20000>;
136		};
137
138	};
139
140	soc: soc@ffe00000 {
141		ranges = <0x0 0x0 0xffe00000 0x100000>;
142
143		i2c@3000 {
144			rtc@68 {
145				compatible = "dallas,ds1339";
146				reg = <0x68>;
147			};
148		};
149
150		spi@7000 {
151			flash@0 {
152				#address-cells = <1>;
153				#size-cells = <1>;
154				compatible = "spansion,s25sl12801", "jedec,spi-nor";
155				reg = <0>;
156				spi-max-frequency = <40000000>;
157
158				partition@0 {
159					/* 512KB for u-boot Bootloader Image */
160					reg = <0x0 0x00080000>;
161					label = "SPI (RO) U-Boot Image";
162					read-only;
163				};
164
165				partition@80000 {
166					/* 512KB for DTB Image */
167					reg = <0x00080000 0x00080000>;
168					label = "SPI (RO) DTB Image";
169					read-only;
170				};
171
172				partition@100000 {
173					/* 4MB for Linux Kernel Image */
174					reg = <0x00100000 0x00400000>;
175					label = "SPI (RO) Linux Kernel Image";
176					read-only;
177				};
178
179				partition@500000 {
180					/* 4MB for Compressed RFS Image */
181					reg = <0x00500000 0x00400000>;
182					label = "SPI (RO) Compressed RFS Image";
183					read-only;
184				};
185
186				partition@900000 {
187					/* 7MB for JFFS2 based RFS */
188					reg = <0x00900000 0x00700000>;
189					label = "SPI (RW) JFFS2 RFS";
190				};
191			};
192		};
193
194		usb@22000 {
195			phy_type = "ulpi";
196			dr_mode = "host";
197		};
198
199		mdio@24520 {
200			phy0: ethernet-phy@0 {
201				interrupts = <3 1 0 0>;
202				reg = <0x0>;
203			};
204			phy1: ethernet-phy@1 {
205				interrupts = <3 1 0 0>;
206				reg = <0x1>;
207			};
208			tbi-phy@2 {
209				device_type = "tbi-phy";
210				reg = <0x2>;
211			};
212		};
213
214		mdio@25520 {
215			tbi0: tbi-phy@11 {
216				reg = <0x11>;
217				device_type = "tbi-phy";
218			};
219		};
220
221		mdio@26520 {
222			status = "disabled";
223		};
224
225		ptp_clock@24e00 {
226			fsl,tclk-period = <5>;
227			fsl,tmr-prsc = <200>;
228			fsl,tmr-add = <0xCCCCCCCD>;
229			fsl,tmr-fiper1 = <0x3B9AC9FB>;
230			fsl,tmr-fiper2 = <0x0001869B>;
231			fsl,max-adj = <249999999>;
232		};
233
234		enet0: ethernet@24000 {
235			fixed-link = <1 1 1000 0 0>;
236			phy-connection-type = "rgmii-id";
237		};
238
239		enet1: ethernet@25000 {
240			tbi-handle = <&tbi0>;
241			phy-handle = <&phy0>;
242			phy-connection-type = "sgmii";
243		};
244
245		enet2: ethernet@26000 {
246			phy-handle = <&phy1>;
247			phy-connection-type = "rgmii-id";
248		};
249	};
250
251	pci0: pcie@ffe08000 {
252		reg = <0 0xffe08000 0 0x1000>;
253		status = "disabled";
254	};
255
256	pci1: pcie@ffe09000 {
257		reg = <0 0xffe09000 0 0x1000>;
258		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
259			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
260		pcie@0 {
261			ranges = <0x2000000 0x0 0xa0000000
262				  0x2000000 0x0 0xa0000000
263				  0x0 0x20000000
264
265				  0x1000000 0x0 0x0
266				  0x1000000 0x0 0x0
267				  0x0 0x100000>;
268		};
269	};
270
271	pci2: pcie@ffe0a000 {
272		reg = <0 0xffe0a000 0 0x1000>;
273		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
274			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
275		pcie@0 {
276			ranges = <0x2000000 0x0 0x80000000
277				  0x2000000 0x0 0x80000000
278				  0x0 0x20000000
279
280				  0x1000000 0x0 0x0
281				  0x1000000 0x0 0x0
282				  0x0 0x100000>;
283		};
284	};
285};
286
287/include/ "p2020si-post.dtsi"
288