1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 3 4#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H 5#define DT_BINDINGS_MEMORY_TEGRA234_MC_H 6 7/* special clients */ 8#define TEGRA234_SID_INVALID 0x00 9#define TEGRA234_SID_PASSTHROUGH 0x7f 10 11/* ISO stream IDs */ 12#define TEGRA234_SID_ISO_NVDISPLAY 0x01 13#define TEGRA234_SID_ISO_VI 0x02 14#define TEGRA234_SID_ISO_VIFALC 0x03 15#define TEGRA234_SID_ISO_VI2 0x04 16#define TEGRA234_SID_ISO_VI2FALC 0x05 17#define TEGRA234_SID_ISO_VI_VM2 0x06 18#define TEGRA234_SID_ISO_VI2_VM2 0x07 19 20/* NISO0 stream IDs */ 21#define TEGRA234_SID_AON 0x01 22#define TEGRA234_SID_APE 0x02 23#define TEGRA234_SID_HDA 0x03 24#define TEGRA234_SID_GPCDMA 0x04 25#define TEGRA234_SID_ETR 0x05 26#define TEGRA234_SID_MGBE 0x06 27#define TEGRA234_SID_NVDISPLAY 0x07 28#define TEGRA234_SID_DCE 0x08 29#define TEGRA234_SID_PSC 0x09 30#define TEGRA234_SID_RCE 0x0a 31#define TEGRA234_SID_SCE 0x0b 32#define TEGRA234_SID_UFSHC 0x0c 33#define TEGRA234_SID_APE_1 0x0d 34#define TEGRA234_SID_GPCDMA_1 0x0e 35#define TEGRA234_SID_GPCDMA_2 0x0f 36#define TEGRA234_SID_GPCDMA_3 0x10 37#define TEGRA234_SID_GPCDMA_4 0x11 38#define TEGRA234_SID_PCIE0 0x12 39#define TEGRA234_SID_PCIE4 0x13 40#define TEGRA234_SID_PCIE5 0x14 41#define TEGRA234_SID_PCIE6 0x15 42#define TEGRA234_SID_RCE_VM2 0x16 43#define TEGRA234_SID_RCE_SERVER 0x17 44#define TEGRA234_SID_SMMU_TEST 0x18 45#define TEGRA234_SID_UFS_1 0x19 46#define TEGRA234_SID_UFS_2 0x1a 47#define TEGRA234_SID_UFS_3 0x1b 48#define TEGRA234_SID_UFS_4 0x1c 49#define TEGRA234_SID_UFS_5 0x1d 50#define TEGRA234_SID_UFS_6 0x1e 51#define TEGRA234_SID_PCIE9 0x1f 52#define TEGRA234_SID_VSE_GPCDMA_VM0 0x20 53#define TEGRA234_SID_VSE_GPCDMA_VM1 0x21 54#define TEGRA234_SID_VSE_GPCDMA_VM2 0x22 55#define TEGRA234_SID_NVDLA1 0x23 56#define TEGRA234_SID_NVENC 0x24 57#define TEGRA234_SID_NVJPG1 0x25 58#define TEGRA234_SID_OFA 0x26 59#define TEGRA234_SID_MGBE_VF1 0x49 60#define TEGRA234_SID_MGBE_VF2 0x4a 61#define TEGRA234_SID_MGBE_VF3 0x4b 62#define TEGRA234_SID_MGBE_VF4 0x4c 63#define TEGRA234_SID_MGBE_VF5 0x4d 64#define TEGRA234_SID_MGBE_VF6 0x4e 65#define TEGRA234_SID_MGBE_VF7 0x4f 66#define TEGRA234_SID_MGBE_VF8 0x50 67#define TEGRA234_SID_MGBE_VF9 0x51 68#define TEGRA234_SID_MGBE_VF10 0x52 69#define TEGRA234_SID_MGBE_VF11 0x53 70#define TEGRA234_SID_MGBE_VF12 0x54 71#define TEGRA234_SID_MGBE_VF13 0x55 72#define TEGRA234_SID_MGBE_VF14 0x56 73#define TEGRA234_SID_MGBE_VF15 0x57 74#define TEGRA234_SID_MGBE_VF16 0x58 75#define TEGRA234_SID_MGBE_VF17 0x59 76#define TEGRA234_SID_MGBE_VF18 0x5a 77#define TEGRA234_SID_MGBE_VF19 0x5b 78#define TEGRA234_SID_MGBE_VF20 0x5c 79#define TEGRA234_SID_APE_2 0x5e 80#define TEGRA234_SID_APE_3 0x5f 81#define TEGRA234_SID_UFS_7 0x60 82#define TEGRA234_SID_UFS_8 0x61 83#define TEGRA234_SID_UFS_9 0x62 84#define TEGRA234_SID_UFS_10 0x63 85#define TEGRA234_SID_UFS_11 0x64 86#define TEGRA234_SID_UFS_12 0x65 87#define TEGRA234_SID_UFS_13 0x66 88#define TEGRA234_SID_UFS_14 0x67 89#define TEGRA234_SID_UFS_15 0x68 90#define TEGRA234_SID_UFS_16 0x69 91#define TEGRA234_SID_UFS_17 0x6a 92#define TEGRA234_SID_UFS_18 0x6b 93#define TEGRA234_SID_UFS_19 0x6c 94#define TEGRA234_SID_UFS_20 0x6d 95#define TEGRA234_SID_GPCDMA_5 0x6e 96#define TEGRA234_SID_GPCDMA_6 0x6f 97#define TEGRA234_SID_GPCDMA_7 0x70 98#define TEGRA234_SID_GPCDMA_8 0x71 99#define TEGRA234_SID_GPCDMA_9 0x72 100 101/* NISO1 stream IDs */ 102#define TEGRA234_SID_SDMMC1A 0x01 103#define TEGRA234_SID_SDMMC4 0x02 104#define TEGRA234_SID_EQOS 0x03 105#define TEGRA234_SID_HWMP_PMA 0x04 106#define TEGRA234_SID_PCIE1 0x05 107#define TEGRA234_SID_PCIE2 0x06 108#define TEGRA234_SID_PCIE3 0x07 109#define TEGRA234_SID_PCIE7 0x08 110#define TEGRA234_SID_PCIE8 0x09 111#define TEGRA234_SID_PCIE10 0x0b 112#define TEGRA234_SID_QSPI0 0x0c 113#define TEGRA234_SID_QSPI1 0x0d 114#define TEGRA234_SID_XUSB_HOST 0x0e 115#define TEGRA234_SID_XUSB_DEV 0x0f 116#define TEGRA234_SID_BPMP 0x10 117#define TEGRA234_SID_FSI 0x11 118#define TEGRA234_SID_PVA0_VM0 0x12 119#define TEGRA234_SID_PVA0_VM1 0x13 120#define TEGRA234_SID_PVA0_VM2 0x14 121#define TEGRA234_SID_PVA0_VM3 0x15 122#define TEGRA234_SID_PVA0_VM4 0x16 123#define TEGRA234_SID_PVA0_VM5 0x17 124#define TEGRA234_SID_PVA0_VM6 0x18 125#define TEGRA234_SID_PVA0_VM7 0x19 126#define TEGRA234_SID_XUSB_VF0 0x1a 127#define TEGRA234_SID_XUSB_VF1 0x1b 128#define TEGRA234_SID_XUSB_VF2 0x1c 129#define TEGRA234_SID_XUSB_VF3 0x1d 130#define TEGRA234_SID_EQOS_VF1 0x1e 131#define TEGRA234_SID_EQOS_VF2 0x1f 132#define TEGRA234_SID_EQOS_VF3 0x20 133#define TEGRA234_SID_EQOS_VF4 0x21 134#define TEGRA234_SID_ISP_VM2 0x22 135#define TEGRA234_SID_HOST1X 0x27 136#define TEGRA234_SID_ISP 0x28 137#define TEGRA234_SID_NVDEC 0x29 138#define TEGRA234_SID_NVJPG 0x2a 139#define TEGRA234_SID_NVDLA0 0x2b 140#define TEGRA234_SID_PVA0 0x2c 141#define TEGRA234_SID_SES_SE0 0x2d 142#define TEGRA234_SID_SES_SE1 0x2e 143#define TEGRA234_SID_SES_SE2 0x2f 144#define TEGRA234_SID_SEU1_SE0 0x30 145#define TEGRA234_SID_SEU1_SE1 0x31 146#define TEGRA234_SID_SEU1_SE2 0x32 147#define TEGRA234_SID_TSEC 0x33 148#define TEGRA234_SID_VIC 0x34 149#define TEGRA234_SID_HC_VM0 0x3d 150#define TEGRA234_SID_HC_VM1 0x3e 151#define TEGRA234_SID_HC_VM2 0x3f 152#define TEGRA234_SID_HC_VM3 0x40 153#define TEGRA234_SID_HC_VM4 0x41 154#define TEGRA234_SID_HC_VM5 0x42 155#define TEGRA234_SID_HC_VM6 0x43 156#define TEGRA234_SID_HC_VM7 0x44 157#define TEGRA234_SID_SE_VM0 0x45 158#define TEGRA234_SID_SE_VM1 0x46 159#define TEGRA234_SID_SE_VM2 0x47 160#define TEGRA234_SID_ISPFALC 0x48 161#define TEGRA234_SID_NISO1_SMMU_TEST 0x49 162#define TEGRA234_SID_TSEC_VM0 0x4a 163 164/* Shared stream IDs */ 165#define TEGRA234_SID_HOST1X_CTX0 0x35 166#define TEGRA234_SID_HOST1X_CTX1 0x36 167#define TEGRA234_SID_HOST1X_CTX2 0x37 168#define TEGRA234_SID_HOST1X_CTX3 0x38 169#define TEGRA234_SID_HOST1X_CTX4 0x39 170#define TEGRA234_SID_HOST1X_CTX5 0x3a 171#define TEGRA234_SID_HOST1X_CTX6 0x3b 172#define TEGRA234_SID_HOST1X_CTX7 0x3c 173 174/* 175 * memory client IDs 176 */ 177 178/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ 179#define TEGRA234_MEMORY_CLIENT_PTCR 0x00 180/* MSS internal memqual MIU7 read clients */ 181#define TEGRA234_MEMORY_CLIENT_MIU7R 0x01 182/* MSS internal memqual MIU7 write clients */ 183#define TEGRA234_MEMORY_CLIENT_MIU7W 0x02 184/* MSS internal memqual MIU8 read clients */ 185#define TEGRA234_MEMORY_CLIENT_MIU8R 0x03 186/* MSS internal memqual MIU8 write clients */ 187#define TEGRA234_MEMORY_CLIENT_MIU8W 0x04 188/* MSS internal memqual MIU9 read clients */ 189#define TEGRA234_MEMORY_CLIENT_MIU9R 0x05 190/* MSS internal memqual MIU9 write clients */ 191#define TEGRA234_MEMORY_CLIENT_MIU9W 0x06 192/* MSS internal memqual MIU10 read clients */ 193#define TEGRA234_MEMORY_CLIENT_MIU10R 0x07 194/* MSS internal memqual MIU10 write clients */ 195#define TEGRA234_MEMORY_CLIENT_MIU10W 0x08 196/* MSS internal memqual MIU11 read clients */ 197#define TEGRA234_MEMORY_CLIENT_MIU11R 0x09 198/* MSS internal memqual MIU11 write clients */ 199#define TEGRA234_MEMORY_CLIENT_MIU11W 0x0a 200/* MSS internal memqual MIU12 read clients */ 201#define TEGRA234_MEMORY_CLIENT_MIU12R 0x0b 202/* MSS internal memqual MIU12 write clients */ 203#define TEGRA234_MEMORY_CLIENT_MIU12W 0x0c 204/* MSS internal memqual MIU13 read clients */ 205#define TEGRA234_MEMORY_CLIENT_MIU13R 0x0d 206/* MSS internal memqual MIU13 write clients */ 207#define TEGRA234_MEMORY_CLIENT_MIU13W 0x0e 208#define TEGRA234_MEMORY_CLIENT_NVL5RHP 0x13 209#define TEGRA234_MEMORY_CLIENT_NVL5R 0x14 210/* High-definition audio (HDA) read clients */ 211#define TEGRA234_MEMORY_CLIENT_HDAR 0x15 212/* Host channel data read clients */ 213#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 214#define TEGRA234_MEMORY_CLIENT_NVL5W 0x17 215#define TEGRA234_MEMORY_CLIENT_NVL6RHP 0x18 216#define TEGRA234_MEMORY_CLIENT_NVL6R 0x19 217#define TEGRA234_MEMORY_CLIENT_NVL6W 0x1a 218#define TEGRA234_MEMORY_CLIENT_NVL7RHP 0x1b 219#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c 220#define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d 221#define TEGRA234_MEMORY_CLIENT_NVL7W 0x1e 222#define TEGRA234_MEMORY_CLIENT_NVL8RHP 0x20 223#define TEGRA234_MEMORY_CLIENT_NVL8R 0x21 224#define TEGRA234_MEMORY_CLIENT_NVL8W 0x22 225#define TEGRA234_MEMORY_CLIENT_NVL9RHP 0x23 226#define TEGRA234_MEMORY_CLIENT_NVL9R 0x24 227#define TEGRA234_MEMORY_CLIENT_NVL9W 0x25 228/* PCIE6 read clients */ 229#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 230/* PCIE6 write clients */ 231#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 232/* PCIE7 read clients */ 233#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a 234#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b 235/* DLA0ARDB read clients */ 236#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c 237/* DLA0ARDB1 read clients */ 238#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d 239/* DLA0 writes */ 240#define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e 241/* DLA1ARDB read clients */ 242#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f 243/* PCIE7 write clients */ 244#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 245/* PCIE8 read clients */ 246#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 247/* High-definition audio (HDA) write clients */ 248#define TEGRA234_MEMORY_CLIENT_HDAW 0x35 249/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ 250#define TEGRA234_MEMORY_CLIENT_MPCOREW 0x39 251/* OFAA client */ 252#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a 253/* PCIE8 write clients */ 254#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b 255/* PCIE9 read clients */ 256#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c 257/* PCIE6r1 read clients */ 258#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d 259/* PCIE9 write clients */ 260#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e 261/* PCIE10 read clients */ 262#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f 263/* PCIE10 write clients */ 264#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 265/* ISP read client for Crossbar A */ 266#define TEGRA234_MEMORY_CLIENT_ISPRA 0x44 267/* ISP read client 1 for Crossbar A */ 268#define TEGRA234_MEMORY_CLIENT_ISPFALR 0x45 269/* ISP Write client for Crossbar A */ 270#define TEGRA234_MEMORY_CLIENT_ISPWA 0x46 271/* ISP Write client Crossbar B */ 272#define TEGRA234_MEMORY_CLIENT_ISPWB 0x47 273/* PCIE10r1 read clients */ 274#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 275/* PCIE7r1 read clients */ 276#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 277/* XUSB_HOST read clients */ 278#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTR 0x4a 279/* XUSB_HOST write clients */ 280#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTW 0x4b 281/* XUSB read clients */ 282#define TEGRA234_MEMORY_CLIENT_XUSB_DEVR 0x4c 283/* XUSB_DEV write clients */ 284#define TEGRA234_MEMORY_CLIENT_XUSB_DEVW 0x4d 285/* TSEC Memory Return Data Client Description */ 286#define TEGRA234_MEMORY_CLIENT_TSECSRD 0x54 287/* TSEC Memory Write Client Description */ 288#define TEGRA234_MEMORY_CLIENT_TSECSWR 0x55 289/* XSPI writes */ 290#define TEGRA234_MEMORY_CLIENT_XSPI1W 0x56 291/* MGBE0 read client */ 292#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 293/* MGBEB read client */ 294#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59 295/* MGBEC read client */ 296#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a 297/* MGBED read client */ 298#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b 299/* MGBE0 write client */ 300#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c 301/* OFAA client */ 302#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d 303/* OFAA writes */ 304#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e 305/* MGBEB write client */ 306#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f 307/* sdmmca memory read client */ 308#define TEGRA234_MEMORY_CLIENT_SDMMCRA 0x60 309/* MGBEC write client */ 310#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 311/* sdmmcd memory read client */ 312#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 313/* sdmmca memory write client */ 314#define TEGRA234_MEMORY_CLIENT_SDMMCWA 0x64 315/* MGBED write client */ 316#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 317/* sdmmcd memory write client */ 318#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 319/* SE Memory Return Data Client Description */ 320#define TEGRA234_MEMORY_CLIENT_SEU1RD 0x68 321/* SE Memory Write Client Description */ 322#define TEGRA234_MEMORY_CLIENT_SUE1WR 0x69 323#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c 324#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d 325/* DLA1ARDB1 read clients */ 326#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e 327/* DLA1 writes */ 328#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f 329/* VI FLACON read clients */ 330#define TEGRA234_MEMORY_CLIENT_VI2FALR 0x71 331/* VI Write client */ 332#define TEGRA234_MEMORY_CLIENT_VI2W 0x70 333/* VI Write client */ 334#define TEGRA234_MEMORY_CLIENT_VIW 0x72 335/* NISO display read client */ 336#define TEGRA234_MEMORY_CLIENT_NVDISPNISOR 0x73 337/* NVDISPNISO writes */ 338#define TEGRA234_MEMORY_CLIENT_NVDISPNISOW 0x74 339/* XSPI client */ 340#define TEGRA234_MEMORY_CLIENT_XSPI0R 0x75 341/* XSPI writes */ 342#define TEGRA234_MEMORY_CLIENT_XSPI0W 0x76 343/* XSPI client */ 344#define TEGRA234_MEMORY_CLIENT_XSPI1R 0x77 345#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78 346#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79 347/* Audio Processing (APE) engine read clients */ 348#define TEGRA234_MEMORY_CLIENT_APER 0x7a 349/* Audio Processing (APE) engine write clients */ 350#define TEGRA234_MEMORY_CLIENT_APEW 0x7b 351/* VI2FAL writes */ 352#define TEGRA234_MEMORY_CLIENT_VI2FALW 0x7c 353#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e 354#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f 355/* SE Memory Return Data Client Description */ 356#define TEGRA234_MEMORY_CLIENT_SESRD 0x80 357/* SE Memory Write Client Description */ 358#define TEGRA234_MEMORY_CLIENT_SESWR 0x81 359/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ 360#define TEGRA234_MEMORY_CLIENT_AXIAPR 0x82 361/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ 362#define TEGRA234_MEMORY_CLIENT_AXIAPW 0x83 363/* ETR read clients */ 364#define TEGRA234_MEMORY_CLIENT_ETRR 0x84 365/* ETR write clients */ 366#define TEGRA234_MEMORY_CLIENT_ETRW 0x85 367/* AXI Switch read client */ 368#define TEGRA234_MEMORY_CLIENT_AXISR 0x8c 369/* AXI Switch write client */ 370#define TEGRA234_MEMORY_CLIENT_AXISW 0x8d 371/* EQOS read client */ 372#define TEGRA234_MEMORY_CLIENT_EQOSR 0x8e 373/* EQOS write client */ 374#define TEGRA234_MEMORY_CLIENT_EQOSW 0x8f 375/* UFSHC read client */ 376#define TEGRA234_MEMORY_CLIENT_UFSHCR 0x90 377/* UFSHC write client */ 378#define TEGRA234_MEMORY_CLIENT_UFSHCW 0x91 379/* NVDISPLAY read client */ 380#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR 0x92 381/* BPMP read client */ 382#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 383/* BPMP write client */ 384#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 385/* BPMPDMA read client */ 386#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 387/* BPMPDMA write client */ 388#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 389/* AON read client */ 390#define TEGRA234_MEMORY_CLIENT_AONR 0x97 391/* AON write client */ 392#define TEGRA234_MEMORY_CLIENT_AONW 0x98 393/* AONDMA read client */ 394#define TEGRA234_MEMORY_CLIENT_AONDMAR 0x99 395/* AONDMA write client */ 396#define TEGRA234_MEMORY_CLIENT_AONDMAW 0x9a 397/* SCE read client */ 398#define TEGRA234_MEMORY_CLIENT_SCER 0x9b 399/* SCE write client */ 400#define TEGRA234_MEMORY_CLIENT_SCEW 0x9c 401/* SCEDMA read client */ 402#define TEGRA234_MEMORY_CLIENT_SCEDMAR 0x9d 403/* SCEDMA write client */ 404#define TEGRA234_MEMORY_CLIENT_SCEDMAW 0x9e 405/* APEDMA read client */ 406#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f 407/* APEDMA write client */ 408#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 409/* NVDISPLAY read client instance 2 */ 410#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 0xa1 411#define TEGRA234_MEMORY_CLIENT_VICSRD1 0xa2 412/* MSS internal memqual MIU0 read clients */ 413#define TEGRA234_MEMORY_CLIENT_MIU0R 0xa6 414/* MSS internal memqual MIU0 write clients */ 415#define TEGRA234_MEMORY_CLIENT_MIU0W 0xa7 416/* MSS internal memqual MIU1 read clients */ 417#define TEGRA234_MEMORY_CLIENT_MIU1R 0xa8 418/* MSS internal memqual MIU1 write clients */ 419#define TEGRA234_MEMORY_CLIENT_MIU1W 0xa9 420/* MSS internal memqual MIU2 read clients */ 421#define TEGRA234_MEMORY_CLIENT_MIU2R 0xae 422/* MSS internal memqual MIU2 write clients */ 423#define TEGRA234_MEMORY_CLIENT_MIU2W 0xaf 424/* MSS internal memqual MIU3 read clients */ 425#define TEGRA234_MEMORY_CLIENT_MIU3R 0xb0 426/* MSS internal memqual MIU3 write clients */ 427#define TEGRA234_MEMORY_CLIENT_MIU3W 0xb1 428/* MSS internal memqual MIU4 read clients */ 429#define TEGRA234_MEMORY_CLIENT_MIU4R 0xb2 430/* MSS internal memqual MIU4 write clients */ 431#define TEGRA234_MEMORY_CLIENT_MIU4W 0xb3 432#define TEGRA234_MEMORY_CLIENT_DPMUR 0xb4 433#define TEGRA234_MEMORY_CLIENT_DPMUW 0xb5 434#define TEGRA234_MEMORY_CLIENT_NVL0R 0xb6 435#define TEGRA234_MEMORY_CLIENT_NVL0W 0xb7 436#define TEGRA234_MEMORY_CLIENT_NVL1R 0xb8 437#define TEGRA234_MEMORY_CLIENT_NVL1W 0xb9 438#define TEGRA234_MEMORY_CLIENT_NVL2R 0xba 439#define TEGRA234_MEMORY_CLIENT_NVL2W 0xbb 440/* VI FLACON read clients */ 441#define TEGRA234_MEMORY_CLIENT_VIFALR 0xbc 442/* VIFAL write clients */ 443#define TEGRA234_MEMORY_CLIENT_VIFALW 0xbd 444/* DLA0ARDA read clients */ 445#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe 446/* DLA0 Falcon read clients */ 447#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf 448/* DLA0 write clients */ 449#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0 450/* DLA0 write clients */ 451#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1 452/* DLA1ARDA read clients */ 453#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2 454/* DLA1 Falcon read clients */ 455#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3 456/* DLA1 write clients */ 457#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4 458/* DLA1 write clients */ 459#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5 460/* PVA0RDA read clients */ 461#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6 462/* PVA0RDB read clients */ 463#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7 464/* PVA0RDC read clients */ 465#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8 466/* PVA0WRA write clients */ 467#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9 468/* PVA0WRB write clients */ 469#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca 470/* PVA0WRC write clients */ 471#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb 472/* RCE read client */ 473#define TEGRA234_MEMORY_CLIENT_RCER 0xd2 474/* RCE write client */ 475#define TEGRA234_MEMORY_CLIENT_RCEW 0xd3 476/* RCEDMA read client */ 477#define TEGRA234_MEMORY_CLIENT_RCEDMAR 0xd4 478/* RCEDMA write client */ 479#define TEGRA234_MEMORY_CLIENT_RCEDMAW 0xd5 480/* PCIE0 read clients */ 481#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 482/* PCIE0 write clients */ 483#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 484/* PCIE1 read clients */ 485#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda 486/* PCIE1 write clients */ 487#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb 488/* PCIE2 read clients */ 489#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc 490/* PCIE2 write clients */ 491#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd 492/* PCIE3 read clients */ 493#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde 494/* PCIE3 write clients */ 495#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf 496/* PCIE4 read clients */ 497#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 498/* PCIE4 write clients */ 499#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 500/* PCIE5 read clients */ 501#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 502/* PCIE5 write clients */ 503#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 504/* ISP read client 1 for Crossbar A */ 505#define TEGRA234_MEMORY_CLIENT_ISPFALW 0xe4 506#define TEGRA234_MEMORY_CLIENT_NVL3R 0xe5 507#define TEGRA234_MEMORY_CLIENT_NVL3W 0xe6 508#define TEGRA234_MEMORY_CLIENT_NVL4R 0xe7 509#define TEGRA234_MEMORY_CLIENT_NVL4W 0xe8 510/* DLA0ARDA1 read clients */ 511#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9 512/* DLA1ARDA1 read clients */ 513#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea 514/* PVA0RDA1 read clients */ 515#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb 516/* PVA0RDB1 read clients */ 517#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec 518/* PCIE5r1 read clients */ 519#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef 520#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0 521/* ISP read client for Crossbar A */ 522#define TEGRA234_MEMORY_CLIENT_ISPRA1 0xf2 523#define TEGRA234_MEMORY_CLIENT_NVL0RHP 0xf4 524#define TEGRA234_MEMORY_CLIENT_NVL1RHP 0xf5 525#define TEGRA234_MEMORY_CLIENT_NVL2RHP 0xf6 526#define TEGRA234_MEMORY_CLIENT_NVL3RHP 0xf7 527#define TEGRA234_MEMORY_CLIENT_NVL4RHP 0xf8 528/* MSS internal memqual MIU5 read clients */ 529#define TEGRA234_MEMORY_CLIENT_MIU5R 0xfc 530/* MSS internal memqual MIU5 write clients */ 531#define TEGRA234_MEMORY_CLIENT_MIU5W 0xfd 532/* MSS internal memqual MIU6 read clients */ 533#define TEGRA234_MEMORY_CLIENT_MIU6R 0xfe 534/* MSS internal memqual MIU6 write clients */ 535#define TEGRA234_MEMORY_CLIENT_MIU6W 0xff 536#define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123 537#define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124 538 539/* ICC ID's for dummy MC clients used to represent CPU Clusters */ 540#define TEGRA_ICC_MC_CPU_CLUSTER0 1003 541#define TEGRA_ICC_MC_CPU_CLUSTER1 1004 542#define TEGRA_ICC_MC_CPU_CLUSTER2 1005 543 544#endif 545