1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Yongqiang Niu <yongqiang.niu@mediatek.com> 5 */ 6 7#ifndef _DT_BINDINGS_GCE_MT8186_H 8#define _DT_BINDINGS_GCE_MT8186_H 9 10/* assign timeout 0 also means default */ 11#define CMDQ_NO_TIMEOUT 0xffffffff 12#define CMDQ_TIMEOUT_DEFAULT 1000 13 14/* GCE thread priority */ 15#define CMDQ_THR_PRIO_LOWEST 0 16#define CMDQ_THR_PRIO_1 1 17#define CMDQ_THR_PRIO_2 2 18#define CMDQ_THR_PRIO_3 3 19#define CMDQ_THR_PRIO_4 4 20#define CMDQ_THR_PRIO_5 5 21#define CMDQ_THR_PRIO_6 6 22#define CMDQ_THR_PRIO_HIGHEST 7 23 24/* CPR count in 32bit register */ 25#define GCE_CPR_COUNT 1312 26 27/* GCE subsys table */ 28#define SUBSYS_1300XXXX 0 29#define SUBSYS_1400XXXX 1 30#define SUBSYS_1401XXXX 2 31#define SUBSYS_1402XXXX 3 32#define SUBSYS_1502XXXX 4 33#define SUBSYS_1582XXXX 5 34#define SUBSYS_1B00XXXX 6 35#define SUBSYS_1C00XXXX 7 36#define SUBSYS_1C10XXXX 8 37#define SUBSYS_1000XXXX 9 38#define SUBSYS_1001XXXX 10 39#define SUBSYS_1020XXXX 11 40#define SUBSYS_1021XXXX 12 41#define SUBSYS_1022XXXX 13 42#define SUBSYS_1023XXXX 14 43#define SUBSYS_1060XXXX 15 44#define SUBSYS_1602XXXX 16 45#define SUBSYS_1608XXXX 17 46#define SUBSYS_1700XXXX 18 47#define SUBSYS_1701XXXX 19 48#define SUBSYS_1702XXXX 20 49#define SUBSYS_1703XXXX 21 50#define SUBSYS_1706XXXX 22 51#define SUBSYS_1A00XXXX 23 52#define SUBSYS_1A01XXXX 24 53#define SUBSYS_1A02XXXX 25 54#define SUBSYS_1A03XXXX 26 55#define SUBSYS_1A04XXXX 27 56#define SUBSYS_1A05XXXX 28 57#define SUBSYS_1A06XXXX 29 58#define SUBSYS_NO_SUPPORT 99 59 60/* GCE General Purpose Register (GPR) support 61 * Leave note for scenario usage here 62 */ 63/* GCE: write mask */ 64#define GCE_GPR_R00 0x00 65#define GCE_GPR_R01 0x01 66/* MDP: P1: JPEG dest */ 67#define GCE_GPR_R02 0x02 68#define GCE_GPR_R03 0x03 69/* MDP: PQ color */ 70#define GCE_GPR_R04 0x04 71/* MDP: 2D sharpness */ 72#define GCE_GPR_R05 0x05 73/* DISP: poll esd */ 74#define GCE_GPR_R06 0x06 75#define GCE_GPR_R07 0x07 76/* MDP: P4: 2D sharpness dst */ 77#define GCE_GPR_R08 0x08 78#define GCE_GPR_R09 0x09 79/* VCU: poll with timeout for GPR timer */ 80#define GCE_GPR_R10 0x0A 81#define GCE_GPR_R11 0x0B 82/* CMDQ: debug */ 83#define GCE_GPR_R12 0x0C 84#define GCE_GPR_R13 0x0D 85/* CMDQ: P7: debug */ 86#define GCE_GPR_R14 0x0E 87#define GCE_GPR_R15 0x0F 88 89/* GCE hardware events */ 90/* VDEC */ 91#define CMDQ_EVENT_LINE_COUNT_THRESHOLD_INTERRUPT 0 92#define CMDQ_EVENT_VDEC_INT 1 93#define CMDQ_EVENT_VDEC_PAUSE 2 94#define CMDQ_EVENT_VDEC_DEC_ERROR 3 95#define CMDQ_EVENT_MDEC_TIMEOUT 4 96#define CMDQ_EVENT_DRAM_ACCESS_DONE 5 97#define CMDQ_EVENT_INI_FETCH_RDY 6 98#define CMDQ_EVENT_PROCESS_FLAG 7 99#define CMDQ_EVENT_SEARCH_START_CODE_DONE 8 100#define CMDQ_EVENT_REF_REORDER_DONE 9 101#define CMDQ_EVENT_WP_TBLE_DONE 10 102#define CMDQ_EVENT_COUNT_SRAM_CLR_DONE 11 103#define CMDQ_EVENT_GCE_CNT_OP_THRESHOLD 15 104#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_0 16 105#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_1 17 106#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_2 18 107#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_3 19 108#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_4 20 109#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_5 21 110#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_6 22 111#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_7 23 112#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_8 24 113#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_9 25 114#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_10 26 115#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_11 27 116#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_12 28 117#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_13 29 118#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_14 30 119#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_15 31 120#define CMDQ_EVENT_WPE_GCE_FRAME_DONE 32 121 122/* CAM */ 123#define CMDQ_EVENT_ISP_FRAME_DONE_A 65 124#define CMDQ_EVENT_ISP_FRAME_DONE_B 66 125#define CMDQ_EVENT_CAMSV1_PASS1_DONE 70 126#define CMDQ_EVENT_CAMSV2_PASS1_DONE 71 127#define CMDQ_EVENT_CAMSV3_PASS1_DONE 72 128#define CMDQ_EVENT_MRAW_0_PASS1_DONE 73 129#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 75 130#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 76 131#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 77 132#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 78 133#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 79 134#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 80 135#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 81 136#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 82 137#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 83 138#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 84 139#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 85 140#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 86 141#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 87 142#define CMDQ_EVENT_TG_OVRUN_A_INT 88 143#define CMDQ_EVENT_DMA_R1_ERROR_A_INT 89 144#define CMDQ_EVENT_TG_OVRUN_B_INT 90 145#define CMDQ_EVENT_DMA_R1_ERROR_B_INT 91 146#define CMDQ_EVENT_TG_OVRUN_M0_INT 94 147#define CMDQ_EVENT_R1_ERROR_M0_INT 95 148#define CMDQ_EVENT_TG_GRABERR_M0_INT 96 149#define CMDQ_EVENT_TG_GRABERR_A_INT 98 150#define CMDQ_EVENT_CQ_VR_SNAP_A_INT 99 151#define CMDQ_EVENT_TG_GRABERR_B_INT 100 152#define CMDQ_EVENT_CQ_VR_SNAP_B_INT 101 153/* VENC */ 154#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 129 155#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 130 156#define CMDQ_EVENT_JPGENC_CMDQ_DONE 131 157#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 132 158#define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE 133 159#define CMDQ_EVENT_VENC_CMDQ_PPS_DONE 136 160#define CMDQ_EVENT_VENC_CMDQ_SPS_DONE 137 161#define CMDQ_EVENT_VENC_CMDQ_VPS_DONE 138 162/* IPE */ 163#define CMDQ_EVENT_FDVT_DONE 161 164#define CMDQ_EVENT_FE_DONE 162 165#define CMDQ_EVENT_RSC_DONE 163 166#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 164 167#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 165 168/* IMG2 */ 169#define CMDQ_EVENT_GCE_IMG2_EVENT0 193 170#define CMDQ_EVENT_GCE_IMG2_EVENT1 194 171#define CMDQ_EVENT_GCE_IMG2_EVENT2 195 172#define CMDQ_EVENT_GCE_IMG2_EVENT3 196 173#define CMDQ_EVENT_GCE_IMG2_EVENT4 197 174#define CMDQ_EVENT_GCE_IMG2_EVENT5 198 175#define CMDQ_EVENT_GCE_IMG2_EVENT6 199 176#define CMDQ_EVENT_GCE_IMG2_EVENT7 200 177#define CMDQ_EVENT_GCE_IMG2_EVENT8 201 178#define CMDQ_EVENT_GCE_IMG2_EVENT9 202 179#define CMDQ_EVENT_GCE_IMG2_EVENT10 203 180#define CMDQ_EVENT_GCE_IMG2_EVENT11 204 181#define CMDQ_EVENT_GCE_IMG2_EVENT12 205 182#define CMDQ_EVENT_GCE_IMG2_EVENT13 206 183#define CMDQ_EVENT_GCE_IMG2_EVENT14 207 184#define CMDQ_EVENT_GCE_IMG2_EVENT15 208 185#define CMDQ_EVENT_GCE_IMG2_EVENT16 209 186#define CMDQ_EVENT_GCE_IMG2_EVENT17 210 187#define CMDQ_EVENT_GCE_IMG2_EVENT18 211 188#define CMDQ_EVENT_GCE_IMG2_EVENT19 212 189#define CMDQ_EVENT_GCE_IMG2_EVENT20 213 190#define CMDQ_EVENT_GCE_IMG2_EVENT21 214 191#define CMDQ_EVENT_GCE_IMG2_EVENT22 215 192#define CMDQ_EVENT_GCE_IMG2_EVENT23 216 193/* IMG1 */ 194#define CMDQ_EVENT_GCE_IMG1_EVENT0 225 195#define CMDQ_EVENT_GCE_IMG1_EVENT1 226 196#define CMDQ_EVENT_GCE_IMG1_EVENT2 227 197#define CMDQ_EVENT_GCE_IMG1_EVENT3 228 198#define CMDQ_EVENT_GCE_IMG1_EVENT4 229 199#define CMDQ_EVENT_GCE_IMG1_EVENT5 230 200#define CMDQ_EVENT_GCE_IMG1_EVENT6 231 201#define CMDQ_EVENT_GCE_IMG1_EVENT7 232 202#define CMDQ_EVENT_GCE_IMG1_EVENT8 233 203#define CMDQ_EVENT_GCE_IMG1_EVENT9 234 204#define CMDQ_EVENT_GCE_IMG1_EVENT10 235 205#define CMDQ_EVENT_GCE_IMG1_EVENT11 236 206#define CMDQ_EVENT_GCE_IMG1_EVENT12 237 207#define CMDQ_EVENT_GCE_IMG1_EVENT13 238 208#define CMDQ_EVENT_GCE_IMG1_EVENT14 239 209#define CMDQ_EVENT_GCE_IMG1_EVENT15 240 210#define CMDQ_EVENT_GCE_IMG1_EVENT16 241 211#define CMDQ_EVENT_GCE_IMG1_EVENT17 242 212#define CMDQ_EVENT_GCE_IMG1_EVENT18 243 213#define CMDQ_EVENT_GCE_IMG1_EVENT19 244 214#define CMDQ_EVENT_GCE_IMG1_EVENT20 245 215#define CMDQ_EVENT_GCE_IMG1_EVENT21 246 216#define CMDQ_EVENT_GCE_IMG1_EVENT22 247 217#define CMDQ_EVENT_GCE_IMG1_EVENT23 248 218/* MDP */ 219#define CMDQ_EVENT_MDP_RDMA0_SOF 256 220#define CMDQ_EVENT_MDP_RDMA1_SOF 257 221#define CMDQ_EVENT_MDP_AAL0_SOF 258 222#define CMDQ_EVENT_MDP_AAL1_SOF 259 223#define CMDQ_EVENT_MDP_HDR0_SOF 260 224#define CMDQ_EVENT_MDP_RSZ0_SOF 261 225#define CMDQ_EVENT_MDP_RSZ1_SOF 262 226#define CMDQ_EVENT_MDP_WROT0_SOF 263 227#define CMDQ_EVENT_MDP_WROT1_SOF 264 228#define CMDQ_EVENT_MDP_TDSHP0_SOF 265 229#define CMDQ_EVENT_MDP_TDSHP1_SOF 266 230#define CMDQ_EVENT_IMG_DL_RELAY0_SOF 267 231#define CMDQ_EVENT_IMG_DL_RELAY1_SOF 268 232#define CMDQ_EVENT_MDP_COLOR0_SOF 269 233#define CMDQ_EVENT_MDP_WROT3_FRAME_DONE 288 234#define CMDQ_EVENT_MDP_WROT2_FRAME_DONE 289 235#define CMDQ_EVENT_MDP_WROT1_FRAME_DONE 290 236#define CMDQ_EVENT_MDP_WROT0_FRAME_DONE 291 237#define CMDQ_EVENT_MDP_TDSHP3_FRAME_DONE 292 238#define CMDQ_EVENT_MDP_TDSHP2_FRAME_DONE 293 239#define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE 294 240#define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE 295 241#define CMDQ_EVENT_MDP_RSZ3_FRAME_DONE 296 242#define CMDQ_EVENT_MDP_RSZ2_FRAME_DONE 297 243#define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE 298 244#define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE 299 245#define CMDQ_EVENT_MDP_RDMA3_FRAME_DONE 300 246#define CMDQ_EVENT_MDP_RDMA2_FRAME_DONE 301 247#define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE 302 248#define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE 303 249#define CMDQ_EVENT_MDP_HDR1_FRAME_DONE 304 250#define CMDQ_EVENT_MDP_HDR0_FRAME_DONE 305 251#define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE 306 252#define CMDQ_EVENT_MDP_AAL3_FRAME_DONE 307 253#define CMDQ_EVENT_MDP_AAL2_FRAME_DONE 308 254#define CMDQ_EVENT_MDP_AAL1_FRAME_DONE 309 255#define CMDQ_EVENT_MDP_AAL0_FRAME_DONE 310 256#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0 320 257#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1 321 258#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2 322 259#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3 323 260#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4 324 261#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5 325 262#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6 326 263#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7 327 264#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8 328 265#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 329 266#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10 330 267#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11 331 268#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12 332 269#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13 333 270#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14 334 271#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15 335 272#define CMDQ_EVENT_MDP_WROT3_SW_RST_DONE_ENG_EVENT 336 273#define CMDQ_EVENT_MDP_WROT2_SW_RST_DONE_ENG_EVENT 337 274#define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT 338 275#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT 339 276#define CMDQ_EVENT_MDP_RDMA3_SW_RST_DONE_ENG_EVENT 340 277#define CMDQ_EVENT_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 341 278#define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 342 279#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 343 280/* DISP */ 281#define CMDQ_EVENT_DISP_OVL0_SOF 384 282#define CMDQ_EVENT_DISP_OVL0_2L_SOF 385 283#define CMDQ_EVENT_DISP_RDMA0_SOF 386 284#define CMDQ_EVENT_DISP_RSZ0_SOF 387 285#define CMDQ_EVENT_DISP_COLOR0_SOF 388 286#define CMDQ_EVENT_DISP_CCORR0_SOF 389 287#define CMDQ_EVENT_DISP_CCORR1_SOF 390 288#define CMDQ_EVENT_DISP_AAL0_SOF 391 289#define CMDQ_EVENT_DISP_GAMMA0_SOF 392 290#define CMDQ_EVENT_DISP_POSTMASK0_SOF 393 291#define CMDQ_EVENT_DISP_DITHER0_SOF 394 292#define CMDQ_EVENT_DISP_CM0_SOF 395 293#define CMDQ_EVENT_DISP_SPR0_SOF 396 294#define CMDQ_EVENT_DISP_DSC_WRAP0_SOF 397 295#define CMDQ_EVENT_DSI0_SOF 398 296#define CMDQ_EVENT_DISP_WDMA0_SOF 399 297#define CMDQ_EVENT_DISP_PWM0_SOF 400 298#define CMDQ_EVENT_DSI0_FRAME_DONE 410 299#define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE 411 300#define CMDQ_EVENT_DISP_SPR0_FRAME_DONE 412 301#define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE 413 302#define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE 414 303#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 415 304#define CMDQ_EVENT_DISP_OVL0_FRAME_DONE 416 305#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE 417 306#define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE 418 307#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_DONE 420 308#define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE 421 309#define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE 422 310#define CMDQ_EVENT_DISP_CM0_FRAME_DONE 423 311#define CMDQ_EVENT_DISP_CCORR1_FRAME_DONE 424 312#define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE 425 313#define CMDQ_EVENT_DISP_AAL0_FRAME_DONE 426 314#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0 434 315#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1 435 316#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_2 436 317#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_3 437 318#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_4 438 319#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_5 439 320#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_6 440 321#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_7 441 322#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_8 442 323#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_9 443 324#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_10 444 325#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_11 445 326#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_12 446 327#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_13 447 328#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_14 448 329#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_15 449 330#define CMDQ_EVENT_DSI0_TE_ENG_EVENT 450 331#define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT 451 332#define CMDQ_EVENT_DSI0_DONE_ENG_EVENT 452 333#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 453 334#define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT 454 335#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG_EVENT 455 336#define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVENT 456 337#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_EVENT 457 338#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0 458 339#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1 459 340#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2 460 341#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3 461 342#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4 462 343#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5 463 344#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6 464 345#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7 465 346#define CMDQ_EVENT_OUT_EVENT_0 898 347 348/* CMDQ sw tokens 349 * Following definitions are gce sw token which may use by clients 350 * event operation API. 351 * Note that token 512 to 639 may set secure 352 */ 353 354/* end of hw event and begin of sw token */ 355#define CMDQ_MAX_HW_EVENT 512 356 357/* Config thread notify trigger thread */ 358#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640 359/* Trigger thread notify config thread */ 360#define CMDQ_SYNC_TOKEN_STREAM_EOF 641 361/* Block Trigger thread until the ESD check finishes. */ 362#define CMDQ_SYNC_TOKEN_ESD_EOF 642 363#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643 364/* check CABC setup finish */ 365#define CMDQ_SYNC_TOKEN_CABC_EOF 644 366 367/* Notify normal CMDQ there are some secure task done 368 * MUST NOT CHANGE, this token sync with secure world 369 */ 370#define CMDQ_SYNC_SECURE_THR_EOF 647 371 372/* CMDQ use sw token */ 373#define CMDQ_SYNC_TOKEN_USER_0 649 374#define CMDQ_SYNC_TOKEN_USER_1 650 375#define CMDQ_SYNC_TOKEN_POLL_MONITOR 651 376#define CMDQ_SYNC_TOKEN_TPR_LOCK 652 377 378/* ISP sw token */ 379#define CMDQ_SYNC_TOKEN_MSS 665 380#define CMDQ_SYNC_TOKEN_MSF 666 381 382/* DISP sw token */ 383#define CMDQ_SYNC_TOKEN_SODI 671 384 385/* GPR access tokens (for register backup) 386 * There are 15 32-bit GPR, 3 GPR form a set 387 * (64-bit for address, 32-bit for value) 388 * MUST NOT CHANGE, these tokens sync with MDP 389 */ 390#define CMDQ_SYNC_TOKEN_GPR_SET_0 700 391#define CMDQ_SYNC_TOKEN_GPR_SET_1 701 392#define CMDQ_SYNC_TOKEN_GPR_SET_2 702 393#define CMDQ_SYNC_TOKEN_GPR_SET_3 703 394#define CMDQ_SYNC_TOKEN_GPR_SET_4 704 395 396/* Resource lock event to control resource in GCE thread */ 397#define CMDQ_SYNC_RESOURCE_WROT0 710 398#define CMDQ_SYNC_RESOURCE_WROT1 711 399 400/* event for gpr timer, used in sleep and poll with timeout */ 401#define CMDQ_TOKEN_GPR_TIMER_R0 994 402#define CMDQ_TOKEN_GPR_TIMER_R1 995 403#define CMDQ_TOKEN_GPR_TIMER_R2 996 404#define CMDQ_TOKEN_GPR_TIMER_R3 997 405#define CMDQ_TOKEN_GPR_TIMER_R4 998 406#define CMDQ_TOKEN_GPR_TIMER_R5 999 407#define CMDQ_TOKEN_GPR_TIMER_R6 1000 408#define CMDQ_TOKEN_GPR_TIMER_R7 1001 409#define CMDQ_TOKEN_GPR_TIMER_R8 1002 410#define CMDQ_TOKEN_GPR_TIMER_R9 1003 411#define CMDQ_TOKEN_GPR_TIMER_R10 1004 412#define CMDQ_TOKEN_GPR_TIMER_R11 1005 413#define CMDQ_TOKEN_GPR_TIMER_R12 1006 414#define CMDQ_TOKEN_GPR_TIMER_R13 1007 415#define CMDQ_TOKEN_GPR_TIMER_R14 1008 416#define CMDQ_TOKEN_GPR_TIMER_R15 1009 417 418#define CMDQ_EVENT_MAX 0x3FF 419/* CMDQ sw tokens END */ 420 421#endif 422