1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * This header provides macros for JZ4775 DMA bindings.
4 *
5 * Copyright (c) 2020 ��������� (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
6 */
7
8#ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__
9#define __DT_BINDINGS_DMA_JZ4775_DMA_H__
10
11/*
12 * Request type numbers for the JZ4775 DMA controller (written to the DRTn
13 * register for the channel).
14 */
15#define JZ4775_DMA_I2S0_TX	0x6
16#define JZ4775_DMA_I2S0_RX	0x7
17#define JZ4775_DMA_AUTO		0x8
18#define JZ4775_DMA_SADC_RX	0x9
19#define JZ4775_DMA_UART3_TX	0x0e
20#define JZ4775_DMA_UART3_RX	0x0f
21#define JZ4775_DMA_UART2_TX	0x10
22#define JZ4775_DMA_UART2_RX	0x11
23#define JZ4775_DMA_UART1_TX	0x12
24#define JZ4775_DMA_UART1_RX	0x13
25#define JZ4775_DMA_UART0_TX	0x14
26#define JZ4775_DMA_UART0_RX	0x15
27#define JZ4775_DMA_SSI0_TX	0x16
28#define JZ4775_DMA_SSI0_RX	0x17
29#define JZ4775_DMA_MSC0_TX	0x1a
30#define JZ4775_DMA_MSC0_RX	0x1b
31#define JZ4775_DMA_MSC1_TX	0x1c
32#define JZ4775_DMA_MSC1_RX	0x1d
33#define JZ4775_DMA_MSC2_TX	0x1e
34#define JZ4775_DMA_MSC2_RX	0x1f
35#define JZ4775_DMA_PCM0_TX	0x20
36#define JZ4775_DMA_PCM0_RX	0x21
37#define JZ4775_DMA_SMB0_TX	0x24
38#define JZ4775_DMA_SMB0_RX	0x25
39#define JZ4775_DMA_SMB1_TX	0x26
40#define JZ4775_DMA_SMB1_RX	0x27
41#define JZ4775_DMA_SMB2_TX	0x28
42#define JZ4775_DMA_SMB2_RX	0x29
43
44#endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */
45