1/* SPDX-License-Identifier: GPL-2.0+
2 *
3 * Copyright (C) 2015 Renesas Electronics Corp.
4 */
5#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
6#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
10/* r8a7795 CPG Core Clocks */
11#define R8A7795_CLK_Z			0
12#define R8A7795_CLK_Z2			1
13#define R8A7795_CLK_ZR			2
14#define R8A7795_CLK_ZG			3
15#define R8A7795_CLK_ZTR			4
16#define R8A7795_CLK_ZTRD2		5
17#define R8A7795_CLK_ZT			6
18#define R8A7795_CLK_ZX			7
19#define R8A7795_CLK_S0D1		8
20#define R8A7795_CLK_S0D4		9
21#define R8A7795_CLK_S1D1		10
22#define R8A7795_CLK_S1D2		11
23#define R8A7795_CLK_S1D4		12
24#define R8A7795_CLK_S2D1		13
25#define R8A7795_CLK_S2D2		14
26#define R8A7795_CLK_S2D4		15
27#define R8A7795_CLK_S3D1		16
28#define R8A7795_CLK_S3D2		17
29#define R8A7795_CLK_S3D4		18
30#define R8A7795_CLK_LB			19
31#define R8A7795_CLK_CL			20
32#define R8A7795_CLK_ZB3			21
33#define R8A7795_CLK_ZB3D2		22
34#define R8A7795_CLK_CR			23
35#define R8A7795_CLK_CRD2		24
36#define R8A7795_CLK_SD0H		25
37#define R8A7795_CLK_SD0			26
38#define R8A7795_CLK_SD1H		27
39#define R8A7795_CLK_SD1			28
40#define R8A7795_CLK_SD2H		29
41#define R8A7795_CLK_SD2			30
42#define R8A7795_CLK_SD3H		31
43#define R8A7795_CLK_SD3			32
44#define R8A7795_CLK_SSP2		33
45#define R8A7795_CLK_SSP1		34
46#define R8A7795_CLK_SSPRS		35
47#define R8A7795_CLK_RPC			36
48#define R8A7795_CLK_RPCD2		37
49#define R8A7795_CLK_MSO			38
50#define R8A7795_CLK_CANFD		39
51#define R8A7795_CLK_HDMI		40
52#define R8A7795_CLK_CSI0		41
53/* CLK_CSIREF was removed */
54#define R8A7795_CLK_CP			43
55#define R8A7795_CLK_CPEX		44
56#define R8A7795_CLK_R			45
57#define R8A7795_CLK_OSC			46
58
59/* r8a7795 ES2.0 CPG Core Clocks */
60#define R8A7795_CLK_S0D2		47
61#define R8A7795_CLK_S0D3		48
62#define R8A7795_CLK_S0D6		49
63#define R8A7795_CLK_S0D8		50
64#define R8A7795_CLK_S0D12		51
65
66#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
67