1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2/* 3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. 4 */ 5 6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6115_H 7#define _DT_BINDINGS_CLK_QCOM_GCC_SM6115_H 8 9/* GCC clocks */ 10#define GPLL0 0 11#define GPLL0_OUT_AUX2 1 12#define GPLL0_OUT_MAIN 2 13#define GPLL10 3 14#define GPLL10_OUT_MAIN 4 15#define GPLL11 5 16#define GPLL11_OUT_MAIN 6 17#define GPLL3 7 18#define GPLL4 8 19#define GPLL4_OUT_MAIN 9 20#define GPLL6 10 21#define GPLL6_OUT_MAIN 11 22#define GPLL7 12 23#define GPLL7_OUT_MAIN 13 24#define GPLL8 14 25#define GPLL8_OUT_MAIN 15 26#define GPLL9 16 27#define GPLL9_OUT_MAIN 17 28#define GCC_CAMSS_CSI0PHYTIMER_CLK 18 29#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 19 30#define GCC_CAMSS_CSI1PHYTIMER_CLK 20 31#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 21 32#define GCC_CAMSS_CSI2PHYTIMER_CLK 22 33#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 23 34#define GCC_CAMSS_MCLK0_CLK 24 35#define GCC_CAMSS_MCLK0_CLK_SRC 25 36#define GCC_CAMSS_MCLK1_CLK 26 37#define GCC_CAMSS_MCLK1_CLK_SRC 27 38#define GCC_CAMSS_MCLK2_CLK 28 39#define GCC_CAMSS_MCLK2_CLK_SRC 29 40#define GCC_CAMSS_MCLK3_CLK 30 41#define GCC_CAMSS_MCLK3_CLK_SRC 31 42#define GCC_CAMSS_NRT_AXI_CLK 32 43#define GCC_CAMSS_OPE_AHB_CLK 33 44#define GCC_CAMSS_OPE_AHB_CLK_SRC 34 45#define GCC_CAMSS_OPE_CLK 35 46#define GCC_CAMSS_OPE_CLK_SRC 36 47#define GCC_CAMSS_RT_AXI_CLK 37 48#define GCC_CAMSS_TFE_0_CLK 38 49#define GCC_CAMSS_TFE_0_CLK_SRC 39 50#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 40 51#define GCC_CAMSS_TFE_0_CSID_CLK 41 52#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 42 53#define GCC_CAMSS_TFE_1_CLK 43 54#define GCC_CAMSS_TFE_1_CLK_SRC 44 55#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 45 56#define GCC_CAMSS_TFE_1_CSID_CLK 46 57#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 47 58#define GCC_CAMSS_TFE_2_CLK 48 59#define GCC_CAMSS_TFE_2_CLK_SRC 49 60#define GCC_CAMSS_TFE_2_CPHY_RX_CLK 50 61#define GCC_CAMSS_TFE_2_CSID_CLK 51 62#define GCC_CAMSS_TFE_2_CSID_CLK_SRC 52 63#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 53 64#define GCC_CAMSS_TOP_AHB_CLK 54 65#define GCC_CAMSS_TOP_AHB_CLK_SRC 55 66#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 56 67#define GCC_CPUSS_AHB_CLK 57 68#define GCC_CPUSS_GNOC_CLK 60 69#define GCC_DISP_AHB_CLK 61 70#define GCC_DISP_GPLL0_DIV_CLK_SRC 62 71#define GCC_DISP_HF_AXI_CLK 63 72#define GCC_DISP_THROTTLE_CORE_CLK 64 73#define GCC_DISP_XO_CLK 65 74#define GCC_GP1_CLK 66 75#define GCC_GP1_CLK_SRC 67 76#define GCC_GP2_CLK 68 77#define GCC_GP2_CLK_SRC 69 78#define GCC_GP3_CLK 70 79#define GCC_GP3_CLK_SRC 71 80#define GCC_GPU_CFG_AHB_CLK 72 81#define GCC_GPU_GPLL0_CLK_SRC 73 82#define GCC_GPU_GPLL0_DIV_CLK_SRC 74 83#define GCC_GPU_IREF_CLK 75 84#define GCC_GPU_MEMNOC_GFX_CLK 76 85#define GCC_GPU_SNOC_DVM_GFX_CLK 77 86#define GCC_GPU_THROTTLE_CORE_CLK 78 87#define GCC_GPU_THROTTLE_XO_CLK 79 88#define GCC_PDM2_CLK 80 89#define GCC_PDM2_CLK_SRC 81 90#define GCC_PDM_AHB_CLK 82 91#define GCC_PDM_XO4_CLK 83 92#define GCC_PRNG_AHB_CLK 84 93#define GCC_QMIP_CAMERA_NRT_AHB_CLK 85 94#define GCC_QMIP_CAMERA_RT_AHB_CLK 86 95#define GCC_QMIP_DISP_AHB_CLK 87 96#define GCC_QMIP_GPU_CFG_AHB_CLK 88 97#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 89 98#define GCC_QUPV3_WRAP0_CORE_2X_CLK 90 99#define GCC_QUPV3_WRAP0_CORE_CLK 91 100#define GCC_QUPV3_WRAP0_S0_CLK 92 101#define GCC_QUPV3_WRAP0_S0_CLK_SRC 93 102#define GCC_QUPV3_WRAP0_S1_CLK 94 103#define GCC_QUPV3_WRAP0_S1_CLK_SRC 95 104#define GCC_QUPV3_WRAP0_S2_CLK 96 105#define GCC_QUPV3_WRAP0_S2_CLK_SRC 97 106#define GCC_QUPV3_WRAP0_S3_CLK 98 107#define GCC_QUPV3_WRAP0_S3_CLK_SRC 99 108#define GCC_QUPV3_WRAP0_S4_CLK 100 109#define GCC_QUPV3_WRAP0_S4_CLK_SRC 101 110#define GCC_QUPV3_WRAP0_S5_CLK 102 111#define GCC_QUPV3_WRAP0_S5_CLK_SRC 103 112#define GCC_QUPV3_WRAP_0_M_AHB_CLK 104 113#define GCC_QUPV3_WRAP_0_S_AHB_CLK 105 114#define GCC_SDCC1_AHB_CLK 106 115#define GCC_SDCC1_APPS_CLK 107 116#define GCC_SDCC1_APPS_CLK_SRC 108 117#define GCC_SDCC1_ICE_CORE_CLK 109 118#define GCC_SDCC1_ICE_CORE_CLK_SRC 110 119#define GCC_SDCC2_AHB_CLK 111 120#define GCC_SDCC2_APPS_CLK 112 121#define GCC_SDCC2_APPS_CLK_SRC 113 122#define GCC_SYS_NOC_CPUSS_AHB_CLK 114 123#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 115 124#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 116 125#define GCC_UFS_PHY_AHB_CLK 117 126#define GCC_UFS_PHY_AXI_CLK 118 127#define GCC_UFS_PHY_AXI_CLK_SRC 119 128#define GCC_UFS_PHY_ICE_CORE_CLK 120 129#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 121 130#define GCC_UFS_PHY_PHY_AUX_CLK 122 131#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 123 132#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 124 133#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 125 134#define GCC_UFS_PHY_UNIPRO_CORE_CLK 126 135#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 127 136#define GCC_USB30_PRIM_MASTER_CLK 128 137#define GCC_USB30_PRIM_MASTER_CLK_SRC 129 138#define GCC_USB30_PRIM_MOCK_UTMI_CLK 130 139#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 131 140#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 132 141#define GCC_USB30_PRIM_SLEEP_CLK 133 142#define GCC_USB3_PRIM_CLKREF_CLK 134 143#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 135 144#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 136 145#define GCC_USB3_PRIM_PHY_PIPE_CLK 137 146#define GCC_VCODEC0_AXI_CLK 138 147#define GCC_VENUS_AHB_CLK 139 148#define GCC_VENUS_CTL_AXI_CLK 140 149#define GCC_VIDEO_AHB_CLK 141 150#define GCC_VIDEO_AXI0_CLK 142 151#define GCC_VIDEO_THROTTLE_CORE_CLK 143 152#define GCC_VIDEO_VCODEC0_SYS_CLK 144 153#define GCC_VIDEO_VENUS_CLK_SRC 145 154#define GCC_VIDEO_VENUS_CTL_CLK 146 155#define GCC_VIDEO_XO_CLK 147 156#define GCC_AHB2PHY_CSI_CLK 148 157#define GCC_AHB2PHY_USB_CLK 149 158#define GCC_BIMC_GPU_AXI_CLK 150 159#define GCC_BOOT_ROM_AHB_CLK 151 160#define GCC_CAM_THROTTLE_NRT_CLK 152 161#define GCC_CAM_THROTTLE_RT_CLK 153 162#define GCC_CAMERA_AHB_CLK 154 163#define GCC_CAMERA_XO_CLK 155 164#define GCC_CAMSS_AXI_CLK 156 165#define GCC_CAMSS_AXI_CLK_SRC 157 166#define GCC_CAMSS_CAMNOC_ATB_CLK 158 167#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 159 168#define GCC_CAMSS_CCI_0_CLK 160 169#define GCC_CAMSS_CCI_CLK_SRC 161 170#define GCC_CAMSS_CPHY_0_CLK 162 171#define GCC_CAMSS_CPHY_1_CLK 163 172#define GCC_CAMSS_CPHY_2_CLK 164 173#define GCC_UFS_CLKREF_CLK 165 174#define GCC_DISP_GPLL0_CLK_SRC 166 175 176/* GCC resets */ 177#define GCC_QUSB2PHY_PRIM_BCR 0 178#define GCC_QUSB2PHY_SEC_BCR 1 179#define GCC_SDCC1_BCR 2 180#define GCC_UFS_PHY_BCR 3 181#define GCC_USB30_PRIM_BCR 4 182#define GCC_USB_PHY_CFG_AHB2PHY_BCR 5 183#define GCC_VCODEC0_BCR 6 184#define GCC_VENUS_BCR 7 185#define GCC_VIDEO_INTERFACE_BCR 8 186#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 9 187#define GCC_USB3_PHY_PRIM_SP0_BCR 10 188#define GCC_SDCC2_BCR 11 189 190/* Indexes for GDSCs */ 191#define GCC_CAMSS_TOP_GDSC 0 192#define GCC_UFS_PHY_GDSC 1 193#define GCC_USB30_PRIM_GDSC 2 194#define GCC_VCODEC0_GDSC 3 195#define GCC_VENUS_GDSC 4 196#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 5 197#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 6 198#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 7 199#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 8 200 201#endif 202