1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/*
3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals
4 *
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_mcu {
9	mcu_conf: scm-conf@40f00000 {
10		compatible = "syscon", "simple-mfd";
11		reg = <0x0 0x40f00000 0x0 0x20000>;
12		#address-cells = <1>;
13		#size-cells = <1>;
14		ranges = <0x0 0x0 0x40f00000 0x20000>;
15
16		phy_gmii_sel: phy@4040 {
17			compatible = "ti,am654-phy-gmii-sel";
18			reg = <0x4040 0x4>;
19			#phy-cells = <1>;
20		};
21	};
22
23	/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
24	mcu_timerio_input: pinctrl@40f04200 {
25		compatible = "pinctrl-single";
26		reg = <0x0 0x40f04200 0x0 0x10>;
27		#pinctrl-cells = <1>;
28		pinctrl-single,register-width = <32>;
29		pinctrl-single,function-mask = <0x00000101>;
30	};
31
32	/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
33	mcu_timerio_output: pinctrl@40f04280 {
34		compatible = "pinctrl-single";
35		reg = <0x0 0x40f04280 0x0 0x8>;
36		#pinctrl-cells = <1>;
37		pinctrl-single,register-width = <32>;
38		pinctrl-single,function-mask = <0x00000003>;
39	};
40
41	mcu_uart0: serial@40a00000 {
42		compatible = "ti,am654-uart";
43		reg = <0x00 0x40a00000 0x00 0x100>;
44		interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
45		clock-frequency = <96000000>;
46		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
47		status = "disabled";
48	};
49
50	mcu_ram: sram@41c00000 {
51		compatible = "mmio-sram";
52		reg = <0x00 0x41c00000 0x00 0x80000>;
53		ranges = <0x0 0x00 0x41c00000 0x80000>;
54		#address-cells = <1>;
55		#size-cells = <1>;
56	};
57
58	mcu_i2c0: i2c@40b00000 {
59		compatible = "ti,am654-i2c", "ti,omap4-i2c";
60		reg = <0x0 0x40b00000 0x0 0x100>;
61		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
62		#address-cells = <1>;
63		#size-cells = <0>;
64		clock-names = "fck";
65		clocks = <&k3_clks 114 1>;
66		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
67		status = "disabled";
68	};
69
70	mcu_spi0: spi@40300000 {
71		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
72		reg = <0x0 0x40300000 0x0 0x400>;
73		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
74		clocks = <&k3_clks 142 1>;
75		power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
76		#address-cells = <1>;
77		#size-cells = <0>;
78		status = "disabled";
79	};
80
81	mcu_spi1: spi@40310000 {
82		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
83		reg = <0x0 0x40310000 0x0 0x400>;
84		interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
85		clocks = <&k3_clks 143 1>;
86		power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
87		#address-cells = <1>;
88		#size-cells = <0>;
89		status = "disabled";
90	};
91
92	mcu_spi2: spi@40320000 {
93		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
94		reg = <0x0 0x40320000 0x0 0x400>;
95		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
96		clocks = <&k3_clks 144 1>;
97		power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
98		#address-cells = <1>;
99		#size-cells = <0>;
100		status = "disabled";
101	};
102
103	tscadc0: tscadc@40200000 {
104		compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
105		reg = <0x0 0x40200000 0x0 0x1000>;
106		interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
107		clocks = <&k3_clks 0 2>;
108		assigned-clocks = <&k3_clks 0 2>;
109		assigned-clock-rates = <60000000>;
110		clock-names = "fck";
111		dmas = <&mcu_udmap 0x7100>,
112			<&mcu_udmap 0x7101 >;
113		dma-names = "fifo0", "fifo1";
114		status = "disabled";
115
116		adc {
117			#io-channel-cells = <1>;
118			compatible = "ti,am654-adc", "ti,am3359-adc";
119		};
120	};
121
122	tscadc1: tscadc@40210000 {
123		compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
124		reg = <0x0 0x40210000 0x0 0x1000>;
125		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
126		clocks = <&k3_clks 1 2>;
127		assigned-clocks = <&k3_clks 1 2>;
128		assigned-clock-rates = <60000000>;
129		clock-names = "fck";
130		dmas = <&mcu_udmap 0x7102>,
131			<&mcu_udmap 0x7103>;
132		dma-names = "fifo0", "fifo1";
133		status = "disabled";
134
135		adc {
136			#io-channel-cells = <1>;
137			compatible = "ti,am654-adc", "ti,am3359-adc";
138		};
139	};
140
141	/*
142	 * The MCU domain timer interrupts are routed only to the ESM module,
143	 * and not currently available for Linux. The MCU domain timers are
144	 * of limited use without interrupts, and likely reserved by the ESM.
145	 */
146	mcu_timer0: timer@40400000 {
147		compatible = "ti,am654-timer";
148		reg = <0x00 0x40400000 0x00 0x400>;
149		clocks = <&k3_clks 35 0>;
150		clock-names = "fck";
151		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
152		ti,timer-pwm;
153		status = "reserved";
154	};
155
156	mcu_timer1: timer@40410000 {
157		compatible = "ti,am654-timer";
158		reg = <0x00 0x40410000 0x00 0x400>;
159		clocks = <&k3_clks 36 0>;
160		clock-names = "fck";
161		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
162		ti,timer-pwm;
163		status = "reserved";
164	};
165
166	mcu_timer2: timer@40420000 {
167		compatible = "ti,am654-timer";
168		reg = <0x00 0x40420000 0x00 0x400>;
169		clocks = <&k3_clks 37 0>;
170		clock-names = "fck";
171		power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
172		ti,timer-pwm;
173		status = "reserved";
174	};
175
176	mcu_timer3: timer@40430000 {
177		compatible = "ti,am654-timer";
178		reg = <0x00 0x40430000 0x00 0x400>;
179		clocks = <&k3_clks 38 0>;
180		clock-names = "fck";
181		power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
182		ti,timer-pwm;
183		status = "reserved";
184	};
185
186	mcu_navss: bus@28380000 {
187		compatible = "simple-bus";
188		#address-cells = <2>;
189		#size-cells = <2>;
190		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
191		dma-coherent;
192		dma-ranges;
193
194		ti,sci-dev-id = <119>;
195
196		mcu_ringacc: ringacc@2b800000 {
197			compatible = "ti,am654-navss-ringacc";
198			reg = <0x0 0x2b800000 0x0 0x400000>,
199			      <0x0 0x2b000000 0x0 0x400000>,
200			      <0x0 0x28590000 0x0 0x100>,
201			      <0x0 0x2a500000 0x0 0x40000>,
202			      <0x0 0x28440000 0x0 0x40000>;
203			reg-names = "rt", "fifos", "proxy_gcfg",
204				    "proxy_target", "cfg";
205			ti,num-rings = <286>;
206			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
207			ti,sci = <&dmsc>;
208			ti,sci-dev-id = <195>;
209			msi-parent = <&inta_main_udmass>;
210		};
211
212		mcu_udmap: dma-controller@285c0000 {
213			compatible = "ti,am654-navss-mcu-udmap";
214			reg = <0x0 0x285c0000 0x0 0x100>,
215			      <0x0 0x2a800000 0x0 0x40000>,
216			      <0x0 0x2aa00000 0x0 0x40000>,
217			      <0x0 0x284a0000 0x0 0x4000>,
218			      <0x0 0x284c0000 0x0 0x4000>,
219			      <0x0 0x28400000 0x0 0x2000>;
220			reg-names = "gcfg", "rchanrt", "tchanrt",
221				    "tchan", "rchan", "rflow";
222			msi-parent = <&inta_main_udmass>;
223			#dma-cells = <1>;
224
225			ti,sci = <&dmsc>;
226			ti,sci-dev-id = <194>;
227			ti,ringacc = <&mcu_ringacc>;
228
229			ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
230						<0xd>; /* TX_CHAN */
231			ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
232						<0xa>; /* RX_CHAN */
233			ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
234		};
235	};
236
237	secure_proxy_mcu: mailbox@2a480000 {
238		compatible = "ti,am654-secure-proxy";
239		#mbox-cells = <1>;
240		reg-names = "target_data", "rt", "scfg";
241		reg = <0x0 0x2a480000 0x0 0x80000>,
242		      <0x0 0x2a380000 0x0 0x80000>,
243		      <0x0 0x2a400000 0x0 0x80000>;
244		/*
245		 * Marked Disabled:
246		 * Node is incomplete as it is meant for bootloaders and
247		 * firmware on non-MPU processors
248		 */
249		status = "disabled";
250	};
251
252	m_can0: can@40528000 {
253		compatible = "bosch,m_can";
254		reg = <0x0 0x40528000 0x0 0x400>,
255		      <0x0 0x40500000 0x0 0x4400>;
256		reg-names = "m_can", "message_ram";
257		power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
258		clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
259		clock-names = "hclk", "cclk";
260		interrupt-parent = <&gic500>;
261		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
262			     <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
263		interrupt-names = "int0", "int1";
264		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
265		status = "disabled";
266	};
267
268	m_can1: can@40568000 {
269		compatible = "bosch,m_can";
270		reg = <0x0 0x40568000 0x0 0x400>,
271		      <0x0 0x40540000 0x0 0x4400>;
272		reg-names = "m_can", "message_ram";
273		power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
274		clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
275		clock-names = "hclk", "cclk";
276		interrupt-parent = <&gic500>;
277		interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
278			     <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
279		interrupt-names = "int0", "int1";
280		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
281		status = "disabled";
282	};
283
284	fss: bus@47000000 {
285		compatible = "simple-bus";
286		#address-cells = <2>;
287		#size-cells = <2>;
288		ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */
289			 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
290			 <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */
291			 <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* OSPI0 Memory */
292			 <0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */
293
294		ospi0: spi@47040000 {
295			compatible = "ti,am654-ospi", "cdns,qspi-nor";
296			reg = <0x0 0x47040000 0x0 0x100>,
297				<0x5 0x00000000 0x1 0x0000000>;
298			interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
299			cdns,fifo-depth = <256>;
300			cdns,fifo-width = <4>;
301			cdns,trigger-address = <0x0>;
302			clocks = <&k3_clks 248 0>;
303			assigned-clocks = <&k3_clks 248 0>;
304			assigned-clock-parents = <&k3_clks 248 2>;
305			assigned-clock-rates = <166666666>;
306			power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
307			#address-cells = <1>;
308			#size-cells = <0>;
309			status = "disabled";
310		};
311
312		ospi1: spi@47050000 {
313			compatible = "ti,am654-ospi", "cdns,qspi-nor";
314			reg = <0x0 0x47050000 0x0 0x100>,
315				<0x7 0x00000000 0x1 0x00000000>;
316			interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
317			cdns,fifo-depth = <256>;
318			cdns,fifo-width = <4>;
319			cdns,trigger-address = <0x0>;
320			clocks = <&k3_clks 249 6>;
321			power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
322			#address-cells = <1>;
323			#size-cells = <0>;
324			status = "disabled";
325		};
326	};
327
328	mcu_cpsw: ethernet@46000000 {
329		compatible = "ti,am654-cpsw-nuss";
330		#address-cells = <2>;
331		#size-cells = <2>;
332		reg = <0x0 0x46000000 0x0 0x200000>;
333		reg-names = "cpsw_nuss";
334		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
335		dma-coherent;
336		clocks = <&k3_clks 5 10>;
337		clock-names = "fck";
338		power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
339
340		dmas = <&mcu_udmap 0xf000>,
341		       <&mcu_udmap 0xf001>,
342		       <&mcu_udmap 0xf002>,
343		       <&mcu_udmap 0xf003>,
344		       <&mcu_udmap 0xf004>,
345		       <&mcu_udmap 0xf005>,
346		       <&mcu_udmap 0xf006>,
347		       <&mcu_udmap 0xf007>,
348		       <&mcu_udmap 0x7000>;
349		dma-names = "tx0", "tx1", "tx2", "tx3",
350			    "tx4", "tx5", "tx6", "tx7",
351			    "rx";
352
353		ethernet-ports {
354			#address-cells = <1>;
355			#size-cells = <0>;
356
357			cpsw_port1: port@1 {
358				reg = <1>;
359				ti,mac-only;
360				label = "port1";
361				ti,syscon-efuse = <&mcu_conf 0x200>;
362				phys = <&phy_gmii_sel 1>;
363			};
364		};
365
366		davinci_mdio: mdio@f00 {
367			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
368			reg = <0x0 0xf00 0x0 0x100>;
369			#address-cells = <1>;
370			#size-cells = <0>;
371			clocks = <&k3_clks 5 10>;
372			clock-names = "fck";
373			bus_freq = <1000000>;
374			status = "disabled";
375		};
376
377		cpts@3d000 {
378			compatible = "ti,am65-cpts";
379			reg = <0x0 0x3d000 0x0 0x400>;
380			clocks = <&mcu_cpsw_cpts_mux>;
381			clock-names = "cpts";
382			interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
383			interrupt-names = "cpts";
384			ti,cpts-ext-ts-inputs = <4>;
385			ti,cpts-periodic-outputs = <2>;
386
387			mcu_cpsw_cpts_mux: refclk-mux {
388				#clock-cells = <0>;
389				clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
390					<&k3_clks 118 6>, <&k3_clks 118 3>,
391					<&k3_clks 118 8>, <&k3_clks 118 14>,
392					<&k3_clks 120 3>, <&k3_clks 121 3>;
393				assigned-clocks = <&mcu_cpsw_cpts_mux>;
394				assigned-clock-parents = <&k3_clks 118 5>;
395			};
396		};
397	};
398
399	mcu_r5fss0: r5fss@41000000 {
400		compatible = "ti,am654-r5fss";
401		ti,cluster-mode = <1>;
402		#address-cells = <1>;
403		#size-cells = <1>;
404		ranges = <0x41000000 0x00 0x41000000 0x20000>,
405			 <0x41400000 0x00 0x41400000 0x20000>;
406		power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
407
408		mcu_r5fss0_core0: r5f@41000000 {
409			compatible = "ti,am654-r5f";
410			reg = <0x41000000 0x00008000>,
411			      <0x41010000 0x00008000>;
412			reg-names = "atcm", "btcm";
413			ti,sci = <&dmsc>;
414			ti,sci-dev-id = <159>;
415			ti,sci-proc-ids = <0x01 0xff>;
416			resets = <&k3_reset 159 1>;
417			firmware-name = "am65x-mcu-r5f0_0-fw";
418			ti,atcm-enable = <1>;
419			ti,btcm-enable = <1>;
420			ti,loczrama = <1>;
421		};
422
423		mcu_r5fss0_core1: r5f@41400000 {
424			compatible = "ti,am654-r5f";
425			reg = <0x41400000 0x00008000>,
426			      <0x41410000 0x00008000>;
427			reg-names = "atcm", "btcm";
428			ti,sci = <&dmsc>;
429			ti,sci-dev-id = <245>;
430			ti,sci-proc-ids = <0x02 0xff>;
431			resets = <&k3_reset 245 1>;
432			firmware-name = "am65x-mcu-r5f0_1-fw";
433			ti,atcm-enable = <1>;
434			ti,btcm-enable = <1>;
435			ti,loczrama = <1>;
436		};
437	};
438
439	mcu_rti1: watchdog@40610000 {
440		compatible = "ti,j7-rti-wdt";
441		reg = <0x0 0x40610000 0x0 0x100>;
442		clocks = <&k3_clks 135 0>;
443		power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
444		assigned-clocks = <&k3_clks 135 0>;
445		assigned-clock-parents = <&k3_clks 135 4>;
446	};
447};
448