#
2822c791 |
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22-Jan-2024 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65: Add MIT license along with GPL-2.0 Modify license to include dual licensing as GPL-2.0-only OR MIT license for SoC and TI evm device tree files. This allows for Linux kernel device tree to be used in other Operating System ecosystems such as Zephyr or FreeBSD. While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync with latest SPDX conventions (GPL-2.0 is deprecated). While at this, update the TI copyright year to sync with current year to indicate license change (and add it at least for one file which was missing TI copyright). Cc: "Alexander A. Klimov" <grandmaster@al2klimov.de> Cc: Jan Kiszka <jan.kiszka@siemens.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Rob Herring <robh@kernel.org> Cc: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Acked-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240122145539.194512-7-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
0fa8d3a5 |
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13-Dec-2023 |
Manorit Chawdhry <m-chawdhry@ti.com> |
arm64: dts: ti: k3-am65: Add additional regs for DMA components Add additional reg properties for UDMA and RingAcc nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20231213135138.929517-2-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
6507bfa7 |
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05-Oct-2023 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-*: Convert NAVSS to simple-bus "simple-mfd" as standalone compatible is frowned upon, so model main and MCU NAVSS (Navigator SubSystem) nodes as simple-bus as there is really no need for these nodes to be MFD. Link: https://lore.kernel.org/r/20231005151302.1290363-3-vigneshr@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
8ea3fc2b |
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10-Aug-2023 |
Dhruva Gole <d-gole@ti.com> |
arm64: dts: ti: k3-*: fix fss node dtbs check warnings Fix these fss node warnings that dtbs_check throws: fss@47000000: $nodename:0: 'fss@47000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' By renaming fss to bus. Cc: Nishant Menon <nm@ti.com> Suggested-by: Andrew Davis <afd@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Reid Tonking <reidt@ti.com> Link: https://lore.kernel.org/r/20230810081847.277094-1-d-gole@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
1228242d |
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09-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable TSCADC nodes at the board level TSCADC nodes defined in the top-level AM65 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information. Disable the TSCADC nodes in the top-level dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-13-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
46d0c519 |
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09-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable OSPI nodes at the board level OSPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-5-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
702110c2 |
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09-Aug-2023 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3: Add cfg reg region to ringacc node Add register range of ringacc cfg node to all k3 SoC dtsi files. This is normally under Device Management firmware control but some entities like bootloader have to access directly and thus required to be present in DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230809175932.2553156-3-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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#
414772b8 |
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02-Jul-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: ti: minor whitespace cleanup around '=' The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230702185221.44319-1-krzysztof.kozlowski@linaro.org Signed-off-by: Nishanth Menon <nm@ti.com>
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#
84debc33 |
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30-May-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65-mcu: Add mcu_secproxy MCU domain has it's own secure proxy for communicating with ROM and for R5 micro controller firmware operations. This is in addition to the one in the main domain NAVSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230530165900.47502-4-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
498f7b0f |
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07-Jun-2023 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65-main: Fix mcan node name s/mcan/can to stay in sync with bindings conventions. Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230607132043.3932726-2-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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#
cdbaf880 |
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15-Nov-2022 |
Tony Lindgren <tony@atomide.com> |
arm64: dts: ti: k3-am65: Add general purpose timers for am65 There are 12 general purpose timers on am65 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional four timers in the MCU domain that do not have interrupts routable for Linux. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Compared to am64, the timer clocks are different on am65. And the MCU timers are at a different IO address. Then j72 adds more timers compared to am65 with a total of 30 timers. And the j72 clocks are different. To avoid duplication for dtsi files, eventually we may want to consider adding timer specific shared dtsi files with the timer clocks mapped using SoC specific files in include/dt-bindings/clock. But let's get am65 timers usable first. Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221115154842.7755-3-tony@atomide.com
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#
7928c712 |
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15-Nov-2022 |
Tony Lindgren <tony@atomide.com> |
arm64: dts: ti: k3-am65: Configure pinctrl for timer IO pads Compared to the earlier TI SoCs, am65 has an additional level of dedicated multiplexing registers for the timer IO pads. There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.8.3.1 Timers Overview". For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3632. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework. Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221115154842.7755-2-tony@atomide.com
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#
b08bf4a5 |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable MCAN nodes at the board level MCAN nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the MCAN nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-9-afd@ti.com
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#
c75c5c0b |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable MDIO nodes at the board level MDIO nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with a pinmux. As the attached PHY is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the MDIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-8-afd@ti.com
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#
1c49cbb1 |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable SPI nodes at the board level SPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the SPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-4-afd@ti.com
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c0a5ba87 |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable I2C nodes at the board level I2C nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the I2C nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-3-afd@ti.com
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#
65e8781a |
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28-Oct-2022 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am65: Enable UART nodes at the board level UART nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the UART nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-2-afd@ti.com
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#
e5bad300 |
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24-Oct-2022 |
Matt Ranostay <mranostay@ti.com> |
arm64: dts: ti: Rename clock-names adc_tsc_fck to fck Avoid the following warnings from dt-schema by just renaming the clock-names string from adc_tsc_fck to fck so it matches the values in ti,am3359-tscadc.yaml tscadc@40200000: clock-names:0: 'fck' was expected Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Judith Mendez <jm@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20221024151648.394623-1-mranostay@ti.com
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#
c3e4ea55 |
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22-Nov-2021 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: k3-am65-mcu: Add Support for MCAN Add Support for two MCAN controllers present on the am65x SOC. Both support classic CAN messages as well as CAN-FD. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20211122134159.29936-2-a-govindraju@ti.com
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#
d65f069e |
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07-Jun-2021 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes 8250_omap compatible UART IPs on all SoCs have registers aligned at 4 byte address boundary and constant byte addressability. Thus there is no need for reg-io-width or reg-shift DT properties. These properties are not used by 8250_omap driver nor documented as part of binding document. Therefore drop them. This is in preparation to move omap-serial.txt to YAML format. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210607134558.23704-1-vigneshr@ti.com
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#
9ecdb6d6 |
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10-May-2021 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-am65|j721e|am64: Map the dma / navigator subsystem via explicit ranges Instead of using empty ranges property, lets map explicitly the address range that is mapped onto the dma / navigator subsystems (navss/dmss). This is also exposed via the dtbs_check with dt-schema newer than 2021.03 version by throwing out following: arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml: bus@100000: main-navss: {'type': 'object'} is not allowed for {'compatible': ['simple-mfd'], '#address-cells': [[2]], ..... This has already been correctly done for J7200, however was missed for other k3 SoCs. Fix that oversight. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tero Kristo <kristo@kernel.org> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20210510145429.8752-1-nm@ti.com
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6674a90b |
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20-Feb-2021 |
Jan Kiszka <jan.kiszka@siemens.com> |
arm64: dts: ti: k3-am65-mcu: Add RTI watchdog entry Add the DT entry for a watchdog based on RTI1. On SR1.0 silicon, it requires additional firmware on the MCU R5F cores to handle the expiry, e.g. https://github.com/siemens/k3-rti-wdt. As this firmware will also lock the power domain to protect it against premature shutdown, mark it shared. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Praneeth Bajjuri <praneeth@ti.com> Link: https://lore.kernel.org/r/279c20fa-6e5e-4f88-9cd1-f76297a28a19@web.de
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#
5bb9e0f6 |
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28-Oct-2020 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-am65-mcu: Add MCU domain R5F cluster node The AM65x SoCs have a single dual-core Arm Cortex-R5F processor (R5FSS) subsystem/cluster. This R5F cluster (MCU_R5FSS0) is present within the MCU domain, and can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - TCMA and TCMB (further interleaved into two banks). There are some IP integration differences from standard Arm R5F clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for this R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A53 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: am65x-mcu-r5f0_0-fw (LockStep mode and for Core0 in Split mode) am65x-mcu-r5f0_1-fw (Core1 in Split mode) Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20201029033802.15366-2-s-anna@ti.com
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#
9dcd17be |
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29-Aug-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am65: ringacc: drop ti, dma-ring-reset-quirk Remove obsolete "ti,dma-ring-reset-quirk" Ringacc DT property. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200829184139.15547-4-grygorii.strashko@ti.com
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e5c956c4 |
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03-Sep-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: k3-*: Fix up node_name_chars_strict warnings Building with W=2 throws up a bunch of easy to fixup warnings.. node_name_chars_strict is one of them.. Knock those out. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200903130015.21361-9-nm@ti.com
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#
6da45875 |
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06-Aug-2020 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: k3-am65: Update the RM resource types Update the ringacc and udma dt nodes to use the latest RM resource types similar to the ones used in k3-j721e dt nodes. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200806074826.24607-14-lokeshvutla@ti.com
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303d6f62 |
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12-Jul-2020 |
Alexander A. Klimov <grandmaster@al2klimov.de> |
arm64: dts: ti: k3-*: Replace HTTP links with HTTPS ones Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
ef2d1363 |
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06-May-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am65/j721e-mcu: update cpts node Update CPTS node following DT binding update: - add reg and compatible properties - fix node name Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
885a26ba |
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01-May-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am65-mcu: add cpsw cpts node Add DT node for the TI AM65x SoC Common Platform Time Sync (CPTS). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ba86a6e9 |
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23-Mar-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am65-mcu: add cpsw nuss node Add DT node for the TI AM65x SoC Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
243246b5 |
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03-Mar-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am65-mcu: add phy-gmii-sel node Add DT node for the TI AM65x SoC phy-gmii-sel PHY required for Ethernet ports mode selection. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
85800da0 |
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12-Mar-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-am65-mcu: Add DMA entries for ADC Add DMA entries for ADC nodes Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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#
3d623054 |
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23-Jan-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-am65: DMA support Add the ringacc and udmap nodes for main and mcu NAVSS. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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f2965b99 |
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16-Dec-2019 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am65-mcu: add system control module node The MCU System control module support is added to the device tree to allow drivers to access to their System control module registers. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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07481770 |
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11-Dec-2019 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-am65: Add OSPI DT node AM654 SoC has two Cadence OSPI controller instances under Flash subsystem (FSS). Add DT nodes for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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c68272cb |
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29-Jul-2019 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: k3-am654: Update the power domain cells Update the power-domain cells to 2 and mark all devices as exclusive. Main uart 0 is the debug console for based boards and it is used by different software entities like u-boot, atf, linux. So just mark main_uart0 as shared device for base board. Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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f853f005 |
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05-Jun-2019 |
Suman Anna <s-anna@ti.com> |
arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node Add the on-chip SRAM present within the MCU domain as a mmio-sram node. The K3 AM65x SoCs have 512 KB of such memory. Any specific memory range within this RAM needed by a software module ought to be reserved using an appropriate child node. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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aa6eaaa2 |
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12-Feb-2019 |
Vignesh R <vigneshr@ti.com> |
arm64: dts: ti: k3-am65-mcu: Add ADC nodes TI AM654 SoC has two ADC instances in the MCU domain. Add DT nodes for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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2cd7d393 |
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09-Dec-2018 |
Vignesh R <vigneshr@ti.com> |
arm64: dts: ti: k3-am654: Add McSPI DT nodes There are 3 instances of McSPI in MCU domain and 4 instances in Main domain. Add DT nodes for all McSPI instances present on AM654 SoC. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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c484fc95 |
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11-Dec-2018 |
Vignesh R <vigneshr@ti.com> |
arm64: dts: ti: k3-am654: Populate power-domain property for UART nodes Populate power-domain property for UART nodes, this is required for Linux to enable UART clocks via PM calls. Without this UART instances not initialized by bootloader (like main_uart1) fails to work in Linux. Also, drop current-speed property from main_uart1 and main_uart2 nodes as these UARTs are not initialized before Linux boots up and current speed is unknown. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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19a1768f |
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12-Nov-2018 |
Vignesh R <vigneshr@ti.com> |
arm64: dts: ti: k3-am654-base-board: Add I2C nodes Add DT entries for I2C instances present in AM654 SoC. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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4201af25 |
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05-Sep-2018 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: am654: Add uart nodes Add uart nodes for AM654 device tree components. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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