1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/*
3 * Device Tree Source for AM642 SoC family in Dual core configuration
4 *
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8/dts-v1/;
9
10#include "k3-am64.dtsi"
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu-map {
18			cluster0: cluster0 {
19				core0 {
20					cpu = <&cpu0>;
21				};
22
23				core1 {
24					cpu = <&cpu1>;
25				};
26			};
27		};
28
29		cpu0: cpu@0 {
30			compatible = "arm,cortex-a53";
31			reg = <0x000>;
32			device_type = "cpu";
33			enable-method = "psci";
34			i-cache-size = <0x8000>;
35			i-cache-line-size = <64>;
36			i-cache-sets = <256>;
37			d-cache-size = <0x8000>;
38			d-cache-line-size = <64>;
39			d-cache-sets = <128>;
40			next-level-cache = <&L2_0>;
41		};
42
43		cpu1: cpu@1 {
44			compatible = "arm,cortex-a53";
45			reg = <0x001>;
46			device_type = "cpu";
47			enable-method = "psci";
48			i-cache-size = <0x8000>;
49			i-cache-line-size = <64>;
50			i-cache-sets = <256>;
51			d-cache-size = <0x8000>;
52			d-cache-line-size = <64>;
53			d-cache-sets = <128>;
54			next-level-cache = <&L2_0>;
55		};
56	};
57
58	L2_0: l2-cache0 {
59		compatible = "cache";
60		cache-level = <2>;
61		cache-unified;
62		cache-size = <0x40000>;
63		cache-line-size = <64>;
64		cache-sets = <256>;
65	};
66};
67