1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
4 */
5
6/dts-v1/;
7#include "sparx5_pcb_common.dtsi"
8
9/{
10	gpio-restart {
11		compatible = "gpio-restart";
12		gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
13		priority = <200>;
14	};
15
16	leds {
17		compatible = "gpio-leds";
18		led-0 {
19			label = "eth60:yellow";
20			gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>;
21			default-state = "off";
22		};
23		led-1 {
24			label = "eth60:green";
25			gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>;
26			default-state = "off";
27		};
28		led-2 {
29			label = "eth61:yellow";
30			gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>;
31			default-state = "off";
32		};
33		led-3 {
34			label = "eth61:green";
35			gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>;
36			default-state = "off";
37		};
38		led-4 {
39			label = "eth62:yellow";
40			gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>;
41			default-state = "off";
42		};
43		led-5 {
44			label = "eth62:green";
45			gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>;
46			default-state = "off";
47		};
48		led-6 {
49			label = "eth63:yellow";
50			gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>;
51			default-state = "off";
52		};
53		led-7 {
54			label = "eth63:green";
55			gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>;
56			default-state = "off";
57		};
58	};
59};
60
61&gpio {
62	i2cmux_pins_i: i2cmux-pins {
63	       pins = "GPIO_35", "GPIO_36",
64		      "GPIO_50", "GPIO_51";
65		function = "twi_scl_m";
66		output-low;
67	};
68	i2cmux_s29: i2cmux-0-pins {
69		pins = "GPIO_35";
70		function = "twi_scl_m";
71		output-high;
72	};
73	i2cmux_s30: i2cmux-1-pins {
74		pins = "GPIO_36";
75		function = "twi_scl_m";
76		output-high;
77	};
78	i2cmux_s31: i2cmux-2-pins {
79		pins = "GPIO_50";
80		function = "twi_scl_m";
81		output-high;
82	};
83	i2cmux_s32: i2cmux-3-pins {
84		pins = "GPIO_51";
85		function = "twi_scl_m";
86		output-high;
87	};
88};
89
90&spi0 {
91	status = "okay";
92	spi@0 {
93		compatible = "spi-mux";
94		mux-controls = <&mux>;
95		#address-cells = <1>;
96		#size-cells = <0>;
97		reg = <0>; /* CS0 */
98		flash@9 {
99			compatible = "jedec,spi-nor";
100			spi-max-frequency = <8000000>;
101			reg = <0x9>; /* SPI */
102		};
103	};
104};
105
106&sgpio1 {
107	status = "okay";
108	microchip,sgpio-port-ranges = <24 31>;
109	gpio@0 {
110		ngpios = <64>;
111	};
112	gpio@1 {
113		ngpios = <64>;
114	};
115};
116
117&sgpio2 {
118	status = "okay";
119	microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
120};
121
122&axi {
123	i2c0_imux: i2c-mux {
124		compatible = "i2c-mux-pinctrl";
125		#address-cells = <1>;
126		#size-cells = <0>;
127		i2c-parent = <&i2c0>;
128	};
129};
130
131&i2c0_imux {
132	pinctrl-names =
133		"i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",
134		"idle";
135	pinctrl-0 = <&i2cmux_s29>;
136	pinctrl-1 = <&i2cmux_s30>;
137	pinctrl-2 = <&i2cmux_s31>;
138	pinctrl-3 = <&i2cmux_s32>;
139	pinctrl-4 = <&i2cmux_pins_i>;
140	i2c_sfp1: i2c@0 {
141		reg = <0x0>;
142		#address-cells = <1>;
143		#size-cells = <0>;
144	};
145	i2c_sfp2: i2c@1 {
146		reg = <0x1>;
147		#address-cells = <1>;
148		#size-cells = <0>;
149	};
150	i2c_sfp3: i2c@2 {
151		reg = <0x2>;
152		#address-cells = <1>;
153		#size-cells = <0>;
154	};
155	i2c_sfp4: i2c@3 {
156		reg = <0x3>;
157		#address-cells = <1>;
158		#size-cells = <0>;
159	};
160};
161
162&axi {
163	sfp_eth60: sfp-eth60 {
164		compatible	 = "sff,sfp";
165		i2c-bus = <&i2c_sfp1>;
166		tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
167		rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
168		los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
169		mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
170		tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
171	};
172	sfp_eth61: sfp-eth61 {
173		compatible = "sff,sfp";
174		i2c-bus = <&i2c_sfp2>;
175		tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
176		rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
177		los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
178		mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
179		tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
180	};
181	sfp_eth62: sfp-eth62 {
182		compatible = "sff,sfp";
183		i2c-bus = <&i2c_sfp3>;
184		tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
185		rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
186		los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
187		mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
188		tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
189	};
190	sfp_eth63: sfp-eth63 {
191		compatible = "sff,sfp";
192		i2c-bus = <&i2c_sfp4>;
193		tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
194		rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
195		los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
196		mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
197		tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
198	};
199};
200
201&mdio0 {
202	status = "okay";
203	phy0: ethernet-phy@0 {
204		reg = <0>;
205	};
206	phy1: ethernet-phy@1 {
207		reg = <1>;
208	};
209	phy2: ethernet-phy@2 {
210		reg = <2>;
211	};
212	phy3: ethernet-phy@3 {
213		reg = <3>;
214	};
215	phy4: ethernet-phy@4 {
216		reg = <4>;
217	};
218	phy5: ethernet-phy@5 {
219		reg = <5>;
220	};
221	phy6: ethernet-phy@6 {
222		reg = <6>;
223	};
224	phy7: ethernet-phy@7 {
225		reg = <7>;
226	};
227	phy8: ethernet-phy@8 {
228		reg = <8>;
229	};
230	phy9: ethernet-phy@9 {
231		reg = <9>;
232	};
233	phy10: ethernet-phy@10 {
234		reg = <10>;
235	};
236	phy11: ethernet-phy@11 {
237		reg = <11>;
238	};
239	phy12: ethernet-phy@12 {
240		reg = <12>;
241	};
242	phy13: ethernet-phy@13 {
243		reg = <13>;
244	};
245	phy14: ethernet-phy@14 {
246		reg = <14>;
247	};
248	phy15: ethernet-phy@15 {
249		reg = <15>;
250	};
251	phy16: ethernet-phy@16 {
252		reg = <16>;
253	};
254	phy17: ethernet-phy@17 {
255		reg = <17>;
256	};
257	phy18: ethernet-phy@18 {
258		reg = <18>;
259	};
260	phy19: ethernet-phy@19 {
261		reg = <19>;
262	};
263	phy20: ethernet-phy@20 {
264		reg = <20>;
265	};
266	phy21: ethernet-phy@21 {
267		reg = <21>;
268	};
269	phy22: ethernet-phy@22 {
270		reg = <22>;
271	};
272	phy23: ethernet-phy@23 {
273		reg = <23>;
274	};
275};
276
277&mdio1 {
278	status = "okay";
279	phy24: ethernet-phy@24 {
280		reg = <0>;
281	};
282	phy25: ethernet-phy@25 {
283		reg = <1>;
284	};
285	phy26: ethernet-phy@26 {
286		reg = <2>;
287	};
288	phy27: ethernet-phy@27 {
289		reg = <3>;
290	};
291	phy28: ethernet-phy@28 {
292		reg = <4>;
293	};
294	phy29: ethernet-phy@29 {
295		reg = <5>;
296	};
297	phy30: ethernet-phy@30 {
298		reg = <6>;
299	};
300	phy31: ethernet-phy@31 {
301		reg = <7>;
302	};
303	phy32: ethernet-phy@32 {
304		reg = <8>;
305	};
306	phy33: ethernet-phy@33 {
307		reg = <9>;
308	};
309	phy34: ethernet-phy@34 {
310		reg = <10>;
311	};
312	phy35: ethernet-phy@35 {
313		reg = <11>;
314	};
315	phy36: ethernet-phy@36 {
316		reg = <12>;
317	};
318	phy37: ethernet-phy@37 {
319		reg = <13>;
320	};
321	phy38: ethernet-phy@38 {
322		reg = <14>;
323	};
324	phy39: ethernet-phy@39 {
325		reg = <15>;
326	};
327	phy40: ethernet-phy@40 {
328		reg = <16>;
329	};
330	phy41: ethernet-phy@41 {
331		reg = <17>;
332	};
333	phy42: ethernet-phy@42 {
334		reg = <18>;
335	};
336	phy43: ethernet-phy@43 {
337		reg = <19>;
338	};
339	phy44: ethernet-phy@44 {
340		reg = <20>;
341	};
342	phy45: ethernet-phy@45 {
343		reg = <21>;
344	};
345	phy46: ethernet-phy@46 {
346		reg = <22>;
347	};
348	phy47: ethernet-phy@47 {
349		reg = <23>;
350	};
351};
352
353&mdio3 {
354	status = "okay";
355	phy64: ethernet-phy@64 {
356		reg = <28>;
357	};
358};
359
360&switch {
361	ethernet-ports {
362		#address-cells = <1>;
363		#size-cells = <0>;
364
365		port0: port@0 {
366			reg = <0>;
367			microchip,bandwidth = <1000>;
368			phys = <&serdes 13>;
369			phy-handle = <&phy0>;
370			phy-mode = "qsgmii";
371		};
372		port1: port@1 {
373			reg = <1>;
374			microchip,bandwidth = <1000>;
375			phys = <&serdes 13>;
376			phy-handle = <&phy1>;
377			phy-mode = "qsgmii";
378		};
379		port2: port@2 {
380			reg = <2>;
381			microchip,bandwidth = <1000>;
382			phys = <&serdes 13>;
383			phy-handle = <&phy2>;
384			phy-mode = "qsgmii";
385		};
386		port3: port@3 {
387			reg = <3>;
388			microchip,bandwidth = <1000>;
389			phys = <&serdes 13>;
390			phy-handle = <&phy3>;
391			phy-mode = "qsgmii";
392		};
393		port4: port@4 {
394			reg = <4>;
395			microchip,bandwidth = <1000>;
396			phys = <&serdes 14>;
397			phy-handle = <&phy4>;
398			phy-mode = "qsgmii";
399		};
400		port5: port@5 {
401			reg = <5>;
402			microchip,bandwidth = <1000>;
403			phys = <&serdes 14>;
404			phy-handle = <&phy5>;
405			phy-mode = "qsgmii";
406		};
407		port6: port@6 {
408			reg = <6>;
409			microchip,bandwidth = <1000>;
410			phys = <&serdes 14>;
411			phy-handle = <&phy6>;
412			phy-mode = "qsgmii";
413		};
414		port7: port@7 {
415			reg = <7>;
416			microchip,bandwidth = <1000>;
417			phys = <&serdes 14>;
418			phy-handle = <&phy7>;
419			phy-mode = "qsgmii";
420		};
421		port8: port@8 {
422			reg = <8>;
423			microchip,bandwidth = <1000>;
424			phys = <&serdes 15>;
425			phy-handle = <&phy8>;
426			phy-mode = "qsgmii";
427		};
428		port9: port@9 {
429			reg = <9>;
430			microchip,bandwidth = <1000>;
431			phys = <&serdes 15>;
432			phy-handle = <&phy9>;
433			phy-mode = "qsgmii";
434		};
435		port10: port@10 {
436			reg = <10>;
437			microchip,bandwidth = <1000>;
438			phys = <&serdes 15>;
439			phy-handle = <&phy10>;
440			phy-mode = "qsgmii";
441		};
442		port11: port@11 {
443			reg = <11>;
444			microchip,bandwidth = <1000>;
445			phys = <&serdes 15>;
446			phy-handle = <&phy11>;
447			phy-mode = "qsgmii";
448		};
449		port12: port@12 {
450			reg = <12>;
451			microchip,bandwidth = <1000>;
452			phys = <&serdes 16>;
453			phy-handle = <&phy12>;
454			phy-mode = "qsgmii";
455		};
456		port13: port@13 {
457			reg = <13>;
458			microchip,bandwidth = <1000>;
459			phys = <&serdes 16>;
460			phy-handle = <&phy13>;
461			phy-mode = "qsgmii";
462		};
463		port14: port@14 {
464			reg = <14>;
465			microchip,bandwidth = <1000>;
466			phys = <&serdes 16>;
467			phy-handle = <&phy14>;
468			phy-mode = "qsgmii";
469		};
470		port15: port@15 {
471			reg = <15>;
472			microchip,bandwidth = <1000>;
473			phys = <&serdes 16>;
474			phy-handle = <&phy15>;
475			phy-mode = "qsgmii";
476		};
477		port16: port@16 {
478			reg = <16>;
479			microchip,bandwidth = <1000>;
480			phys = <&serdes 17>;
481			phy-handle = <&phy16>;
482			phy-mode = "qsgmii";
483		};
484		port17: port@17 {
485			reg = <17>;
486			microchip,bandwidth = <1000>;
487			phys = <&serdes 17>;
488			phy-handle = <&phy17>;
489			phy-mode = "qsgmii";
490		};
491		port18: port@18 {
492			reg = <18>;
493			microchip,bandwidth = <1000>;
494			phys = <&serdes 17>;
495			phy-handle = <&phy18>;
496			phy-mode = "qsgmii";
497		};
498		port19: port@19 {
499			reg = <19>;
500			microchip,bandwidth = <1000>;
501			phys = <&serdes 17>;
502			phy-handle = <&phy19>;
503			phy-mode = "qsgmii";
504		};
505		port20: port@20 {
506			reg = <20>;
507			microchip,bandwidth = <1000>;
508			phys = <&serdes 18>;
509			phy-handle = <&phy20>;
510			phy-mode = "qsgmii";
511		};
512		port21: port@21 {
513			reg = <21>;
514			microchip,bandwidth = <1000>;
515			phys = <&serdes 18>;
516			phy-handle = <&phy21>;
517			phy-mode = "qsgmii";
518		};
519		port22: port@22 {
520			reg = <22>;
521			microchip,bandwidth = <1000>;
522			phys = <&serdes 18>;
523			phy-handle = <&phy22>;
524			phy-mode = "qsgmii";
525		};
526		port23: port@23 {
527			reg = <23>;
528			microchip,bandwidth = <1000>;
529			phys = <&serdes 18>;
530			phy-handle = <&phy23>;
531			phy-mode = "qsgmii";
532		};
533		port24: port@24 {
534			reg = <24>;
535			microchip,bandwidth = <1000>;
536			phys = <&serdes 19>;
537			phy-handle = <&phy24>;
538			phy-mode = "qsgmii";
539		};
540		port25: port@25 {
541			reg = <25>;
542			microchip,bandwidth = <1000>;
543			phys = <&serdes 19>;
544			phy-handle = <&phy25>;
545			phy-mode = "qsgmii";
546		};
547		port26: port@26 {
548			reg = <26>;
549			microchip,bandwidth = <1000>;
550			phys = <&serdes 19>;
551			phy-handle = <&phy26>;
552			phy-mode = "qsgmii";
553		};
554		port27: port@27 {
555			reg = <27>;
556			microchip,bandwidth = <1000>;
557			phys = <&serdes 19>;
558			phy-handle = <&phy27>;
559			phy-mode = "qsgmii";
560		};
561		port28: port@28 {
562			reg = <28>;
563			microchip,bandwidth = <1000>;
564			phys = <&serdes 20>;
565			phy-handle = <&phy28>;
566			phy-mode = "qsgmii";
567		};
568		port29: port@29 {
569			reg = <29>;
570			microchip,bandwidth = <1000>;
571			phys = <&serdes 20>;
572			phy-handle = <&phy29>;
573			phy-mode = "qsgmii";
574		};
575		port30: port@30 {
576			reg = <30>;
577			microchip,bandwidth = <1000>;
578			phys = <&serdes 20>;
579			phy-handle = <&phy30>;
580			phy-mode = "qsgmii";
581		};
582		port31: port@31 {
583			reg = <31>;
584			microchip,bandwidth = <1000>;
585			phys = <&serdes 20>;
586			phy-handle = <&phy31>;
587			phy-mode = "qsgmii";
588		};
589		port32: port@32 {
590			reg = <32>;
591			microchip,bandwidth = <1000>;
592			phys = <&serdes 21>;
593			phy-handle = <&phy32>;
594			phy-mode = "qsgmii";
595		};
596		port33: port@33 {
597			reg = <33>;
598			microchip,bandwidth = <1000>;
599			phys = <&serdes 21>;
600			phy-handle = <&phy33>;
601			phy-mode = "qsgmii";
602		};
603		port34: port@34 {
604			reg = <34>;
605			microchip,bandwidth = <1000>;
606			phys = <&serdes 21>;
607			phy-handle = <&phy34>;
608			phy-mode = "qsgmii";
609		};
610		port35: port@35 {
611			reg = <35>;
612			microchip,bandwidth = <1000>;
613			phys = <&serdes 21>;
614			phy-handle = <&phy35>;
615			phy-mode = "qsgmii";
616		};
617		port36: port@36 {
618			reg = <36>;
619			microchip,bandwidth = <1000>;
620			phys = <&serdes 22>;
621			phy-handle = <&phy36>;
622			phy-mode = "qsgmii";
623		};
624		port37: port@37 {
625			reg = <37>;
626			microchip,bandwidth = <1000>;
627			phys = <&serdes 22>;
628			phy-handle = <&phy37>;
629			phy-mode = "qsgmii";
630		};
631		port38: port@38 {
632			reg = <38>;
633			microchip,bandwidth = <1000>;
634			phys = <&serdes 22>;
635			phy-handle = <&phy38>;
636			phy-mode = "qsgmii";
637		};
638		port39: port@39 {
639			reg = <39>;
640			microchip,bandwidth = <1000>;
641			phys = <&serdes 22>;
642			phy-handle = <&phy39>;
643			phy-mode = "qsgmii";
644		};
645		port40: port@40 {
646			reg = <40>;
647			microchip,bandwidth = <1000>;
648			phys = <&serdes 23>;
649			phy-handle = <&phy40>;
650			phy-mode = "qsgmii";
651		};
652		port41: port@41 {
653			reg = <41>;
654			microchip,bandwidth = <1000>;
655			phys = <&serdes 23>;
656			phy-handle = <&phy41>;
657			phy-mode = "qsgmii";
658		};
659		port42: port@42 {
660			reg = <42>;
661			microchip,bandwidth = <1000>;
662			phys = <&serdes 23>;
663			phy-handle = <&phy42>;
664			phy-mode = "qsgmii";
665		};
666		port43: port@43 {
667			reg = <43>;
668			microchip,bandwidth = <1000>;
669			phys = <&serdes 23>;
670			phy-handle = <&phy43>;
671			phy-mode = "qsgmii";
672		};
673		port44: port@44 {
674			reg = <44>;
675			microchip,bandwidth = <1000>;
676			phys = <&serdes 24>;
677			phy-handle = <&phy44>;
678			phy-mode = "qsgmii";
679		};
680		port45: port@45 {
681			reg = <45>;
682			microchip,bandwidth = <1000>;
683			phys = <&serdes 24>;
684			phy-handle = <&phy45>;
685			phy-mode = "qsgmii";
686		};
687		port46: port@46 {
688			reg = <46>;
689			microchip,bandwidth = <1000>;
690			phys = <&serdes 24>;
691			phy-handle = <&phy46>;
692			phy-mode = "qsgmii";
693		};
694		port47: port@47 {
695			reg = <47>;
696			microchip,bandwidth = <1000>;
697			phys = <&serdes 24>;
698			phy-handle = <&phy47>;
699			phy-mode = "qsgmii";
700		};
701		/* Then the 25G interfaces */
702		port60: port@60 {
703			reg = <60>;
704			microchip,bandwidth = <25000>;
705			phys = <&serdes 29>;
706			phy-mode = "10gbase-r";
707			sfp = <&sfp_eth60>;
708			managed = "in-band-status";
709		};
710		port61: port@61 {
711			reg = <61>;
712			microchip,bandwidth = <25000>;
713			phys = <&serdes 30>;
714			phy-mode = "10gbase-r";
715			sfp = <&sfp_eth61>;
716			managed = "in-band-status";
717		};
718		port62: port@62 {
719			reg = <62>;
720			microchip,bandwidth = <25000>;
721			phys = <&serdes 31>;
722			phy-mode = "10gbase-r";
723			sfp = <&sfp_eth62>;
724			managed = "in-band-status";
725		};
726		port63: port@63 {
727			reg = <63>;
728			microchip,bandwidth = <25000>;
729			phys = <&serdes 32>;
730			phy-mode = "10gbase-r";
731			sfp = <&sfp_eth63>;
732			managed = "in-band-status";
733		};
734		/* Finally the Management interface */
735		port64: port@64 {
736			reg = <64>;
737			microchip,bandwidth = <1000>;
738			phys = <&serdes 0>;
739			phy-handle = <&phy64>;
740			phy-mode = "sgmii";
741		};
742	};
743};
744