1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interconnect/fsl,imx8mp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15#include "imx8mp-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec; 24 ethernet1 = &eqos; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 i2c4 = &i2c5; 35 i2c5 = &i2c6; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 spi0 = &flexspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 A53_0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0>; 54 clock-latency = <61036>; 55 clocks = <&clk IMX8MP_CLK_ARM>; 56 enable-method = "psci"; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&A53_L2>; 64 nvmem-cells = <&cpu_speed_grade>; 65 nvmem-cell-names = "speed_grade"; 66 operating-points-v2 = <&a53_opp_table>; 67 #cooling-cells = <2>; 68 }; 69 70 A53_1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x1>; 74 clock-latency = <61036>; 75 clocks = <&clk IMX8MP_CLK_ARM>; 76 enable-method = "psci"; 77 i-cache-size = <0x8000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <128>; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A53_2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x2>; 92 clock-latency = <61036>; 93 clocks = <&clk IMX8MP_CLK_ARM>; 94 enable-method = "psci"; 95 i-cache-size = <0x8000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 }; 105 106 A53_3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x3>; 110 clock-latency = <61036>; 111 clocks = <&clk IMX8MP_CLK_ARM>; 112 enable-method = "psci"; 113 i-cache-size = <0x8000>; 114 i-cache-line-size = <64>; 115 i-cache-sets = <256>; 116 d-cache-size = <0x8000>; 117 d-cache-line-size = <64>; 118 d-cache-sets = <128>; 119 next-level-cache = <&A53_L2>; 120 operating-points-v2 = <&a53_opp_table>; 121 #cooling-cells = <2>; 122 }; 123 124 A53_L2: l2-cache0 { 125 compatible = "cache"; 126 cache-unified; 127 cache-level = <2>; 128 cache-size = <0x80000>; 129 cache-line-size = <64>; 130 cache-sets = <512>; 131 }; 132 }; 133 134 a53_opp_table: opp-table { 135 compatible = "operating-points-v2"; 136 opp-shared; 137 138 opp-1200000000 { 139 opp-hz = /bits/ 64 <1200000000>; 140 opp-microvolt = <850000>; 141 opp-supported-hw = <0x8a0>, <0x7>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 146 opp-1600000000 { 147 opp-hz = /bits/ 64 <1600000000>; 148 opp-microvolt = <950000>; 149 opp-supported-hw = <0xa0>, <0x7>; 150 clock-latency-ns = <150000>; 151 opp-suspend; 152 }; 153 154 opp-1800000000 { 155 opp-hz = /bits/ 64 <1800000000>; 156 opp-microvolt = <1000000>; 157 opp-supported-hw = <0x20>, <0x3>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 }; 162 163 osc_32k: clock-osc-32k { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <32768>; 167 clock-output-names = "osc_32k"; 168 }; 169 170 osc_24m: clock-osc-24m { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <24000000>; 174 clock-output-names = "osc_24m"; 175 }; 176 177 clk_ext1: clock-ext1 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext1"; 182 }; 183 184 clk_ext2: clock-ext2 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <133000000>; 188 clock-output-names = "clk_ext2"; 189 }; 190 191 clk_ext3: clock-ext3 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext3"; 196 }; 197 198 clk_ext4: clock-ext4 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext4"; 203 }; 204 205 funnel { 206 /* 207 * non-configurable funnel don't show up on the AMBA 208 * bus. As such no need to add "arm,primecell". 209 */ 210 compatible = "arm,coresight-static-funnel"; 211 212 in-ports { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 216 port@0 { 217 reg = <0>; 218 219 ca_funnel_in_port0: endpoint { 220 remote-endpoint = <&etm0_out_port>; 221 }; 222 }; 223 224 port@1 { 225 reg = <1>; 226 227 ca_funnel_in_port1: endpoint { 228 remote-endpoint = <&etm1_out_port>; 229 }; 230 }; 231 232 port@2 { 233 reg = <2>; 234 235 ca_funnel_in_port2: endpoint { 236 remote-endpoint = <&etm2_out_port>; 237 }; 238 }; 239 240 port@3 { 241 reg = <3>; 242 243 ca_funnel_in_port3: endpoint { 244 remote-endpoint = <&etm3_out_port>; 245 }; 246 }; 247 }; 248 249 out-ports { 250 port { 251 252 ca_funnel_out_port0: endpoint { 253 remote-endpoint = <&hugo_funnel_in_port0>; 254 }; 255 }; 256 }; 257 }; 258 259 reserved-memory { 260 #address-cells = <2>; 261 #size-cells = <2>; 262 ranges; 263 264 dsp_reserved: dsp@92400000 { 265 reg = <0 0x92400000 0 0x2000000>; 266 no-map; 267 status = "disabled"; 268 }; 269 }; 270 271 pmu { 272 compatible = "arm,cortex-a53-pmu"; 273 interrupts = <GIC_PPI 7 274 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 275 }; 276 277 psci { 278 compatible = "arm,psci-1.0"; 279 method = "smc"; 280 }; 281 282 thermal-zones { 283 cpu-thermal { 284 polling-delay-passive = <250>; 285 polling-delay = <2000>; 286 thermal-sensors = <&tmu 0>; 287 trips { 288 cpu_alert0: trip0 { 289 temperature = <85000>; 290 hysteresis = <2000>; 291 type = "passive"; 292 }; 293 294 cpu_crit0: trip1 { 295 temperature = <95000>; 296 hysteresis = <2000>; 297 type = "critical"; 298 }; 299 }; 300 301 cooling-maps { 302 map0 { 303 trip = <&cpu_alert0>; 304 cooling-device = 305 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 306 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 307 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 308 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 309 }; 310 }; 311 }; 312 313 soc-thermal { 314 polling-delay-passive = <250>; 315 polling-delay = <2000>; 316 thermal-sensors = <&tmu 1>; 317 trips { 318 soc_alert0: trip0 { 319 temperature = <85000>; 320 hysteresis = <2000>; 321 type = "passive"; 322 }; 323 324 soc_crit0: trip1 { 325 temperature = <95000>; 326 hysteresis = <2000>; 327 type = "critical"; 328 }; 329 }; 330 331 cooling-maps { 332 map0 { 333 trip = <&soc_alert0>; 334 cooling-device = 335 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 336 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 337 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 338 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 339 }; 340 }; 341 }; 342 }; 343 344 timer { 345 compatible = "arm,armv8-timer"; 346 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 347 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 348 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 349 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 350 clock-frequency = <8000000>; 351 arm,no-tick-in-suspend; 352 }; 353 354 soc: soc@0 { 355 compatible = "fsl,imx8mp-soc", "simple-bus"; 356 #address-cells = <1>; 357 #size-cells = <1>; 358 ranges = <0x0 0x0 0x0 0x3e000000>; 359 nvmem-cells = <&imx8mp_uid>; 360 nvmem-cell-names = "soc_unique_id"; 361 362 etm0: etm@28440000 { 363 compatible = "arm,coresight-etm4x", "arm,primecell"; 364 reg = <0x28440000 0x1000>; 365 cpu = <&A53_0>; 366 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 367 clock-names = "apb_pclk"; 368 369 out-ports { 370 port { 371 etm0_out_port: endpoint { 372 remote-endpoint = <&ca_funnel_in_port0>; 373 }; 374 }; 375 }; 376 }; 377 378 etm1: etm@28540000 { 379 compatible = "arm,coresight-etm4x", "arm,primecell"; 380 reg = <0x28540000 0x1000>; 381 cpu = <&A53_1>; 382 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 383 clock-names = "apb_pclk"; 384 385 out-ports { 386 port { 387 etm1_out_port: endpoint { 388 remote-endpoint = <&ca_funnel_in_port1>; 389 }; 390 }; 391 }; 392 }; 393 394 etm2: etm@28640000 { 395 compatible = "arm,coresight-etm4x", "arm,primecell"; 396 reg = <0x28640000 0x1000>; 397 cpu = <&A53_2>; 398 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 399 clock-names = "apb_pclk"; 400 401 out-ports { 402 port { 403 etm2_out_port: endpoint { 404 remote-endpoint = <&ca_funnel_in_port2>; 405 }; 406 }; 407 }; 408 }; 409 410 etm3: etm@28740000 { 411 compatible = "arm,coresight-etm4x", "arm,primecell"; 412 reg = <0x28740000 0x1000>; 413 cpu = <&A53_3>; 414 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 415 clock-names = "apb_pclk"; 416 417 out-ports { 418 port { 419 etm3_out_port: endpoint { 420 remote-endpoint = <&ca_funnel_in_port3>; 421 }; 422 }; 423 }; 424 }; 425 426 funnel@28c03000 { 427 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 428 reg = <0x28c03000 0x1000>; 429 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 430 clock-names = "apb_pclk"; 431 432 in-ports { 433 #address-cells = <1>; 434 #size-cells = <0>; 435 436 port@0 { 437 reg = <0>; 438 439 hugo_funnel_in_port0: endpoint { 440 remote-endpoint = <&ca_funnel_out_port0>; 441 }; 442 }; 443 444 port@1 { 445 reg = <1>; 446 447 hugo_funnel_in_port1: endpoint { 448 /* M7 input */ 449 }; 450 }; 451 452 port@2 { 453 reg = <2>; 454 455 hugo_funnel_in_port2: endpoint { 456 /* DSP input */ 457 }; 458 }; 459 /* the other input ports are not connect to anything */ 460 }; 461 462 out-ports { 463 port { 464 hugo_funnel_out_port0: endpoint { 465 remote-endpoint = <&etf_in_port>; 466 }; 467 }; 468 }; 469 }; 470 471 etf@28c04000 { 472 compatible = "arm,coresight-tmc", "arm,primecell"; 473 reg = <0x28c04000 0x1000>; 474 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 475 clock-names = "apb_pclk"; 476 477 in-ports { 478 port { 479 etf_in_port: endpoint { 480 remote-endpoint = <&hugo_funnel_out_port0>; 481 }; 482 }; 483 }; 484 485 out-ports { 486 port { 487 etf_out_port: endpoint { 488 remote-endpoint = <&etr_in_port>; 489 }; 490 }; 491 }; 492 }; 493 494 etr@28c06000 { 495 compatible = "arm,coresight-tmc", "arm,primecell"; 496 reg = <0x28c06000 0x1000>; 497 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 498 clock-names = "apb_pclk"; 499 500 in-ports { 501 port { 502 etr_in_port: endpoint { 503 remote-endpoint = <&etf_out_port>; 504 }; 505 }; 506 }; 507 }; 508 509 aips1: bus@30000000 { 510 compatible = "fsl,aips-bus", "simple-bus"; 511 reg = <0x30000000 0x400000>; 512 #address-cells = <1>; 513 #size-cells = <1>; 514 ranges; 515 516 gpio1: gpio@30200000 { 517 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 518 reg = <0x30200000 0x10000>; 519 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 522 gpio-controller; 523 #gpio-cells = <2>; 524 interrupt-controller; 525 #interrupt-cells = <2>; 526 gpio-ranges = <&iomuxc 0 5 30>; 527 }; 528 529 gpio2: gpio@30210000 { 530 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 531 reg = <0x30210000 0x10000>; 532 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 535 gpio-controller; 536 #gpio-cells = <2>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 gpio-ranges = <&iomuxc 0 35 21>; 540 }; 541 542 gpio3: gpio@30220000 { 543 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 544 reg = <0x30220000 0x10000>; 545 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 548 gpio-controller; 549 #gpio-cells = <2>; 550 interrupt-controller; 551 #interrupt-cells = <2>; 552 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 553 }; 554 555 gpio4: gpio@30230000 { 556 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 557 reg = <0x30230000 0x10000>; 558 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 561 gpio-controller; 562 #gpio-cells = <2>; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 gpio-ranges = <&iomuxc 0 82 32>; 566 }; 567 568 gpio5: gpio@30240000 { 569 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 570 reg = <0x30240000 0x10000>; 571 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 574 gpio-controller; 575 #gpio-cells = <2>; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 gpio-ranges = <&iomuxc 0 114 30>; 579 }; 580 581 tmu: tmu@30260000 { 582 compatible = "fsl,imx8mp-tmu"; 583 reg = <0x30260000 0x10000>; 584 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 585 nvmem-cells = <&tmu_calib>; 586 nvmem-cell-names = "calib"; 587 #thermal-sensor-cells = <1>; 588 }; 589 590 wdog1: watchdog@30280000 { 591 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 592 reg = <0x30280000 0x10000>; 593 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 595 status = "disabled"; 596 }; 597 598 wdog2: watchdog@30290000 { 599 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 600 reg = <0x30290000 0x10000>; 601 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 603 status = "disabled"; 604 }; 605 606 wdog3: watchdog@302a0000 { 607 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 608 reg = <0x302a0000 0x10000>; 609 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 611 status = "disabled"; 612 }; 613 614 gpt1: timer@302d0000 { 615 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 616 reg = <0x302d0000 0x10000>; 617 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; 619 clock-names = "ipg", "per"; 620 }; 621 622 gpt2: timer@302e0000 { 623 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 624 reg = <0x302e0000 0x10000>; 625 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; 627 clock-names = "ipg", "per"; 628 }; 629 630 gpt3: timer@302f0000 { 631 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 632 reg = <0x302f0000 0x10000>; 633 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; 635 clock-names = "ipg", "per"; 636 }; 637 638 iomuxc: pinctrl@30330000 { 639 compatible = "fsl,imx8mp-iomuxc"; 640 reg = <0x30330000 0x10000>; 641 }; 642 643 gpr: syscon@30340000 { 644 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 645 reg = <0x30340000 0x10000>; 646 }; 647 648 ocotp: efuse@30350000 { 649 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 650 reg = <0x30350000 0x10000>; 651 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 652 /* For nvmem subnodes */ 653 #address-cells = <1>; 654 #size-cells = <1>; 655 656 /* 657 * The register address below maps to the MX8M 658 * Fusemap Description Table entries this way. 659 * Assuming 660 * reg = <ADDR SIZE>; 661 * then 662 * Fuse Address = (ADDR * 4) + 0x400 663 * Note that if SIZE is greater than 4, then 664 * each subsequent fuse is located at offset 665 * +0x10 in Fusemap Description Table (e.g. 666 * reg = <0x8 0x8> describes fuses 0x420 and 667 * 0x430). 668 */ 669 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 670 reg = <0x8 0x8>; 671 }; 672 673 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 674 reg = <0x10 4>; 675 }; 676 677 eth_mac1: mac-address@90 { /* 0x640 */ 678 reg = <0x90 6>; 679 }; 680 681 eth_mac2: mac-address@96 { /* 0x658 */ 682 reg = <0x96 6>; 683 }; 684 685 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 686 reg = <0x264 0x10>; 687 }; 688 }; 689 690 anatop: clock-controller@30360000 { 691 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 692 reg = <0x30360000 0x10000>; 693 #clock-cells = <1>; 694 }; 695 696 snvs: snvs@30370000 { 697 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 698 reg = <0x30370000 0x10000>; 699 700 snvs_rtc: snvs-rtc-lp { 701 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 702 regmap = <&snvs>; 703 offset = <0x34>; 704 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 707 clock-names = "snvs-rtc"; 708 }; 709 710 snvs_pwrkey: snvs-powerkey { 711 compatible = "fsl,sec-v4.0-pwrkey"; 712 regmap = <&snvs>; 713 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 715 clock-names = "snvs-pwrkey"; 716 linux,keycode = <KEY_POWER>; 717 wakeup-source; 718 status = "disabled"; 719 }; 720 721 snvs_lpgpr: snvs-lpgpr { 722 compatible = "fsl,imx8mp-snvs-lpgpr", 723 "fsl,imx7d-snvs-lpgpr"; 724 }; 725 }; 726 727 clk: clock-controller@30380000 { 728 compatible = "fsl,imx8mp-ccm"; 729 reg = <0x30380000 0x10000>; 730 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 732 #clock-cells = <1>; 733 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 734 <&clk_ext3>, <&clk_ext4>; 735 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 736 "clk_ext3", "clk_ext4"; 737 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 738 <&clk IMX8MP_CLK_A53_CORE>, 739 <&clk IMX8MP_CLK_NOC>, 740 <&clk IMX8MP_CLK_NOC_IO>, 741 <&clk IMX8MP_CLK_GIC>; 742 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 743 <&clk IMX8MP_ARM_PLL_OUT>, 744 <&clk IMX8MP_SYS_PLL2_1000M>, 745 <&clk IMX8MP_SYS_PLL1_800M>, 746 <&clk IMX8MP_SYS_PLL2_500M>; 747 assigned-clock-rates = <0>, <0>, 748 <1000000000>, 749 <800000000>, 750 <500000000>; 751 }; 752 753 src: reset-controller@30390000 { 754 compatible = "fsl,imx8mp-src", "syscon"; 755 reg = <0x30390000 0x10000>; 756 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 757 #reset-cells = <1>; 758 }; 759 760 gpc: gpc@303a0000 { 761 compatible = "fsl,imx8mp-gpc"; 762 reg = <0x303a0000 0x1000>; 763 interrupt-parent = <&gic>; 764 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-controller; 766 #interrupt-cells = <3>; 767 768 pgc { 769 #address-cells = <1>; 770 #size-cells = <0>; 771 772 pgc_mipi_phy1: power-domain@0 { 773 #power-domain-cells = <0>; 774 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 775 }; 776 777 pgc_pcie_phy: power-domain@1 { 778 #power-domain-cells = <0>; 779 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 780 }; 781 782 pgc_usb1_phy: power-domain@2 { 783 #power-domain-cells = <0>; 784 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 785 }; 786 787 pgc_usb2_phy: power-domain@3 { 788 #power-domain-cells = <0>; 789 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 790 }; 791 792 pgc_audio: power-domain@5 { 793 #power-domain-cells = <0>; 794 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; 795 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 796 <&clk IMX8MP_CLK_AUDIO_AXI>; 797 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, 798 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; 799 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 800 <&clk IMX8MP_SYS_PLL1_800M>; 801 assigned-clock-rates = <400000000>, 802 <600000000>; 803 }; 804 805 pgc_gpu2d: power-domain@6 { 806 #power-domain-cells = <0>; 807 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 808 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 809 power-domains = <&pgc_gpumix>; 810 }; 811 812 pgc_gpumix: power-domain@7 { 813 #power-domain-cells = <0>; 814 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 815 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 816 <&clk IMX8MP_CLK_GPU_AHB>; 817 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 818 <&clk IMX8MP_CLK_GPU_AHB>; 819 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 820 <&clk IMX8MP_SYS_PLL1_800M>; 821 assigned-clock-rates = <800000000>, <400000000>; 822 }; 823 824 pgc_gpu3d: power-domain@9 { 825 #power-domain-cells = <0>; 826 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 827 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 828 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 829 power-domains = <&pgc_gpumix>; 830 }; 831 832 pgc_mediamix: power-domain@10 { 833 #power-domain-cells = <0>; 834 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 835 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 836 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 837 }; 838 839 pgc_hdmimix: power-domain@14 { 840 #power-domain-cells = <0>; 841 reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>; 842 clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, 843 <&clk IMX8MP_CLK_HDMI_APB>; 844 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, 845 <&clk IMX8MP_CLK_HDMI_APB>; 846 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, 847 <&clk IMX8MP_SYS_PLL1_133M>; 848 assigned-clock-rates = <500000000>, <133000000>; 849 }; 850 851 pgc_hdmi_phy: power-domain@15 { 852 #power-domain-cells = <0>; 853 reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>; 854 }; 855 856 pgc_mipi_phy2: power-domain@16 { 857 #power-domain-cells = <0>; 858 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 859 }; 860 861 pgc_hsiomix: power-domain@17 { 862 #power-domain-cells = <0>; 863 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 864 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 865 <&clk IMX8MP_CLK_HSIO_ROOT>; 866 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 867 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 868 assigned-clock-rates = <500000000>; 869 }; 870 871 pgc_ispdwp: power-domain@18 { 872 #power-domain-cells = <0>; 873 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 874 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 875 }; 876 877 pgc_vpumix: power-domain@19 { 878 #power-domain-cells = <0>; 879 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 880 clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 881 }; 882 883 pgc_vpu_g1: power-domain@20 { 884 #power-domain-cells = <0>; 885 power-domains = <&pgc_vpumix>; 886 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 887 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 888 }; 889 890 pgc_vpu_g2: power-domain@21 { 891 #power-domain-cells = <0>; 892 power-domains = <&pgc_vpumix>; 893 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 894 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 895 }; 896 897 pgc_vpu_vc8000e: power-domain@22 { 898 #power-domain-cells = <0>; 899 power-domains = <&pgc_vpumix>; 900 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 901 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 902 }; 903 904 pgc_mlmix: power-domain@24 { 905 #power-domain-cells = <0>; 906 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 907 clocks = <&clk IMX8MP_CLK_ML_AXI>, 908 <&clk IMX8MP_CLK_ML_AHB>, 909 <&clk IMX8MP_CLK_NPU_ROOT>; 910 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, 911 <&clk IMX8MP_CLK_ML_AXI>, 912 <&clk IMX8MP_CLK_ML_AHB>; 913 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 914 <&clk IMX8MP_SYS_PLL1_800M>, 915 <&clk IMX8MP_SYS_PLL1_800M>; 916 assigned-clock-rates = <800000000>, 917 <800000000>, 918 <300000000>; 919 }; 920 }; 921 }; 922 }; 923 924 aips2: bus@30400000 { 925 compatible = "fsl,aips-bus", "simple-bus"; 926 reg = <0x30400000 0x400000>; 927 #address-cells = <1>; 928 #size-cells = <1>; 929 ranges; 930 931 pwm1: pwm@30660000 { 932 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 933 reg = <0x30660000 0x10000>; 934 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 936 <&clk IMX8MP_CLK_PWM1_ROOT>; 937 clock-names = "ipg", "per"; 938 #pwm-cells = <3>; 939 status = "disabled"; 940 }; 941 942 pwm2: pwm@30670000 { 943 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 944 reg = <0x30670000 0x10000>; 945 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 947 <&clk IMX8MP_CLK_PWM2_ROOT>; 948 clock-names = "ipg", "per"; 949 #pwm-cells = <3>; 950 status = "disabled"; 951 }; 952 953 pwm3: pwm@30680000 { 954 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 955 reg = <0x30680000 0x10000>; 956 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 958 <&clk IMX8MP_CLK_PWM3_ROOT>; 959 clock-names = "ipg", "per"; 960 #pwm-cells = <3>; 961 status = "disabled"; 962 }; 963 964 pwm4: pwm@30690000 { 965 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 966 reg = <0x30690000 0x10000>; 967 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 969 <&clk IMX8MP_CLK_PWM4_ROOT>; 970 clock-names = "ipg", "per"; 971 #pwm-cells = <3>; 972 status = "disabled"; 973 }; 974 975 system_counter: timer@306a0000 { 976 compatible = "nxp,sysctr-timer"; 977 reg = <0x306a0000 0x20000>; 978 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&osc_24m>; 980 clock-names = "per"; 981 }; 982 983 gpt6: timer@306e0000 { 984 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 985 reg = <0x306e0000 0x10000>; 986 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; 988 clock-names = "ipg", "per"; 989 }; 990 991 gpt5: timer@306f0000 { 992 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 993 reg = <0x306f0000 0x10000>; 994 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; 996 clock-names = "ipg", "per"; 997 }; 998 999 gpt4: timer@30700000 { 1000 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1001 reg = <0x30700000 0x10000>; 1002 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; 1004 clock-names = "ipg", "per"; 1005 }; 1006 }; 1007 1008 aips3: bus@30800000 { 1009 compatible = "fsl,aips-bus", "simple-bus"; 1010 reg = <0x30800000 0x400000>; 1011 #address-cells = <1>; 1012 #size-cells = <1>; 1013 ranges; 1014 1015 spba-bus@30800000 { 1016 compatible = "fsl,spba-bus", "simple-bus"; 1017 reg = <0x30800000 0x100000>; 1018 #address-cells = <1>; 1019 #size-cells = <1>; 1020 ranges; 1021 1022 ecspi1: spi@30820000 { 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1026 reg = <0x30820000 0x10000>; 1027 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 1029 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 1030 clock-names = "ipg", "per"; 1031 assigned-clock-rates = <80000000>; 1032 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 1033 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1034 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 1035 dma-names = "rx", "tx"; 1036 status = "disabled"; 1037 }; 1038 1039 ecspi2: spi@30830000 { 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1043 reg = <0x30830000 0x10000>; 1044 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 1046 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 1047 clock-names = "ipg", "per"; 1048 assigned-clock-rates = <80000000>; 1049 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 1050 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1051 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 1052 dma-names = "rx", "tx"; 1053 status = "disabled"; 1054 }; 1055 1056 ecspi3: spi@30840000 { 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1060 reg = <0x30840000 0x10000>; 1061 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 1063 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 1064 clock-names = "ipg", "per"; 1065 assigned-clock-rates = <80000000>; 1066 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 1067 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1068 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 1069 dma-names = "rx", "tx"; 1070 status = "disabled"; 1071 }; 1072 1073 uart1: serial@30860000 { 1074 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1075 reg = <0x30860000 0x10000>; 1076 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1077 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 1078 <&clk IMX8MP_CLK_UART1_ROOT>; 1079 clock-names = "ipg", "per"; 1080 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 1081 dma-names = "rx", "tx"; 1082 status = "disabled"; 1083 }; 1084 1085 uart3: serial@30880000 { 1086 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1087 reg = <0x30880000 0x10000>; 1088 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1089 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 1090 <&clk IMX8MP_CLK_UART3_ROOT>; 1091 clock-names = "ipg", "per"; 1092 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 1093 dma-names = "rx", "tx"; 1094 status = "disabled"; 1095 }; 1096 1097 uart2: serial@30890000 { 1098 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1099 reg = <0x30890000 0x10000>; 1100 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1101 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 1102 <&clk IMX8MP_CLK_UART2_ROOT>; 1103 clock-names = "ipg", "per"; 1104 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 1105 dma-names = "rx", "tx"; 1106 status = "disabled"; 1107 }; 1108 1109 flexcan1: can@308c0000 { 1110 compatible = "fsl,imx8mp-flexcan"; 1111 reg = <0x308c0000 0x10000>; 1112 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1114 <&clk IMX8MP_CLK_CAN1_ROOT>; 1115 clock-names = "ipg", "per"; 1116 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 1117 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1118 assigned-clock-rates = <40000000>; 1119 fsl,clk-source = /bits/ 8 <0>; 1120 fsl,stop-mode = <&gpr 0x10 4>; 1121 status = "disabled"; 1122 }; 1123 1124 flexcan2: can@308d0000 { 1125 compatible = "fsl,imx8mp-flexcan"; 1126 reg = <0x308d0000 0x10000>; 1127 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1129 <&clk IMX8MP_CLK_CAN2_ROOT>; 1130 clock-names = "ipg", "per"; 1131 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 1132 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1133 assigned-clock-rates = <40000000>; 1134 fsl,clk-source = /bits/ 8 <0>; 1135 fsl,stop-mode = <&gpr 0x10 5>; 1136 status = "disabled"; 1137 }; 1138 }; 1139 1140 crypto: crypto@30900000 { 1141 compatible = "fsl,sec-v4.0"; 1142 #address-cells = <1>; 1143 #size-cells = <1>; 1144 reg = <0x30900000 0x40000>; 1145 ranges = <0 0x30900000 0x40000>; 1146 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1147 clocks = <&clk IMX8MP_CLK_AHB>, 1148 <&clk IMX8MP_CLK_IPG_ROOT>; 1149 clock-names = "aclk", "ipg"; 1150 1151 sec_jr0: jr@1000 { 1152 compatible = "fsl,sec-v4.0-job-ring"; 1153 reg = <0x1000 0x1000>; 1154 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1155 status = "disabled"; 1156 }; 1157 1158 sec_jr1: jr@2000 { 1159 compatible = "fsl,sec-v4.0-job-ring"; 1160 reg = <0x2000 0x1000>; 1161 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1162 }; 1163 1164 sec_jr2: jr@3000 { 1165 compatible = "fsl,sec-v4.0-job-ring"; 1166 reg = <0x3000 0x1000>; 1167 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1168 }; 1169 }; 1170 1171 i2c1: i2c@30a20000 { 1172 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 reg = <0x30a20000 0x10000>; 1176 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 1178 status = "disabled"; 1179 }; 1180 1181 i2c2: i2c@30a30000 { 1182 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 reg = <0x30a30000 0x10000>; 1186 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 1188 status = "disabled"; 1189 }; 1190 1191 i2c3: i2c@30a40000 { 1192 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 reg = <0x30a40000 0x10000>; 1196 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1197 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 1198 status = "disabled"; 1199 }; 1200 1201 i2c4: i2c@30a50000 { 1202 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 reg = <0x30a50000 0x10000>; 1206 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 1208 status = "disabled"; 1209 }; 1210 1211 uart4: serial@30a60000 { 1212 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1213 reg = <0x30a60000 0x10000>; 1214 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 1216 <&clk IMX8MP_CLK_UART4_ROOT>; 1217 clock-names = "ipg", "per"; 1218 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1219 dma-names = "rx", "tx"; 1220 status = "disabled"; 1221 }; 1222 1223 mu: mailbox@30aa0000 { 1224 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1225 reg = <0x30aa0000 0x10000>; 1226 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 1228 #mbox-cells = <2>; 1229 }; 1230 1231 mu2: mailbox@30e60000 { 1232 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1233 reg = <0x30e60000 0x10000>; 1234 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1235 #mbox-cells = <2>; 1236 status = "disabled"; 1237 }; 1238 1239 i2c5: i2c@30ad0000 { 1240 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 reg = <0x30ad0000 0x10000>; 1244 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 1246 status = "disabled"; 1247 }; 1248 1249 i2c6: i2c@30ae0000 { 1250 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 reg = <0x30ae0000 0x10000>; 1254 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 1256 status = "disabled"; 1257 }; 1258 1259 usdhc1: mmc@30b40000 { 1260 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1261 reg = <0x30b40000 0x10000>; 1262 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1263 clocks = <&clk IMX8MP_CLK_DUMMY>, 1264 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1265 <&clk IMX8MP_CLK_USDHC1_ROOT>; 1266 clock-names = "ipg", "ahb", "per"; 1267 fsl,tuning-start-tap = <20>; 1268 fsl,tuning-step = <2>; 1269 bus-width = <4>; 1270 status = "disabled"; 1271 }; 1272 1273 usdhc2: mmc@30b50000 { 1274 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1275 reg = <0x30b50000 0x10000>; 1276 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1277 clocks = <&clk IMX8MP_CLK_DUMMY>, 1278 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1279 <&clk IMX8MP_CLK_USDHC2_ROOT>; 1280 clock-names = "ipg", "ahb", "per"; 1281 fsl,tuning-start-tap = <20>; 1282 fsl,tuning-step = <2>; 1283 bus-width = <4>; 1284 status = "disabled"; 1285 }; 1286 1287 usdhc3: mmc@30b60000 { 1288 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1289 reg = <0x30b60000 0x10000>; 1290 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1291 clocks = <&clk IMX8MP_CLK_DUMMY>, 1292 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1293 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1294 clock-names = "ipg", "ahb", "per"; 1295 fsl,tuning-start-tap = <20>; 1296 fsl,tuning-step = <2>; 1297 bus-width = <4>; 1298 status = "disabled"; 1299 }; 1300 1301 flexspi: spi@30bb0000 { 1302 compatible = "nxp,imx8mp-fspi"; 1303 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1304 reg-names = "fspi_base", "fspi_mmap"; 1305 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1306 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1307 <&clk IMX8MP_CLK_QSPI_ROOT>; 1308 clock-names = "fspi_en", "fspi"; 1309 assigned-clock-rates = <80000000>; 1310 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 status = "disabled"; 1314 }; 1315 1316 sdma1: dma-controller@30bd0000 { 1317 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1318 reg = <0x30bd0000 0x10000>; 1319 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1320 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1321 <&clk IMX8MP_CLK_AHB>; 1322 clock-names = "ipg", "ahb"; 1323 #dma-cells = <3>; 1324 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1325 }; 1326 1327 fec: ethernet@30be0000 { 1328 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1329 reg = <0x30be0000 0x10000>; 1330 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1334 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1335 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1336 <&clk IMX8MP_CLK_ENET_TIMER>, 1337 <&clk IMX8MP_CLK_ENET_REF>, 1338 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1339 clock-names = "ipg", "ahb", "ptp", 1340 "enet_clk_ref", "enet_out"; 1341 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1342 <&clk IMX8MP_CLK_ENET_TIMER>, 1343 <&clk IMX8MP_CLK_ENET_REF>, 1344 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1345 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1346 <&clk IMX8MP_SYS_PLL2_100M>, 1347 <&clk IMX8MP_SYS_PLL2_125M>, 1348 <&clk IMX8MP_SYS_PLL2_50M>; 1349 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1350 fsl,num-tx-queues = <3>; 1351 fsl,num-rx-queues = <3>; 1352 nvmem-cells = <ð_mac1>; 1353 nvmem-cell-names = "mac-address"; 1354 fsl,stop-mode = <&gpr 0x10 3>; 1355 status = "disabled"; 1356 }; 1357 1358 eqos: ethernet@30bf0000 { 1359 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1360 reg = <0x30bf0000 0x10000>; 1361 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1363 interrupt-names = "macirq", "eth_wake_irq"; 1364 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1365 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1366 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1367 <&clk IMX8MP_CLK_ENET_QOS>; 1368 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1369 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1370 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1371 <&clk IMX8MP_CLK_ENET_QOS>; 1372 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1373 <&clk IMX8MP_SYS_PLL2_100M>, 1374 <&clk IMX8MP_SYS_PLL2_125M>; 1375 assigned-clock-rates = <0>, <100000000>, <125000000>; 1376 nvmem-cells = <ð_mac2>; 1377 nvmem-cell-names = "mac-address"; 1378 intf_mode = <&gpr 0x4>; 1379 status = "disabled"; 1380 }; 1381 }; 1382 1383 aips5: bus@30c00000 { 1384 compatible = "fsl,aips-bus", "simple-bus"; 1385 reg = <0x30c00000 0x400000>; 1386 #address-cells = <1>; 1387 #size-cells = <1>; 1388 ranges; 1389 1390 spba-bus@30c00000 { 1391 compatible = "fsl,spba-bus", "simple-bus"; 1392 reg = <0x30c00000 0x100000>; 1393 #address-cells = <1>; 1394 #size-cells = <1>; 1395 ranges; 1396 1397 sai1: sai@30c10000 { 1398 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1399 reg = <0x30c10000 0x10000>; 1400 #sound-dai-cells = <0>; 1401 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, 1402 <&clk IMX8MP_CLK_DUMMY>, 1403 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, 1404 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, 1405 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; 1406 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1407 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 1408 dma-names = "rx", "tx"; 1409 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1410 status = "disabled"; 1411 }; 1412 1413 sai2: sai@30c20000 { 1414 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1415 reg = <0x30c20000 0x10000>; 1416 #sound-dai-cells = <0>; 1417 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, 1418 <&clk IMX8MP_CLK_DUMMY>, 1419 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, 1420 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, 1421 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; 1422 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1423 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 1424 dma-names = "rx", "tx"; 1425 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1426 status = "disabled"; 1427 }; 1428 1429 sai3: sai@30c30000 { 1430 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1431 reg = <0x30c30000 0x10000>; 1432 #sound-dai-cells = <0>; 1433 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, 1434 <&clk IMX8MP_CLK_DUMMY>, 1435 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, 1436 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, 1437 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; 1438 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1439 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 1440 dma-names = "rx", "tx"; 1441 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1442 status = "disabled"; 1443 }; 1444 1445 sai5: sai@30c50000 { 1446 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1447 reg = <0x30c50000 0x10000>; 1448 #sound-dai-cells = <0>; 1449 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, 1450 <&clk IMX8MP_CLK_DUMMY>, 1451 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, 1452 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, 1453 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; 1454 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1455 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 1456 dma-names = "rx", "tx"; 1457 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1458 status = "disabled"; 1459 }; 1460 1461 sai6: sai@30c60000 { 1462 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1463 reg = <0x30c60000 0x10000>; 1464 #sound-dai-cells = <0>; 1465 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, 1466 <&clk IMX8MP_CLK_DUMMY>, 1467 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, 1468 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, 1469 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; 1470 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1471 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 1472 dma-names = "rx", "tx"; 1473 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1474 status = "disabled"; 1475 }; 1476 1477 sai7: sai@30c80000 { 1478 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1479 reg = <0x30c80000 0x10000>; 1480 #sound-dai-cells = <0>; 1481 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, 1482 <&clk IMX8MP_CLK_DUMMY>, 1483 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, 1484 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, 1485 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; 1486 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1487 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 1488 dma-names = "rx", "tx"; 1489 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1490 status = "disabled"; 1491 }; 1492 1493 easrc: easrc@30c90000 { 1494 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc"; 1495 reg = <0x30c90000 0x10000>; 1496 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; 1498 clock-names = "mem"; 1499 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 1500 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 1501 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 1502 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 1503 dma-names = "ctx0_rx", "ctx0_tx", 1504 "ctx1_rx", "ctx1_tx", 1505 "ctx2_rx", "ctx2_tx", 1506 "ctx3_rx", "ctx3_tx"; 1507 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 1508 fsl,asrc-rate = <8000>; 1509 fsl,asrc-format = <2>; 1510 status = "disabled"; 1511 }; 1512 1513 micfil: audio-controller@30ca0000 { 1514 compatible = "fsl,imx8mp-micfil"; 1515 reg = <0x30ca0000 0x10000>; 1516 #sound-dai-cells = <0>; 1517 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1521 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>, 1522 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>, 1523 <&clk IMX8MP_AUDIO_PLL1_OUT>, 1524 <&clk IMX8MP_AUDIO_PLL2_OUT>, 1525 <&clk IMX8MP_CLK_EXT3>; 1526 clock-names = "ipg_clk", "ipg_clk_app", 1527 "pll8k", "pll11k", "clkext3"; 1528 dmas = <&sdma2 24 25 0x80000000>; 1529 dma-names = "rx"; 1530 status = "disabled"; 1531 }; 1532 1533 aud2htx: aud2htx@30cb0000 { 1534 compatible = "fsl,imx8mp-aud2htx"; 1535 reg = <0x30cb0000 0x10000>; 1536 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 1537 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; 1538 clock-names = "bus"; 1539 dmas = <&sdma2 26 2 0>; 1540 dma-names = "tx"; 1541 status = "disabled"; 1542 }; 1543 }; 1544 1545 sdma3: dma-controller@30e00000 { 1546 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1547 reg = <0x30e00000 0x10000>; 1548 #dma-cells = <3>; 1549 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, 1550 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1551 clock-names = "ipg", "ahb"; 1552 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1553 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1554 }; 1555 1556 sdma2: dma-controller@30e10000 { 1557 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1558 reg = <0x30e10000 0x10000>; 1559 #dma-cells = <3>; 1560 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, 1561 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1562 clock-names = "ipg", "ahb"; 1563 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1564 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1565 }; 1566 1567 audio_blk_ctrl: clock-controller@30e20000 { 1568 compatible = "fsl,imx8mp-audio-blk-ctrl"; 1569 reg = <0x30e20000 0x10000>; 1570 #clock-cells = <1>; 1571 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 1572 <&clk IMX8MP_CLK_SAI1>, 1573 <&clk IMX8MP_CLK_SAI2>, 1574 <&clk IMX8MP_CLK_SAI3>, 1575 <&clk IMX8MP_CLK_SAI5>, 1576 <&clk IMX8MP_CLK_SAI6>, 1577 <&clk IMX8MP_CLK_SAI7>; 1578 clock-names = "ahb", 1579 "sai1", "sai2", "sai3", 1580 "sai5", "sai6", "sai7"; 1581 power-domains = <&pgc_audio>; 1582 }; 1583 }; 1584 1585 noc: interconnect@32700000 { 1586 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1587 reg = <0x32700000 0x100000>; 1588 clocks = <&clk IMX8MP_CLK_NOC>; 1589 #interconnect-cells = <1>; 1590 operating-points-v2 = <&noc_opp_table>; 1591 1592 noc_opp_table: opp-table { 1593 compatible = "operating-points-v2"; 1594 1595 opp-200000000 { 1596 opp-hz = /bits/ 64 <200000000>; 1597 }; 1598 1599 opp-1000000000 { 1600 opp-hz = /bits/ 64 <1000000000>; 1601 }; 1602 }; 1603 }; 1604 1605 aips4: bus@32c00000 { 1606 compatible = "fsl,aips-bus", "simple-bus"; 1607 reg = <0x32c00000 0x400000>; 1608 #address-cells = <1>; 1609 #size-cells = <1>; 1610 ranges; 1611 1612 isi_0: isi@32e00000 { 1613 compatible = "fsl,imx8mp-isi"; 1614 reg = <0x32e00000 0x4000>; 1615 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1617 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1618 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1619 clock-names = "axi", "apb"; 1620 fsl,blk-ctrl = <&media_blk_ctrl>; 1621 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; 1622 status = "disabled"; 1623 1624 ports { 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 1628 port@0 { 1629 reg = <0>; 1630 1631 isi_in_0: endpoint { 1632 remote-endpoint = <&mipi_csi_0_out>; 1633 }; 1634 }; 1635 1636 port@1 { 1637 reg = <1>; 1638 1639 isi_in_1: endpoint { 1640 remote-endpoint = <&mipi_csi_1_out>; 1641 }; 1642 }; 1643 }; 1644 }; 1645 1646 dewarp: dwe@32e30000 { 1647 compatible = "nxp,imx8mp-dw100"; 1648 reg = <0x32e30000 0x10000>; 1649 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1651 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1652 clock-names = "axi", "ahb"; 1653 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; 1654 }; 1655 1656 mipi_csi_0: csi@32e40000 { 1657 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1658 reg = <0x32e40000 0x10000>; 1659 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1660 clock-frequency = <266000000>; 1661 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1662 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1663 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1664 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1665 clock-names = "pclk", "wrap", "phy", "axi"; 1666 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, 1667 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1668 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1669 <&clk IMX8MP_CLK_24M>; 1670 assigned-clock-rates = <266000000>; 1671 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; 1672 status = "disabled"; 1673 1674 ports { 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 1678 port@0 { 1679 reg = <0>; 1680 }; 1681 1682 port@1 { 1683 reg = <1>; 1684 1685 mipi_csi_0_out: endpoint { 1686 remote-endpoint = <&isi_in_0>; 1687 }; 1688 }; 1689 }; 1690 }; 1691 1692 mipi_csi_1: csi@32e50000 { 1693 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1694 reg = <0x32e50000 0x10000>; 1695 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1696 clock-frequency = <266000000>; 1697 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1698 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1699 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1700 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1701 clock-names = "pclk", "wrap", "phy", "axi"; 1702 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, 1703 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1704 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1705 <&clk IMX8MP_CLK_24M>; 1706 assigned-clock-rates = <266000000>; 1707 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; 1708 status = "disabled"; 1709 1710 ports { 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 1714 port@0 { 1715 reg = <0>; 1716 }; 1717 1718 port@1 { 1719 reg = <1>; 1720 1721 mipi_csi_1_out: endpoint { 1722 remote-endpoint = <&isi_in_1>; 1723 }; 1724 }; 1725 }; 1726 }; 1727 1728 mipi_dsi: dsi@32e60000 { 1729 compatible = "fsl,imx8mp-mipi-dsim"; 1730 reg = <0x32e60000 0x400>; 1731 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1732 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1733 clock-names = "bus_clk", "sclk_mipi"; 1734 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, 1735 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1736 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1737 <&clk IMX8MP_CLK_24M>; 1738 assigned-clock-rates = <200000000>, <24000000>; 1739 samsung,pll-clock-frequency = <24000000>; 1740 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1741 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; 1742 status = "disabled"; 1743 1744 ports { 1745 #address-cells = <1>; 1746 #size-cells = <0>; 1747 1748 port@0 { 1749 reg = <0>; 1750 1751 dsim_from_lcdif1: endpoint { 1752 remote-endpoint = <&lcdif1_to_dsim>; 1753 }; 1754 }; 1755 1756 port@1 { 1757 reg = <1>; 1758 1759 mipi_dsi_out: endpoint { 1760 }; 1761 }; 1762 }; 1763 }; 1764 1765 lcdif1: display-controller@32e80000 { 1766 compatible = "fsl,imx8mp-lcdif"; 1767 reg = <0x32e80000 0x10000>; 1768 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1769 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1770 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1771 clock-names = "pix", "axi", "disp_axi"; 1772 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1773 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; 1774 status = "disabled"; 1775 1776 port { 1777 lcdif1_to_dsim: endpoint { 1778 remote-endpoint = <&dsim_from_lcdif1>; 1779 }; 1780 }; 1781 }; 1782 1783 lcdif2: display-controller@32e90000 { 1784 compatible = "fsl,imx8mp-lcdif"; 1785 reg = <0x32e90000 0x10000>; 1786 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1787 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1788 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1789 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1790 clock-names = "pix", "axi", "disp_axi"; 1791 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1792 status = "disabled"; 1793 1794 port { 1795 lcdif2_to_ldb: endpoint { 1796 remote-endpoint = <&ldb_from_lcdif2>; 1797 }; 1798 }; 1799 }; 1800 1801 media_blk_ctrl: blk-ctrl@32ec0000 { 1802 compatible = "fsl,imx8mp-media-blk-ctrl", 1803 "syscon"; 1804 reg = <0x32ec0000 0x10000>; 1805 #address-cells = <1>; 1806 #size-cells = <1>; 1807 power-domains = <&pgc_mediamix>, 1808 <&pgc_mipi_phy1>, 1809 <&pgc_mipi_phy1>, 1810 <&pgc_mediamix>, 1811 <&pgc_mediamix>, 1812 <&pgc_mipi_phy2>, 1813 <&pgc_mediamix>, 1814 <&pgc_ispdwp>, 1815 <&pgc_ispdwp>, 1816 <&pgc_mipi_phy2>; 1817 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1818 "lcdif1", "isi", "mipi-csi2", 1819 "lcdif2", "isp", "dwe", 1820 "mipi-dsi2"; 1821 interconnects = 1822 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1823 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1824 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1825 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1826 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1827 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1828 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1829 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1830 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1831 "isi1", "isi2", "isp0", "isp1", 1832 "dwe"; 1833 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1834 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1835 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1836 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1837 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1838 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1839 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1840 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1841 clock-names = "apb", "axi", "cam1", "cam2", 1842 "disp1", "disp2", "isp", "phy"; 1843 1844 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1845 <&clk IMX8MP_CLK_MEDIA_APB>, 1846 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, 1847 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1848 <&clk IMX8MP_VIDEO_PLL1>; 1849 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1850 <&clk IMX8MP_SYS_PLL1_800M>, 1851 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1852 <&clk IMX8MP_VIDEO_PLL1_OUT>; 1853 assigned-clock-rates = <500000000>, <200000000>, 1854 <0>, <0>, <1039500000>; 1855 #power-domain-cells = <1>; 1856 1857 lvds_bridge: bridge@5c { 1858 compatible = "fsl,imx8mp-ldb"; 1859 reg = <0x5c 0x4>, <0x128 0x4>; 1860 reg-names = "ldb", "lvds"; 1861 clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; 1862 clock-names = "ldb"; 1863 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1864 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 1865 status = "disabled"; 1866 1867 ports { 1868 #address-cells = <1>; 1869 #size-cells = <0>; 1870 1871 port@0 { 1872 reg = <0>; 1873 1874 ldb_from_lcdif2: endpoint { 1875 remote-endpoint = <&lcdif2_to_ldb>; 1876 }; 1877 }; 1878 1879 port@1 { 1880 reg = <1>; 1881 1882 ldb_lvds_ch0: endpoint { 1883 }; 1884 }; 1885 1886 port@2 { 1887 reg = <2>; 1888 1889 ldb_lvds_ch1: endpoint { 1890 }; 1891 }; 1892 }; 1893 }; 1894 }; 1895 1896 pcie_phy: pcie-phy@32f00000 { 1897 compatible = "fsl,imx8mp-pcie-phy"; 1898 reg = <0x32f00000 0x10000>; 1899 resets = <&src IMX8MP_RESET_PCIEPHY>, 1900 <&src IMX8MP_RESET_PCIEPHY_PERST>; 1901 reset-names = "pciephy", "perst"; 1902 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 1903 #phy-cells = <0>; 1904 status = "disabled"; 1905 }; 1906 1907 hsio_blk_ctrl: blk-ctrl@32f10000 { 1908 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 1909 reg = <0x32f10000 0x24>; 1910 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1911 <&clk IMX8MP_CLK_PCIE_ROOT>; 1912 clock-names = "usb", "pcie"; 1913 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 1914 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 1915 <&pgc_hsiomix>, <&pgc_pcie_phy>; 1916 power-domain-names = "bus", "usb", "usb-phy1", 1917 "usb-phy2", "pcie", "pcie-phy"; 1918 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 1919 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 1920 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 1921 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 1922 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 1923 #power-domain-cells = <1>; 1924 #clock-cells = <0>; 1925 }; 1926 1927 hdmi_blk_ctrl: blk-ctrl@32fc0000 { 1928 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; 1929 reg = <0x32fc0000 0x1000>; 1930 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 1931 <&clk IMX8MP_CLK_HDMI_ROOT>, 1932 <&clk IMX8MP_CLK_HDMI_REF_266M>, 1933 <&clk IMX8MP_CLK_HDMI_24M>, 1934 <&clk IMX8MP_CLK_HDMI_FDCC_TST>; 1935 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; 1936 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, 1937 <&pgc_hdmimix>, <&pgc_hdmimix>, 1938 <&pgc_hdmimix>, <&pgc_hdmimix>, 1939 <&pgc_hdmimix>, <&pgc_hdmi_phy>, 1940 <&pgc_hdmimix>, <&pgc_hdmimix>; 1941 power-domain-names = "bus", "irqsteer", "lcdif", 1942 "pai", "pvi", "trng", 1943 "hdmi-tx", "hdmi-tx-phy", 1944 "hdcp", "hrv"; 1945 #power-domain-cells = <1>; 1946 }; 1947 1948 irqsteer_hdmi: interrupt-controller@32fc2000 { 1949 compatible = "fsl,imx-irqsteer"; 1950 reg = <0x32fc2000 0x1000>; 1951 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1952 interrupt-controller; 1953 #interrupt-cells = <1>; 1954 fsl,channel = <1>; 1955 fsl,num-irqs = <64>; 1956 clocks = <&clk IMX8MP_CLK_HDMI_APB>; 1957 clock-names = "ipg"; 1958 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; 1959 }; 1960 1961 hdmi_pvi: display-bridge@32fc4000 { 1962 compatible = "fsl,imx8mp-hdmi-pvi"; 1963 reg = <0x32fc4000 0x1000>; 1964 interrupt-parent = <&irqsteer_hdmi>; 1965 interrupts = <12>; 1966 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; 1967 status = "disabled"; 1968 1969 ports { 1970 #address-cells = <1>; 1971 #size-cells = <0>; 1972 1973 port@0 { 1974 reg = <0>; 1975 pvi_from_lcdif3: endpoint { 1976 remote-endpoint = <&lcdif3_to_pvi>; 1977 }; 1978 }; 1979 1980 port@1 { 1981 reg = <1>; 1982 pvi_to_hdmi_tx: endpoint { 1983 remote-endpoint = <&hdmi_tx_from_pvi>; 1984 }; 1985 }; 1986 }; 1987 }; 1988 1989 lcdif3: display-controller@32fc6000 { 1990 compatible = "fsl,imx8mp-lcdif"; 1991 reg = <0x32fc6000 0x1000>; 1992 interrupt-parent = <&irqsteer_hdmi>; 1993 interrupts = <8>; 1994 clocks = <&hdmi_tx_phy>, 1995 <&clk IMX8MP_CLK_HDMI_APB>, 1996 <&clk IMX8MP_CLK_HDMI_ROOT>; 1997 clock-names = "pix", "axi", "disp_axi"; 1998 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; 1999 status = "disabled"; 2000 2001 port { 2002 lcdif3_to_pvi: endpoint { 2003 remote-endpoint = <&pvi_from_lcdif3>; 2004 }; 2005 }; 2006 }; 2007 2008 hdmi_tx: hdmi@32fd8000 { 2009 compatible = "fsl,imx8mp-hdmi-tx"; 2010 reg = <0x32fd8000 0x7eff>; 2011 interrupt-parent = <&irqsteer_hdmi>; 2012 interrupts = <0>; 2013 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2014 <&clk IMX8MP_CLK_HDMI_REF_266M>, 2015 <&clk IMX8MP_CLK_32K>, 2016 <&hdmi_tx_phy>; 2017 clock-names = "iahb", "isfr", "cec", "pix"; 2018 assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; 2019 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; 2020 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; 2021 reg-io-width = <1>; 2022 status = "disabled"; 2023 2024 ports { 2025 #address-cells = <1>; 2026 #size-cells = <0>; 2027 2028 port@0 { 2029 reg = <0>; 2030 2031 hdmi_tx_from_pvi: endpoint { 2032 remote-endpoint = <&pvi_to_hdmi_tx>; 2033 }; 2034 }; 2035 2036 port@1 { 2037 reg = <1>; 2038 /* Point endpoint to the HDMI connector */ 2039 }; 2040 }; 2041 }; 2042 2043 hdmi_tx_phy: phy@32fdff00 { 2044 compatible = "fsl,imx8mp-hdmi-phy"; 2045 reg = <0x32fdff00 0x100>; 2046 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2047 <&clk IMX8MP_CLK_HDMI_24M>; 2048 clock-names = "apb", "ref"; 2049 assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; 2050 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2051 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; 2052 #clock-cells = <0>; 2053 #phy-cells = <0>; 2054 status = "disabled"; 2055 }; 2056 }; 2057 2058 pcie: pcie@33800000 { 2059 compatible = "fsl,imx8mp-pcie"; 2060 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 2061 reg-names = "dbi", "config"; 2062 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2063 <&clk IMX8MP_CLK_HSIO_AXI>, 2064 <&clk IMX8MP_CLK_PCIE_ROOT>; 2065 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2066 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2067 assigned-clock-rates = <10000000>; 2068 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2069 #address-cells = <3>; 2070 #size-cells = <2>; 2071 device_type = "pci"; 2072 bus-range = <0x00 0xff>; 2073 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 2074 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 2075 num-lanes = <1>; 2076 num-viewport = <4>; 2077 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2078 interrupt-names = "msi"; 2079 #interrupt-cells = <1>; 2080 interrupt-map-mask = <0 0 0 0x7>; 2081 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2082 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2083 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2084 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2085 fsl,max-link-speed = <3>; 2086 linux,pci-domain = <0>; 2087 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2088 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2089 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2090 reset-names = "apps", "turnoff"; 2091 phys = <&pcie_phy>; 2092 phy-names = "pcie-phy"; 2093 status = "disabled"; 2094 }; 2095 2096 pcie_ep: pcie-ep@33800000 { 2097 compatible = "fsl,imx8mp-pcie-ep"; 2098 reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; 2099 reg-names = "dbi", "addr_space"; 2100 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2101 <&clk IMX8MP_CLK_HSIO_AXI>, 2102 <&clk IMX8MP_CLK_PCIE_ROOT>; 2103 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2104 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2105 assigned-clock-rates = <10000000>; 2106 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2107 num-lanes = <1>; 2108 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 2109 interrupt-names = "dma"; 2110 fsl,max-link-speed = <3>; 2111 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2112 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2113 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2114 reset-names = "apps", "turnoff"; 2115 phys = <&pcie_phy>; 2116 phy-names = "pcie-phy"; 2117 num-ib-windows = <4>; 2118 num-ob-windows = <4>; 2119 status = "disabled"; 2120 }; 2121 2122 gpu3d: gpu@38000000 { 2123 compatible = "vivante,gc"; 2124 reg = <0x38000000 0x8000>; 2125 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 2126 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 2127 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 2128 <&clk IMX8MP_CLK_GPU_ROOT>, 2129 <&clk IMX8MP_CLK_GPU_AHB>; 2130 clock-names = "core", "shader", "bus", "reg"; 2131 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 2132 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 2133 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 2134 <&clk IMX8MP_SYS_PLL1_800M>; 2135 assigned-clock-rates = <800000000>, <800000000>; 2136 power-domains = <&pgc_gpu3d>; 2137 }; 2138 2139 gpu2d: gpu@38008000 { 2140 compatible = "vivante,gc"; 2141 reg = <0x38008000 0x8000>; 2142 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2143 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 2144 <&clk IMX8MP_CLK_GPU_ROOT>, 2145 <&clk IMX8MP_CLK_GPU_AHB>; 2146 clock-names = "core", "bus", "reg"; 2147 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 2148 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 2149 assigned-clock-rates = <800000000>; 2150 power-domains = <&pgc_gpu2d>; 2151 }; 2152 2153 vpu_g1: video-codec@38300000 { 2154 compatible = "nxp,imx8mm-vpu-g1"; 2155 reg = <0x38300000 0x10000>; 2156 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2157 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 2158 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 2159 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2160 assigned-clock-rates = <600000000>; 2161 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 2162 }; 2163 2164 vpu_g2: video-codec@38310000 { 2165 compatible = "nxp,imx8mq-vpu-g2"; 2166 reg = <0x38310000 0x10000>; 2167 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2168 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 2169 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; 2170 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 2171 assigned-clock-rates = <500000000>; 2172 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 2173 }; 2174 2175 vpumix_blk_ctrl: blk-ctrl@38330000 { 2176 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 2177 reg = <0x38330000 0x100>; 2178 #power-domain-cells = <1>; 2179 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 2180 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 2181 power-domain-names = "bus", "g1", "g2", "vc8000e"; 2182 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 2183 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 2184 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 2185 clock-names = "g1", "g2", "vc8000e"; 2186 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; 2187 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2188 assigned-clock-rates = <600000000>, <600000000>; 2189 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 2190 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 2191 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 2192 interconnect-names = "g1", "g2", "vc8000e"; 2193 }; 2194 2195 npu: npu@38500000 { 2196 compatible = "vivante,gc"; 2197 reg = <0x38500000 0x200000>; 2198 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2199 clocks = <&clk IMX8MP_CLK_NPU_ROOT>, 2200 <&clk IMX8MP_CLK_NPU_ROOT>, 2201 <&clk IMX8MP_CLK_ML_AXI>, 2202 <&clk IMX8MP_CLK_ML_AHB>; 2203 clock-names = "core", "shader", "bus", "reg"; 2204 power-domains = <&pgc_mlmix>; 2205 }; 2206 2207 gic: interrupt-controller@38800000 { 2208 compatible = "arm,gic-v3"; 2209 reg = <0x38800000 0x10000>, 2210 <0x38880000 0xc0000>; 2211 #interrupt-cells = <3>; 2212 interrupt-controller; 2213 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2214 interrupt-parent = <&gic>; 2215 }; 2216 2217 edacmc: memory-controller@3d400000 { 2218 compatible = "snps,ddrc-3.80a"; 2219 reg = <0x3d400000 0x400000>; 2220 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2221 }; 2222 2223 ddr-pmu@3d800000 { 2224 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 2225 reg = <0x3d800000 0x400000>; 2226 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2227 }; 2228 2229 usb3_phy0: usb-phy@381f0040 { 2230 compatible = "fsl,imx8mp-usb-phy"; 2231 reg = <0x381f0040 0x40>; 2232 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2233 clock-names = "phy"; 2234 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2235 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2236 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 2237 #phy-cells = <0>; 2238 status = "disabled"; 2239 }; 2240 2241 usb3_0: usb@32f10100 { 2242 compatible = "fsl,imx8mp-dwc3"; 2243 reg = <0x32f10100 0x8>, 2244 <0x381f0000 0x20>; 2245 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2246 <&clk IMX8MP_CLK_USB_SUSP>; 2247 clock-names = "hsio", "suspend"; 2248 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2249 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2250 #address-cells = <1>; 2251 #size-cells = <1>; 2252 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2253 ranges; 2254 status = "disabled"; 2255 2256 usb_dwc3_0: usb@38100000 { 2257 compatible = "snps,dwc3"; 2258 reg = <0x38100000 0x10000>; 2259 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2260 <&clk IMX8MP_CLK_USB_CORE_REF>, 2261 <&clk IMX8MP_CLK_USB_SUSP>; 2262 clock-names = "bus_early", "ref", "suspend"; 2263 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2264 phys = <&usb3_phy0>, <&usb3_phy0>; 2265 phy-names = "usb2-phy", "usb3-phy"; 2266 snps,gfladj-refclk-lpm-sel-quirk; 2267 snps,parkmode-disable-ss-quirk; 2268 }; 2269 2270 }; 2271 2272 usb3_phy1: usb-phy@382f0040 { 2273 compatible = "fsl,imx8mp-usb-phy"; 2274 reg = <0x382f0040 0x40>; 2275 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2276 clock-names = "phy"; 2277 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2278 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2279 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 2280 #phy-cells = <0>; 2281 status = "disabled"; 2282 }; 2283 2284 usb3_1: usb@32f10108 { 2285 compatible = "fsl,imx8mp-dwc3"; 2286 reg = <0x32f10108 0x8>, 2287 <0x382f0000 0x20>; 2288 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2289 <&clk IMX8MP_CLK_USB_SUSP>; 2290 clock-names = "hsio", "suspend"; 2291 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 2292 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2293 #address-cells = <1>; 2294 #size-cells = <1>; 2295 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2296 ranges; 2297 status = "disabled"; 2298 2299 usb_dwc3_1: usb@38200000 { 2300 compatible = "snps,dwc3"; 2301 reg = <0x38200000 0x10000>; 2302 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2303 <&clk IMX8MP_CLK_USB_CORE_REF>, 2304 <&clk IMX8MP_CLK_USB_SUSP>; 2305 clock-names = "bus_early", "ref", "suspend"; 2306 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 2307 phys = <&usb3_phy1>, <&usb3_phy1>; 2308 phy-names = "usb2-phy", "usb3-phy"; 2309 snps,gfladj-refclk-lpm-sel-quirk; 2310 snps,parkmode-disable-ss-quirk; 2311 }; 2312 }; 2313 2314 dsp: dsp@3b6e8000 { 2315 compatible = "fsl,imx8mp-dsp"; 2316 reg = <0x3b6e8000 0x88000>; 2317 mbox-names = "txdb0", "txdb1", 2318 "rxdb0", "rxdb1"; 2319 mboxes = <&mu2 2 0>, <&mu2 2 1>, 2320 <&mu2 3 0>, <&mu2 3 1>; 2321 memory-region = <&dsp_reserved>; 2322 status = "disabled"; 2323 }; 2324 }; 2325}; 2326