1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mfd/qcom-rpm.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,gcc-ipq806x.h> 8#include <dt-bindings/clock/qcom,lcc-ipq806x.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/reset/qcom,gcc-ipq806x.h> 11#include <dt-bindings/soc/qcom,gsbi.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Qualcomm IPQ8064"; 18 compatible = "qcom,ipq8064"; 19 interrupt-parent = <&intc>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "qcom,krait"; 27 enable-method = "qcom,kpss-acc-v1"; 28 device_type = "cpu"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 qcom,acc = <&acc0>; 32 qcom,saw = <&saw0>; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "qcom,krait"; 37 enable-method = "qcom,kpss-acc-v1"; 38 device_type = "cpu"; 39 reg = <1>; 40 next-level-cache = <&L2>; 41 qcom,acc = <&acc1>; 42 qcom,saw = <&saw1>; 43 }; 44 45 L2: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 cache-unified; 49 }; 50 }; 51 52 thermal-zones { 53 sensor0-thermal { 54 polling-delay-passive = <0>; 55 polling-delay = <0>; 56 thermal-sensors = <&tsens 0>; 57 58 trips { 59 cpu-critical { 60 temperature = <105000>; 61 hysteresis = <2000>; 62 type = "critical"; 63 }; 64 65 cpu-hot { 66 temperature = <95000>; 67 hysteresis = <2000>; 68 type = "hot"; 69 }; 70 }; 71 }; 72 73 sensor1-thermal { 74 polling-delay-passive = <0>; 75 polling-delay = <0>; 76 thermal-sensors = <&tsens 1>; 77 78 trips { 79 cpu-critical { 80 temperature = <105000>; 81 hysteresis = <2000>; 82 type = "critical"; 83 }; 84 85 cpu-hot { 86 temperature = <95000>; 87 hysteresis = <2000>; 88 type = "hot"; 89 }; 90 }; 91 }; 92 93 sensor2-thermal { 94 polling-delay-passive = <0>; 95 polling-delay = <0>; 96 thermal-sensors = <&tsens 2>; 97 98 trips { 99 cpu-critical { 100 temperature = <105000>; 101 hysteresis = <2000>; 102 type = "critical"; 103 }; 104 105 cpu-hot { 106 temperature = <95000>; 107 hysteresis = <2000>; 108 type = "hot"; 109 }; 110 }; 111 }; 112 113 sensor3-thermal { 114 polling-delay-passive = <0>; 115 polling-delay = <0>; 116 thermal-sensors = <&tsens 3>; 117 118 trips { 119 cpu-critical { 120 temperature = <105000>; 121 hysteresis = <2000>; 122 type = "critical"; 123 }; 124 125 cpu-hot { 126 temperature = <95000>; 127 hysteresis = <2000>; 128 type = "hot"; 129 }; 130 }; 131 }; 132 133 sensor4-thermal { 134 polling-delay-passive = <0>; 135 polling-delay = <0>; 136 thermal-sensors = <&tsens 4>; 137 138 trips { 139 cpu-critical { 140 temperature = <105000>; 141 hysteresis = <2000>; 142 type = "critical"; 143 }; 144 145 cpu-hot { 146 temperature = <95000>; 147 hysteresis = <2000>; 148 type = "hot"; 149 }; 150 }; 151 }; 152 153 sensor5-thermal { 154 polling-delay-passive = <0>; 155 polling-delay = <0>; 156 thermal-sensors = <&tsens 5>; 157 158 trips { 159 cpu-critical { 160 temperature = <105000>; 161 hysteresis = <2000>; 162 type = "critical"; 163 }; 164 165 cpu-hot { 166 temperature = <95000>; 167 hysteresis = <2000>; 168 type = "hot"; 169 }; 170 }; 171 }; 172 173 sensor6-thermal { 174 polling-delay-passive = <0>; 175 polling-delay = <0>; 176 thermal-sensors = <&tsens 6>; 177 178 trips { 179 cpu-critical { 180 temperature = <105000>; 181 hysteresis = <2000>; 182 type = "critical"; 183 }; 184 185 cpu-hot { 186 temperature = <95000>; 187 hysteresis = <2000>; 188 type = "hot"; 189 }; 190 }; 191 }; 192 193 sensor7-thermal { 194 polling-delay-passive = <0>; 195 polling-delay = <0>; 196 thermal-sensors = <&tsens 7>; 197 198 trips { 199 cpu-critical { 200 temperature = <105000>; 201 hysteresis = <2000>; 202 type = "critical"; 203 }; 204 205 cpu-hot { 206 temperature = <95000>; 207 hysteresis = <2000>; 208 type = "hot"; 209 }; 210 }; 211 }; 212 213 sensor8-thermal { 214 polling-delay-passive = <0>; 215 polling-delay = <0>; 216 thermal-sensors = <&tsens 8>; 217 218 trips { 219 cpu-critical { 220 temperature = <105000>; 221 hysteresis = <2000>; 222 type = "critical"; 223 }; 224 225 cpu-hot { 226 temperature = <95000>; 227 hysteresis = <2000>; 228 type = "hot"; 229 }; 230 }; 231 }; 232 233 sensor9-thermal { 234 polling-delay-passive = <0>; 235 polling-delay = <0>; 236 thermal-sensors = <&tsens 9>; 237 238 trips { 239 cpu-critical { 240 temperature = <105000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 245 cpu-hot { 246 temperature = <95000>; 247 hysteresis = <2000>; 248 type = "hot"; 249 }; 250 }; 251 }; 252 253 sensor10-thermal { 254 polling-delay-passive = <0>; 255 polling-delay = <0>; 256 thermal-sensors = <&tsens 10>; 257 258 trips { 259 cpu-critical { 260 temperature = <105000>; 261 hysteresis = <2000>; 262 type = "critical"; 263 }; 264 265 cpu-hot { 266 temperature = <95000>; 267 hysteresis = <2000>; 268 type = "hot"; 269 }; 270 }; 271 }; 272 }; 273 274 memory { 275 device_type = "memory"; 276 reg = <0x0 0x0>; 277 }; 278 279 cpu-pmu { 280 compatible = "qcom,krait-pmu"; 281 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 282 IRQ_TYPE_LEVEL_HIGH)>; 283 }; 284 285 reserved-memory { 286 #address-cells = <1>; 287 #size-cells = <1>; 288 ranges; 289 290 nss@40000000 { 291 reg = <0x40000000 0x1000000>; 292 no-map; 293 }; 294 295 smem: smem@41000000 { 296 compatible = "qcom,smem"; 297 reg = <0x41000000 0x200000>; 298 no-map; 299 300 hwlocks = <&sfpb_mutex 3>; 301 }; 302 }; 303 304 clocks { 305 cxo_board: cxo_board { 306 compatible = "fixed-clock"; 307 #clock-cells = <0>; 308 clock-frequency = <25000000>; 309 }; 310 311 pxo_board: pxo_board { 312 compatible = "fixed-clock"; 313 #clock-cells = <0>; 314 clock-frequency = <25000000>; 315 }; 316 317 sleep_clk: sleep_clk { 318 compatible = "fixed-clock"; 319 clock-frequency = <32768>; 320 #clock-cells = <0>; 321 }; 322 }; 323 324 firmware { 325 scm { 326 compatible = "qcom,scm-ipq806x", "qcom,scm"; 327 }; 328 }; 329 330 stmmac_axi_setup: stmmac-axi-config { 331 snps,wr_osr_lmt = <7>; 332 snps,rd_osr_lmt = <7>; 333 snps,blen = <16 0 0 0 0 0 0>; 334 }; 335 336 vsdcc_fixed: vsdcc-regulator { 337 compatible = "regulator-fixed"; 338 regulator-name = "SDCC Power"; 339 regulator-min-microvolt = <3300000>; 340 regulator-max-microvolt = <3300000>; 341 regulator-always-on; 342 }; 343 344 soc: soc { 345 #address-cells = <1>; 346 #size-cells = <1>; 347 ranges; 348 compatible = "simple-bus"; 349 350 rpm: rpm@108000 { 351 compatible = "qcom,rpm-ipq8064"; 352 reg = <0x00108000 0x1000>; 353 qcom,ipc = <&l2cc 0x8 2>; 354 355 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 358 interrupt-names = "ack", "err", "wakeup"; 359 360 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 361 clock-names = "ram"; 362 363 rpmcc: clock-controller { 364 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; 365 #clock-cells = <1>; 366 }; 367 }; 368 369 ssbi@500000 { 370 compatible = "qcom,ssbi"; 371 reg = <0x00500000 0x1000>; 372 qcom,controller-type = "pmic-arbiter"; 373 }; 374 375 qfprom: qfprom@700000 { 376 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; 377 reg = <0x00700000 0x1000>; 378 #address-cells = <1>; 379 #size-cells = <1>; 380 speedbin_efuse: speedbin@c0 { 381 reg = <0xc0 0x4>; 382 }; 383 tsens_calib: calib@400 { 384 reg = <0x400 0xb>; 385 }; 386 tsens_calib_backup: calib_backup@410 { 387 reg = <0x410 0xb>; 388 }; 389 }; 390 391 qcom_pinmux: pinmux@800000 { 392 compatible = "qcom,ipq8064-pinctrl"; 393 reg = <0x00800000 0x4000>; 394 395 gpio-controller; 396 gpio-ranges = <&qcom_pinmux 0 0 69>; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 401 402 pcie0_pins: pcie0_pinmux { 403 mux { 404 pins = "gpio3"; 405 function = "pcie1_rst"; 406 drive-strength = <12>; 407 bias-disable; 408 }; 409 }; 410 411 pcie1_pins: pcie1_pinmux { 412 mux { 413 pins = "gpio48"; 414 function = "pcie2_rst"; 415 drive-strength = <12>; 416 bias-disable; 417 }; 418 }; 419 420 pcie2_pins: pcie2_pinmux { 421 mux { 422 pins = "gpio63"; 423 function = "pcie3_rst"; 424 drive-strength = <12>; 425 bias-disable; 426 }; 427 }; 428 429 i2c4_pins: i2c4-default { 430 pins = "gpio12", "gpio13"; 431 function = "gsbi4"; 432 drive-strength = <12>; 433 bias-disable; 434 }; 435 436 spi_pins: spi_pins { 437 mux { 438 pins = "gpio18", "gpio19", "gpio21"; 439 function = "gsbi5"; 440 drive-strength = <10>; 441 bias-none; 442 }; 443 }; 444 445 leds_pins: leds_pins { 446 mux { 447 pins = "gpio7", "gpio8", "gpio9", 448 "gpio26", "gpio53"; 449 function = "gpio"; 450 drive-strength = <2>; 451 bias-pull-down; 452 output-low; 453 }; 454 }; 455 456 buttons_pins: buttons_pins { 457 mux { 458 pins = "gpio54"; 459 drive-strength = <2>; 460 bias-pull-up; 461 }; 462 }; 463 464 nand_pins: nand_pins { 465 mux { 466 pins = "gpio34", "gpio35", "gpio36", 467 "gpio37", "gpio38", "gpio39", 468 "gpio40", "gpio41", "gpio42", 469 "gpio43", "gpio44", "gpio45", 470 "gpio46", "gpio47"; 471 function = "nand"; 472 drive-strength = <10>; 473 bias-disable; 474 }; 475 476 pullups { 477 pins = "gpio39"; 478 function = "nand"; 479 drive-strength = <10>; 480 bias-pull-up; 481 }; 482 483 hold { 484 pins = "gpio40", "gpio41", "gpio42", 485 "gpio43", "gpio44", "gpio45", 486 "gpio46", "gpio47"; 487 function = "nand"; 488 drive-strength = <10>; 489 bias-bus-hold; 490 }; 491 }; 492 493 mdio0_pins: mdio0-pins { 494 mux { 495 pins = "gpio0", "gpio1"; 496 function = "mdio"; 497 drive-strength = <8>; 498 bias-disable; 499 }; 500 }; 501 502 rgmii2_pins: rgmii2-pins { 503 mux { 504 pins = "gpio27", "gpio28", "gpio29", 505 "gpio30", "gpio31", "gpio32", 506 "gpio51", "gpio52", "gpio59", 507 "gpio60", "gpio61", "gpio62"; 508 function = "rgmii2"; 509 drive-strength = <8>; 510 bias-disable; 511 }; 512 }; 513 }; 514 515 gcc: clock-controller@900000 { 516 compatible = "qcom,gcc-ipq8064", "syscon"; 517 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>; 518 clock-names = "pxo", "cxo", "pll4"; 519 reg = <0x00900000 0x4000>; 520 #clock-cells = <1>; 521 #reset-cells = <1>; 522 #power-domain-cells = <1>; 523 524 tsens: thermal-sensor { 525 compatible = "qcom,ipq8064-tsens"; 526 527 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 528 nvmem-cell-names = "calib", "calib_backup"; 529 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 530 interrupt-names = "uplow"; 531 532 #qcom,sensors = <11>; 533 #thermal-sensor-cells = <1>; 534 }; 535 }; 536 537 sfpb_mutex: hwlock@1200600 { 538 compatible = "qcom,sfpb-mutex"; 539 reg = <0x01200600 0x100>; 540 541 #hwlock-cells = <1>; 542 }; 543 544 intc: interrupt-controller@2000000 { 545 compatible = "qcom,msm-qgic2"; 546 interrupt-controller; 547 #interrupt-cells = <3>; 548 reg = <0x02000000 0x1000>, 549 <0x02002000 0x1000>; 550 }; 551 552 timer@200a000 { 553 compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", 554 "qcom,msm-timer"; 555 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | 556 IRQ_TYPE_EDGE_RISING)>, 557 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | 558 IRQ_TYPE_EDGE_RISING)>, 559 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | 560 IRQ_TYPE_EDGE_RISING)>, 561 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | 562 IRQ_TYPE_EDGE_RISING)>, 563 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | 564 IRQ_TYPE_EDGE_RISING)>; 565 reg = <0x0200a000 0x100>; 566 clock-frequency = <25000000>; 567 clocks = <&sleep_clk>; 568 clock-names = "sleep"; 569 cpu-offset = <0x80000>; 570 }; 571 572 l2cc: clock-controller@2011000 { 573 compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; 574 reg = <0x02011000 0x1000>; 575 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 576 clock-names = "pll8_vote", "pxo"; 577 #clock-cells = <0>; 578 }; 579 580 acc0: clock-controller@2088000 { 581 compatible = "qcom,kpss-acc-v1"; 582 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 583 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 584 clock-names = "pll8_vote", "pxo"; 585 clock-output-names = "acpu0_aux"; 586 #clock-cells = <0>; 587 }; 588 589 saw0: power-manager@2089000 { 590 compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; 591 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 592 }; 593 594 acc1: clock-controller@2098000 { 595 compatible = "qcom,kpss-acc-v1"; 596 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 597 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 598 clock-names = "pll8_vote", "pxo"; 599 clock-output-names = "acpu1_aux"; 600 #clock-cells = <0>; 601 }; 602 603 saw1: power-manager@2099000 { 604 compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; 605 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 606 }; 607 608 nss_common: syscon@3000000 { 609 compatible = "syscon"; 610 reg = <0x03000000 0x0000FFFF>; 611 }; 612 613 usb3_0: usb@100f8800 { 614 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 615 #address-cells = <1>; 616 #size-cells = <1>; 617 reg = <0x100f8800 0x8000>; 618 clocks = <&gcc USB30_0_MASTER_CLK>; 619 clock-names = "core"; 620 621 ranges; 622 623 resets = <&gcc USB30_0_MASTER_RESET>; 624 625 status = "disabled"; 626 627 dwc3_0: usb@10000000 { 628 compatible = "snps,dwc3"; 629 reg = <0x10000000 0xcd00>; 630 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 631 phys = <&hs_phy_0>, <&ss_phy_0>; 632 phy-names = "usb2-phy", "usb3-phy"; 633 dr_mode = "host"; 634 snps,dis_u3_susphy_quirk; 635 }; 636 }; 637 638 hs_phy_0: phy@100f8800 { 639 compatible = "qcom,ipq806x-usb-phy-hs"; 640 reg = <0x100f8800 0x30>; 641 clocks = <&gcc USB30_0_UTMI_CLK>; 642 clock-names = "ref"; 643 #phy-cells = <0>; 644 645 status = "disabled"; 646 }; 647 648 ss_phy_0: phy@100f8830 { 649 compatible = "qcom,ipq806x-usb-phy-ss"; 650 reg = <0x100f8830 0x30>; 651 clocks = <&gcc USB30_0_MASTER_CLK>; 652 clock-names = "ref"; 653 #phy-cells = <0>; 654 655 status = "disabled"; 656 }; 657 658 usb3_1: usb@110f8800 { 659 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 660 #address-cells = <1>; 661 #size-cells = <1>; 662 reg = <0x110f8800 0x8000>; 663 clocks = <&gcc USB30_1_MASTER_CLK>; 664 clock-names = "core"; 665 666 ranges; 667 668 resets = <&gcc USB30_1_MASTER_RESET>; 669 670 status = "disabled"; 671 672 dwc3_1: usb@11000000 { 673 compatible = "snps,dwc3"; 674 reg = <0x11000000 0xcd00>; 675 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 676 phys = <&hs_phy_1>, <&ss_phy_1>; 677 phy-names = "usb2-phy", "usb3-phy"; 678 dr_mode = "host"; 679 snps,dis_u3_susphy_quirk; 680 }; 681 }; 682 683 hs_phy_1: phy@110f8800 { 684 compatible = "qcom,ipq806x-usb-phy-hs"; 685 reg = <0x110f8800 0x30>; 686 clocks = <&gcc USB30_1_UTMI_CLK>; 687 clock-names = "ref"; 688 #phy-cells = <0>; 689 690 status = "disabled"; 691 }; 692 693 ss_phy_1: phy@110f8830 { 694 compatible = "qcom,ipq806x-usb-phy-ss"; 695 reg = <0x110f8830 0x30>; 696 clocks = <&gcc USB30_1_MASTER_CLK>; 697 clock-names = "ref"; 698 #phy-cells = <0>; 699 700 status = "disabled"; 701 }; 702 703 sdcc3bam: dma-controller@12182000 { 704 compatible = "qcom,bam-v1.3.0"; 705 reg = <0x12182000 0x8000>; 706 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&gcc SDC3_H_CLK>; 708 clock-names = "bam_clk"; 709 #dma-cells = <1>; 710 qcom,ee = <0>; 711 }; 712 713 sdcc1bam: dma-controller@12402000 { 714 compatible = "qcom,bam-v1.3.0"; 715 reg = <0x12402000 0x8000>; 716 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&gcc SDC1_H_CLK>; 718 clock-names = "bam_clk"; 719 #dma-cells = <1>; 720 qcom,ee = <0>; 721 }; 722 723 amba: amba { 724 compatible = "simple-bus"; 725 #address-cells = <1>; 726 #size-cells = <1>; 727 ranges; 728 729 sdcc3: mmc@12180000 { 730 compatible = "arm,pl18x", "arm,primecell"; 731 arm,primecell-periphid = <0x00051180>; 732 status = "disabled"; 733 reg = <0x12180000 0x2000>; 734 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 736 clock-names = "mclk", "apb_pclk"; 737 bus-width = <8>; 738 cap-sd-highspeed; 739 cap-mmc-highspeed; 740 max-frequency = <192000000>; 741 sd-uhs-sdr104; 742 sd-uhs-ddr50; 743 vqmmc-supply = <&vsdcc_fixed>; 744 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 745 dma-names = "tx", "rx"; 746 }; 747 748 sdcc1: mmc@12400000 { 749 status = "disabled"; 750 compatible = "arm,pl18x", "arm,primecell"; 751 arm,primecell-periphid = <0x00051180>; 752 reg = <0x12400000 0x2000>; 753 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 755 clock-names = "mclk", "apb_pclk"; 756 bus-width = <8>; 757 max-frequency = <96000000>; 758 non-removable; 759 cap-sd-highspeed; 760 cap-mmc-highspeed; 761 vmmc-supply = <&vsdcc_fixed>; 762 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 763 dma-names = "tx", "rx"; 764 }; 765 }; 766 767 gsbi1: gsbi@12440000 { 768 compatible = "qcom,gsbi-v1.0.0"; 769 reg = <0x12440000 0x100>; 770 cell-index = <1>; 771 clocks = <&gcc GSBI1_H_CLK>; 772 clock-names = "iface"; 773 #address-cells = <1>; 774 #size-cells = <1>; 775 ranges; 776 777 syscon-tcsr = <&tcsr>; 778 779 status = "disabled"; 780 781 gsbi1_serial: serial@12450000 { 782 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 783 reg = <0x12450000 0x100>, 784 <0x12400000 0x03>; 785 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 787 clock-names = "core", "iface"; 788 789 status = "disabled"; 790 }; 791 792 gsbi1_i2c: i2c@12460000 { 793 compatible = "qcom,i2c-qup-v1.1.1"; 794 reg = <0x12460000 0x1000>; 795 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 797 clock-names = "core", "iface"; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 status = "disabled"; 802 }; 803 }; 804 805 gsbi2: gsbi@12480000 { 806 compatible = "qcom,gsbi-v1.0.0"; 807 cell-index = <2>; 808 reg = <0x12480000 0x100>; 809 clocks = <&gcc GSBI2_H_CLK>; 810 clock-names = "iface"; 811 #address-cells = <1>; 812 #size-cells = <1>; 813 ranges; 814 status = "disabled"; 815 816 syscon-tcsr = <&tcsr>; 817 818 gsbi2_serial: serial@12490000 { 819 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 820 reg = <0x12490000 0x1000>, 821 <0x12480000 0x1000>; 822 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; 824 clock-names = "core", "iface"; 825 status = "disabled"; 826 }; 827 828 gsbi2_i2c: i2c@124a0000 { 829 compatible = "qcom,i2c-qup-v1.1.1"; 830 reg = <0x124a0000 0x1000>; 831 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 832 833 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 834 clock-names = "core", "iface"; 835 status = "disabled"; 836 837 #address-cells = <1>; 838 #size-cells = <0>; 839 }; 840 }; 841 842 gsbi4: gsbi@16300000 { 843 compatible = "qcom,gsbi-v1.0.0"; 844 cell-index = <4>; 845 reg = <0x16300000 0x100>; 846 clocks = <&gcc GSBI4_H_CLK>; 847 clock-names = "iface"; 848 #address-cells = <1>; 849 #size-cells = <1>; 850 ranges; 851 status = "disabled"; 852 853 syscon-tcsr = <&tcsr>; 854 855 gsbi4_serial: serial@16340000 { 856 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 857 reg = <0x16340000 0x1000>, 858 <0x16300000 0x1000>; 859 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 861 clock-names = "core", "iface"; 862 status = "disabled"; 863 }; 864 865 i2c@16380000 { 866 compatible = "qcom,i2c-qup-v1.1.1"; 867 reg = <0x16380000 0x1000>; 868 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 869 870 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; 871 clock-names = "core", "iface"; 872 status = "disabled"; 873 874 #address-cells = <1>; 875 #size-cells = <0>; 876 }; 877 }; 878 879 gsbi6: gsbi@16500000 { 880 compatible = "qcom,gsbi-v1.0.0"; 881 reg = <0x16500000 0x100>; 882 cell-index = <6>; 883 clocks = <&gcc GSBI6_H_CLK>; 884 clock-names = "iface"; 885 #address-cells = <1>; 886 #size-cells = <1>; 887 ranges; 888 889 syscon-tcsr = <&tcsr>; 890 891 status = "disabled"; 892 893 gsbi6_i2c: i2c@16580000 { 894 compatible = "qcom,i2c-qup-v1.1.1"; 895 reg = <0x16580000 0x1000>; 896 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 897 898 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 899 clock-names = "core", "iface"; 900 901 #address-cells = <1>; 902 #size-cells = <0>; 903 904 status = "disabled"; 905 }; 906 907 gsbi6_spi: spi@16580000 { 908 compatible = "qcom,spi-qup-v1.1.1"; 909 reg = <0x16580000 0x1000>; 910 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 911 912 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 913 clock-names = "core", "iface"; 914 915 #address-cells = <1>; 916 #size-cells = <0>; 917 918 status = "disabled"; 919 }; 920 }; 921 922 gsbi7: gsbi@16600000 { 923 status = "disabled"; 924 compatible = "qcom,gsbi-v1.0.0"; 925 cell-index = <7>; 926 reg = <0x16600000 0x100>; 927 clocks = <&gcc GSBI7_H_CLK>; 928 clock-names = "iface"; 929 #address-cells = <1>; 930 #size-cells = <1>; 931 ranges; 932 syscon-tcsr = <&tcsr>; 933 934 gsbi7_serial: serial@16640000 { 935 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 936 reg = <0x16640000 0x1000>, 937 <0x16600000 0x1000>; 938 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 940 clock-names = "core", "iface"; 941 status = "disabled"; 942 }; 943 944 gsbi7_i2c: i2c@16680000 { 945 compatible = "qcom,i2c-qup-v1.1.1"; 946 reg = <0x16680000 0x1000>; 947 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 948 949 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; 950 clock-names = "core", "iface"; 951 952 #address-cells = <1>; 953 #size-cells = <0>; 954 955 status = "disabled"; 956 }; 957 }; 958 959 adm_dma: dma-controller@18300000 { 960 compatible = "qcom,adm"; 961 reg = <0x18300000 0x100000>; 962 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 963 #dma-cells = <1>; 964 965 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; 966 clock-names = "core", "iface"; 967 968 resets = <&gcc ADM0_RESET>, 969 <&gcc ADM0_PBUS_RESET>, 970 <&gcc ADM0_C0_RESET>, 971 <&gcc ADM0_C1_RESET>, 972 <&gcc ADM0_C2_RESET>; 973 reset-names = "clk", "pbus", "c0", "c1", "c2"; 974 qcom,ee = <0>; 975 976 status = "disabled"; 977 }; 978 979 gsbi5: gsbi@1a200000 { 980 compatible = "qcom,gsbi-v1.0.0"; 981 cell-index = <5>; 982 reg = <0x1a200000 0x100>; 983 clocks = <&gcc GSBI5_H_CLK>; 984 clock-names = "iface"; 985 #address-cells = <1>; 986 987 #size-cells = <1>; 988 ranges; 989 status = "disabled"; 990 991 syscon-tcsr = <&tcsr>; 992 993 gsbi5_serial: serial@1a240000 { 994 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 995 reg = <0x1a240000 0x1000>, 996 <0x1a200000 0x1000>; 997 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 999 clock-names = "core", "iface"; 1000 status = "disabled"; 1001 }; 1002 1003 i2c@1a280000 { 1004 compatible = "qcom,i2c-qup-v1.1.1"; 1005 reg = <0x1a280000 0x1000>; 1006 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1007 1008 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 1009 clock-names = "core", "iface"; 1010 status = "disabled"; 1011 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 }; 1015 1016 spi@1a280000 { 1017 compatible = "qcom,spi-qup-v1.1.1"; 1018 reg = <0x1a280000 0x1000>; 1019 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1020 1021 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 1022 clock-names = "core", "iface"; 1023 status = "disabled"; 1024 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 }; 1028 }; 1029 1030 tcsr: syscon@1a400000 { 1031 compatible = "qcom,tcsr-ipq8064", "syscon"; 1032 reg = <0x1a400000 0x100>; 1033 }; 1034 1035 rng@1a500000 { 1036 compatible = "qcom,prng"; 1037 reg = <0x1a500000 0x200>; 1038 clocks = <&gcc PRNG_CLK>; 1039 clock-names = "core"; 1040 }; 1041 1042 nand: nand-controller@1ac00000 { 1043 compatible = "qcom,ipq806x-nand"; 1044 reg = <0x1ac00000 0x800>; 1045 1046 pinctrl-0 = <&nand_pins>; 1047 pinctrl-names = "default"; 1048 1049 clocks = <&gcc EBI2_CLK>, 1050 <&gcc EBI2_AON_CLK>; 1051 clock-names = "core", "aon"; 1052 1053 dmas = <&adm_dma 3>; 1054 dma-names = "rxtx"; 1055 qcom,cmd-crci = <15>; 1056 qcom,data-crci = <3>; 1057 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 1061 status = "disabled"; 1062 }; 1063 1064 sata_phy: sata-phy@1b400000 { 1065 compatible = "qcom,ipq806x-sata-phy"; 1066 reg = <0x1b400000 0x200>; 1067 1068 clocks = <&gcc SATA_PHY_CFG_CLK>; 1069 clock-names = "cfg"; 1070 1071 #phy-cells = <0>; 1072 status = "disabled"; 1073 }; 1074 1075 pcie0: pcie@1b500000 { 1076 compatible = "qcom,pcie-ipq8064"; 1077 reg = <0x1b500000 0x1000 1078 0x1b502000 0x80 1079 0x1b600000 0x100 1080 0x0ff00000 0x100000>; 1081 reg-names = "dbi", "elbi", "parf", "config"; 1082 device_type = "pci"; 1083 linux,pci-domain = <0>; 1084 bus-range = <0x00 0xff>; 1085 num-lanes = <1>; 1086 #address-cells = <3>; 1087 #size-cells = <2>; 1088 1089 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */ 1090 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */ 1091 1092 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1093 interrupt-names = "msi"; 1094 #interrupt-cells = <1>; 1095 interrupt-map-mask = <0 0 0 0x7>; 1096 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1097 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1098 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1099 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1100 1101 clocks = <&gcc PCIE_A_CLK>, 1102 <&gcc PCIE_H_CLK>, 1103 <&gcc PCIE_PHY_CLK>, 1104 <&gcc PCIE_AUX_CLK>, 1105 <&gcc PCIE_ALT_REF_CLK>; 1106 clock-names = "core", "iface", "phy", "aux", "ref"; 1107 1108 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; 1109 assigned-clock-rates = <100000000>; 1110 1111 resets = <&gcc PCIE_ACLK_RESET>, 1112 <&gcc PCIE_HCLK_RESET>, 1113 <&gcc PCIE_POR_RESET>, 1114 <&gcc PCIE_PCI_RESET>, 1115 <&gcc PCIE_PHY_RESET>, 1116 <&gcc PCIE_EXT_RESET>; 1117 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1118 1119 pinctrl-0 = <&pcie0_pins>; 1120 pinctrl-names = "default"; 1121 1122 status = "disabled"; 1123 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; 1124 1125 pcie@0 { 1126 device_type = "pci"; 1127 reg = <0x0 0x0 0x0 0x0 0x0>; 1128 bus-range = <0x01 0xff>; 1129 1130 #address-cells = <3>; 1131 #size-cells = <2>; 1132 ranges; 1133 }; 1134 }; 1135 1136 pcie1: pcie@1b700000 { 1137 compatible = "qcom,pcie-ipq8064"; 1138 reg = <0x1b700000 0x1000 1139 0x1b702000 0x80 1140 0x1b800000 0x100 1141 0x31f00000 0x100000>; 1142 reg-names = "dbi", "elbi", "parf", "config"; 1143 device_type = "pci"; 1144 linux,pci-domain = <1>; 1145 bus-range = <0x00 0xff>; 1146 num-lanes = <1>; 1147 #address-cells = <3>; 1148 #size-cells = <2>; 1149 1150 ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */ 1151 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */ 1152 1153 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1154 interrupt-names = "msi"; 1155 #interrupt-cells = <1>; 1156 interrupt-map-mask = <0 0 0 0x7>; 1157 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1158 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1159 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1160 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1161 1162 clocks = <&gcc PCIE_1_A_CLK>, 1163 <&gcc PCIE_1_H_CLK>, 1164 <&gcc PCIE_1_PHY_CLK>, 1165 <&gcc PCIE_1_AUX_CLK>, 1166 <&gcc PCIE_1_ALT_REF_CLK>; 1167 clock-names = "core", "iface", "phy", "aux", "ref"; 1168 1169 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; 1170 assigned-clock-rates = <100000000>; 1171 1172 resets = <&gcc PCIE_1_ACLK_RESET>, 1173 <&gcc PCIE_1_HCLK_RESET>, 1174 <&gcc PCIE_1_POR_RESET>, 1175 <&gcc PCIE_1_PCI_RESET>, 1176 <&gcc PCIE_1_PHY_RESET>, 1177 <&gcc PCIE_1_EXT_RESET>; 1178 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1179 1180 pinctrl-0 = <&pcie1_pins>; 1181 pinctrl-names = "default"; 1182 1183 status = "disabled"; 1184 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; 1185 1186 pcie@0 { 1187 device_type = "pci"; 1188 reg = <0x0 0x0 0x0 0x0 0x0>; 1189 bus-range = <0x01 0xff>; 1190 1191 #address-cells = <3>; 1192 #size-cells = <2>; 1193 ranges; 1194 }; 1195 }; 1196 1197 pcie2: pcie@1b900000 { 1198 compatible = "qcom,pcie-ipq8064"; 1199 reg = <0x1b900000 0x1000 1200 0x1b902000 0x80 1201 0x1ba00000 0x100 1202 0x35f00000 0x100000>; 1203 reg-names = "dbi", "elbi", "parf", "config"; 1204 device_type = "pci"; 1205 linux,pci-domain = <2>; 1206 bus-range = <0x00 0xff>; 1207 num-lanes = <1>; 1208 #address-cells = <3>; 1209 #size-cells = <2>; 1210 1211 ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */ 1212 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */ 1213 1214 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1215 interrupt-names = "msi"; 1216 #interrupt-cells = <1>; 1217 interrupt-map-mask = <0 0 0 0x7>; 1218 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1219 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1220 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1221 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1222 1223 clocks = <&gcc PCIE_2_A_CLK>, 1224 <&gcc PCIE_2_H_CLK>, 1225 <&gcc PCIE_2_PHY_CLK>, 1226 <&gcc PCIE_2_AUX_CLK>, 1227 <&gcc PCIE_2_ALT_REF_CLK>; 1228 clock-names = "core", "iface", "phy", "aux", "ref"; 1229 1230 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; 1231 assigned-clock-rates = <100000000>; 1232 1233 resets = <&gcc PCIE_2_ACLK_RESET>, 1234 <&gcc PCIE_2_HCLK_RESET>, 1235 <&gcc PCIE_2_POR_RESET>, 1236 <&gcc PCIE_2_PCI_RESET>, 1237 <&gcc PCIE_2_PHY_RESET>, 1238 <&gcc PCIE_2_EXT_RESET>; 1239 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1240 1241 pinctrl-0 = <&pcie2_pins>; 1242 pinctrl-names = "default"; 1243 1244 status = "disabled"; 1245 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; 1246 1247 pcie@0 { 1248 device_type = "pci"; 1249 reg = <0x0 0x0 0x0 0x0 0x0>; 1250 bus-range = <0x01 0xff>; 1251 1252 #address-cells = <3>; 1253 #size-cells = <2>; 1254 ranges; 1255 }; 1256 }; 1257 1258 qsgmii_csr: syscon@1bb00000 { 1259 compatible = "syscon"; 1260 reg = <0x1bb00000 0x000001FF>; 1261 }; 1262 1263 lcc: clock-controller@28000000 { 1264 compatible = "qcom,lcc-ipq8064"; 1265 reg = <0x28000000 0x1000>; 1266 #clock-cells = <1>; 1267 #reset-cells = <1>; 1268 }; 1269 1270 lpass@28100000 { 1271 compatible = "qcom,lpass-cpu"; 1272 status = "disabled"; 1273 clocks = <&lcc AHBIX_CLK>, 1274 <&lcc MI2S_OSR_CLK>, 1275 <&lcc MI2S_BIT_CLK>; 1276 clock-names = "ahbix-clk", 1277 "mi2s-osr-clk", 1278 "mi2s-bit-clk"; 1279 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1280 interrupt-names = "lpass-irq-lpaif"; 1281 reg = <0x28100000 0x10000>; 1282 reg-names = "lpass-lpaif"; 1283 }; 1284 1285 sata: sata@29000000 { 1286 compatible = "qcom,ipq806x-ahci", "generic-ahci"; 1287 reg = <0x29000000 0x180>; 1288 1289 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1290 1291 clocks = <&gcc SFAB_SATA_S_H_CLK>, 1292 <&gcc SATA_H_CLK>, 1293 <&gcc SATA_A_CLK>, 1294 <&gcc SATA_RXOOB_CLK>, 1295 <&gcc SATA_PMALIVE_CLK>; 1296 clock-names = "slave_face", "iface", "core", 1297 "rxoob", "pmalive"; 1298 1299 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; 1300 assigned-clock-rates = <100000000>, <100000000>; 1301 1302 phys = <&sata_phy>; 1303 phy-names = "sata-phy"; 1304 status = "disabled"; 1305 }; 1306 1307 gmac0: ethernet@37000000 { 1308 device_type = "network"; 1309 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1310 reg = <0x37000000 0x200000>; 1311 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1312 interrupt-names = "macirq"; 1313 1314 snps,axi-config = <&stmmac_axi_setup>; 1315 snps,pbl = <32>; 1316 snps,aal; 1317 1318 qcom,nss-common = <&nss_common>; 1319 qcom,qsgmii-csr = <&qsgmii_csr>; 1320 1321 clocks = <&gcc GMAC_CORE1_CLK>; 1322 clock-names = "stmmaceth"; 1323 1324 resets = <&gcc GMAC_CORE1_RESET>, 1325 <&gcc GMAC_AHB_RESET>; 1326 reset-names = "stmmaceth", "ahb"; 1327 1328 status = "disabled"; 1329 }; 1330 1331 gmac1: ethernet@37200000 { 1332 device_type = "network"; 1333 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1334 reg = <0x37200000 0x200000>; 1335 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1336 interrupt-names = "macirq"; 1337 1338 snps,axi-config = <&stmmac_axi_setup>; 1339 snps,pbl = <32>; 1340 snps,aal; 1341 1342 qcom,nss-common = <&nss_common>; 1343 qcom,qsgmii-csr = <&qsgmii_csr>; 1344 1345 clocks = <&gcc GMAC_CORE2_CLK>; 1346 clock-names = "stmmaceth"; 1347 1348 resets = <&gcc GMAC_CORE2_RESET>, 1349 <&gcc GMAC_AHB_RESET>; 1350 reset-names = "stmmaceth", "ahb"; 1351 1352 status = "disabled"; 1353 }; 1354 1355 gmac2: ethernet@37400000 { 1356 device_type = "network"; 1357 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1358 reg = <0x37400000 0x200000>; 1359 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1360 interrupt-names = "macirq"; 1361 1362 snps,axi-config = <&stmmac_axi_setup>; 1363 snps,pbl = <32>; 1364 snps,aal; 1365 1366 qcom,nss-common = <&nss_common>; 1367 qcom,qsgmii-csr = <&qsgmii_csr>; 1368 1369 clocks = <&gcc GMAC_CORE3_CLK>; 1370 clock-names = "stmmaceth"; 1371 1372 resets = <&gcc GMAC_CORE3_RESET>, 1373 <&gcc GMAC_AHB_RESET>; 1374 reset-names = "stmmaceth", "ahb"; 1375 1376 status = "disabled"; 1377 }; 1378 1379 gmac3: ethernet@37600000 { 1380 device_type = "network"; 1381 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1382 reg = <0x37600000 0x200000>; 1383 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1384 interrupt-names = "macirq"; 1385 1386 snps,axi-config = <&stmmac_axi_setup>; 1387 snps,pbl = <32>; 1388 snps,aal; 1389 1390 qcom,nss-common = <&nss_common>; 1391 qcom,qsgmii-csr = <&qsgmii_csr>; 1392 1393 clocks = <&gcc GMAC_CORE4_CLK>; 1394 clock-names = "stmmaceth"; 1395 1396 resets = <&gcc GMAC_CORE4_RESET>, 1397 <&gcc GMAC_AHB_RESET>; 1398 reset-names = "stmmaceth", "ahb"; 1399 1400 status = "disabled"; 1401 }; 1402 }; 1403}; 1404