1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include <dt-bindings/clock/meson8-ddr-clkc.h>
8#include <dt-bindings/clock/meson8b-clkc.h>
9#include <dt-bindings/gpio/meson8b-gpio.h>
10#include <dt-bindings/power/meson8-power.h>
11#include <dt-bindings/reset/amlogic,meson8b-reset.h>
12#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13#include <dt-bindings/thermal/thermal.h>
14#include "meson.dtsi"
15
16/ {
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@200 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a5";
24			next-level-cache = <&L2>;
25			reg = <0x200>;
26			enable-method = "amlogic,meson8b-smp";
27			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
28			operating-points-v2 = <&cpu_opp_table>;
29			clocks = <&clkc CLKID_CPUCLK>;
30			#cooling-cells = <2>; /* min followed by max */
31		};
32
33		cpu1: cpu@201 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a5";
36			next-level-cache = <&L2>;
37			reg = <0x201>;
38			enable-method = "amlogic,meson8b-smp";
39			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
40			operating-points-v2 = <&cpu_opp_table>;
41			clocks = <&clkc CLKID_CPUCLK>;
42			#cooling-cells = <2>; /* min followed by max */
43		};
44
45		cpu2: cpu@202 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a5";
48			next-level-cache = <&L2>;
49			reg = <0x202>;
50			enable-method = "amlogic,meson8b-smp";
51			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
52			operating-points-v2 = <&cpu_opp_table>;
53			clocks = <&clkc CLKID_CPUCLK>;
54			#cooling-cells = <2>; /* min followed by max */
55		};
56
57		cpu3: cpu@203 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a5";
60			next-level-cache = <&L2>;
61			reg = <0x203>;
62			enable-method = "amlogic,meson8b-smp";
63			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
64			operating-points-v2 = <&cpu_opp_table>;
65			clocks = <&clkc CLKID_CPUCLK>;
66			#cooling-cells = <2>; /* min followed by max */
67		};
68	};
69
70	cpu_opp_table: opp-table {
71		compatible = "operating-points-v2";
72		opp-shared;
73
74		opp-96000000 {
75			opp-hz = /bits/ 64 <96000000>;
76			opp-microvolt = <860000>;
77		};
78		opp-192000000 {
79			opp-hz = /bits/ 64 <192000000>;
80			opp-microvolt = <860000>;
81		};
82		opp-312000000 {
83			opp-hz = /bits/ 64 <312000000>;
84			opp-microvolt = <860000>;
85		};
86		opp-408000000 {
87			opp-hz = /bits/ 64 <408000000>;
88			opp-microvolt = <860000>;
89		};
90		opp-504000000 {
91			opp-hz = /bits/ 64 <504000000>;
92			opp-microvolt = <860000>;
93		};
94		opp-600000000 {
95			opp-hz = /bits/ 64 <600000000>;
96			opp-microvolt = <860000>;
97		};
98		opp-720000000 {
99			opp-hz = /bits/ 64 <720000000>;
100			opp-microvolt = <860000>;
101		};
102		opp-816000000 {
103			opp-hz = /bits/ 64 <816000000>;
104			opp-microvolt = <900000>;
105		};
106		opp-1008000000 {
107			opp-hz = /bits/ 64 <1008000000>;
108			opp-microvolt = <1140000>;
109		};
110		opp-1200000000 {
111			opp-hz = /bits/ 64 <1200000000>;
112			opp-microvolt = <1140000>;
113		};
114		opp-1320000000 {
115			opp-hz = /bits/ 64 <1320000000>;
116			opp-microvolt = <1140000>;
117		};
118		opp-1488000000 {
119			opp-hz = /bits/ 64 <1488000000>;
120			opp-microvolt = <1140000>;
121		};
122		opp-1536000000 {
123			opp-hz = /bits/ 64 <1536000000>;
124			opp-microvolt = <1140000>;
125		};
126	};
127
128	gpu_opp_table: opp-table-gpu {
129		compatible = "operating-points-v2";
130
131		opp-255000000 {
132			opp-hz = /bits/ 64 <255000000>;
133			opp-microvolt = <1100000>;
134		};
135		opp-364285714 {
136			opp-hz = /bits/ 64 <364285714>;
137			opp-microvolt = <1100000>;
138		};
139		opp-425000000 {
140			opp-hz = /bits/ 64 <425000000>;
141			opp-microvolt = <1100000>;
142		};
143		opp-510000000 {
144			opp-hz = /bits/ 64 <510000000>;
145			opp-microvolt = <1100000>;
146		};
147		opp-637500000 {
148			opp-hz = /bits/ 64 <637500000>;
149			opp-microvolt = <1100000>;
150			turbo-mode;
151		};
152	};
153
154	pmu {
155		compatible = "arm,cortex-a5-pmu";
156		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
157			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
158			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
159			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
160		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
161	};
162
163	reserved-memory {
164		#address-cells = <1>;
165		#size-cells = <1>;
166		ranges;
167
168		/* 2 MiB reserved for Hardware ROM Firmware? */
169		hwrom@0 {
170			reg = <0x0 0x200000>;
171			no-map;
172		};
173	};
174
175	thermal-zones {
176		soc {
177			polling-delay-passive = <250>; /* milliseconds */
178			polling-delay = <1000>; /* milliseconds */
179			thermal-sensors = <&thermal_sensor>;
180
181			cooling-maps {
182				map0 {
183					trip = <&soc_passive>;
184					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
185							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
186							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
187							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
188							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
189				};
190
191				map1 {
192					trip = <&soc_hot>;
193					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
194							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
195							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
196							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
197							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
198				};
199			};
200
201			trips {
202				soc_passive: soc-passive {
203					temperature = <80000>; /* millicelsius */
204					hysteresis = <2000>; /* millicelsius */
205					type = "passive";
206				};
207
208				soc_hot: soc-hot {
209					temperature = <90000>; /* millicelsius */
210					hysteresis = <2000>; /* millicelsius */
211					type = "hot";
212				};
213
214				soc_critical: soc-critical {
215					temperature = <110000>; /* millicelsius */
216					hysteresis = <2000>; /* millicelsius */
217					type = "critical";
218				};
219			};
220		};
221	};
222
223	mmcbus: bus@c8000000 {
224		compatible = "simple-bus";
225		reg = <0xc8000000 0x8000>;
226		#address-cells = <1>;
227		#size-cells = <1>;
228		ranges = <0x0 0xc8000000 0x8000>;
229
230		ddr_clkc: clock-controller@400 {
231			compatible = "amlogic,meson8b-ddr-clkc";
232			reg = <0x400 0x20>;
233			clocks = <&xtal>;
234			clock-names = "xtal";
235			#clock-cells = <1>;
236		};
237
238		dmcbus: bus@6000 {
239			compatible = "simple-bus";
240			reg = <0x6000 0x400>;
241			#address-cells = <1>;
242			#size-cells = <1>;
243			ranges = <0x0 0x6000 0x400>;
244
245			canvas: video-lut@48 {
246				compatible = "amlogic,meson8b-canvas",
247					     "amlogic,canvas";
248				reg = <0x48 0x14>;
249			};
250		};
251	};
252
253	apb: bus@d0000000 {
254		compatible = "simple-bus";
255		reg = <0xd0000000 0x200000>;
256		#address-cells = <1>;
257		#size-cells = <1>;
258		ranges = <0x0 0xd0000000 0x200000>;
259
260		mali: gpu@c0000 {
261			compatible = "amlogic,meson8b-mali", "arm,mali-450";
262			reg = <0xc0000 0x40000>;
263			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
264				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
265				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
266				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
267				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
268				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
269				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
270				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
271			interrupt-names = "gp", "gpmmu", "pp", "pmu",
272					  "pp0", "ppmmu0", "pp1", "ppmmu1";
273			resets = <&reset RESET_MALI>;
274			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
275			clock-names = "bus", "core";
276			operating-points-v2 = <&gpu_opp_table>;
277			#cooling-cells = <2>; /* min followed by max */
278		};
279	};
280}; /* end of / */
281
282&aiu {
283	compatible = "amlogic,aiu-meson8b", "amlogic,aiu";
284	clocks = <&clkc CLKID_AIU_GLUE>,
285		 <&clkc CLKID_I2S_OUT>,
286		 <&clkc CLKID_AOCLK_GATE>,
287		 <&clkc CLKID_CTS_AMCLK>,
288		 <&clkc CLKID_MIXER_IFACE>,
289		 <&clkc CLKID_IEC958>,
290		 <&clkc CLKID_IEC958_GATE>,
291		 <&clkc CLKID_CTS_MCLK_I958>,
292		 <&clkc CLKID_CTS_I958>;
293	clock-names = "pclk",
294		      "i2s_pclk",
295		      "i2s_aoclk",
296		      "i2s_mclk",
297		      "i2s_mixer",
298		      "spdif_pclk",
299		      "spdif_aoclk",
300		      "spdif_mclk",
301		      "spdif_mclk_sel";
302	resets = <&reset RESET_AIU>;
303};
304
305&aobus {
306	pmu: pmu@e0 {
307		compatible = "amlogic,meson8b-pmu", "syscon";
308		reg = <0xe0 0x18>;
309	};
310
311	pinctrl_aobus: pinctrl@84 {
312		compatible = "amlogic,meson8b-aobus-pinctrl";
313		reg = <0x84 0xc>;
314		#address-cells = <1>;
315		#size-cells = <1>;
316		ranges;
317
318		gpio_ao: ao-bank@14 {
319			reg = <0x14 0x4>,
320				<0x2c 0x4>,
321				<0x24 0x8>;
322			reg-names = "mux", "pull", "gpio";
323			gpio-controller;
324			#gpio-cells = <2>;
325			gpio-ranges = <&pinctrl_aobus 0 0 16>;
326		};
327
328		i2s_am_clk_pins: i2s-am-clk-out {
329			mux {
330				groups = "i2s_am_clk_out";
331				function = "i2s";
332				bias-disable;
333			};
334		};
335
336		i2s_out_ao_clk_pins: i2s-ao-clk-out {
337			mux {
338				groups = "i2s_ao_clk_out";
339				function = "i2s";
340				bias-disable;
341			};
342		};
343
344		i2s_out_lr_clk_pins: i2s-lr-clk-out {
345			mux {
346				groups = "i2s_lr_clk_out";
347				function = "i2s";
348				bias-disable;
349			};
350		};
351
352		i2s_out_ch01_ao_pins: i2s-out-ch01 {
353			mux {
354				groups = "i2s_out_01";
355				function = "i2s";
356				bias-disable;
357			};
358		};
359
360		spdif_out_1_pins: spdif-out-1 {
361			mux {
362				groups = "spdif_out_1";
363				function = "spdif_1";
364				bias-disable;
365			};
366		};
367
368		uart_ao_a_pins: uart_ao_a {
369			mux {
370				groups = "uart_tx_ao_a", "uart_rx_ao_a";
371				function = "uart_ao";
372				bias-disable;
373			};
374		};
375
376		ir_recv_pins: remote {
377			mux {
378				groups = "remote_input";
379				function = "remote";
380				bias-disable;
381			};
382		};
383	};
384};
385
386&ao_arc_rproc {
387	compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc";
388	amlogic,secbus2 = <&secbus2>;
389	sram = <&ao_arc_sram>;
390	resets = <&reset RESET_MEDIA_CPU>;
391	clocks = <&clkc CLKID_AO_MEDIA_CPU>;
392};
393
394&cbus {
395	reset: reset-controller@4404 {
396		compatible = "amlogic,meson8b-reset";
397		reg = <0x4404 0x9c>;
398		#reset-cells = <1>;
399	};
400
401	analog_top: analog-top@81a8 {
402		compatible = "amlogic,meson8b-analog-top", "syscon";
403		reg = <0x81a8 0x14>;
404	};
405
406	pwm_ef: pwm@86c0 {
407		compatible = "amlogic,meson8b-pwm";
408		reg = <0x86c0 0x10>;
409		#pwm-cells = <3>;
410		status = "disabled";
411	};
412
413	clock-measure@8758 {
414		compatible = "amlogic,meson8b-clk-measure";
415		reg = <0x8758 0x1c>;
416	};
417
418	pinctrl_cbus: pinctrl@9880 {
419		compatible = "amlogic,meson8b-cbus-pinctrl";
420		reg = <0x9880 0x10>;
421		#address-cells = <1>;
422		#size-cells = <1>;
423		ranges;
424
425		gpio: banks@80b0 {
426			reg = <0x80b0 0x28>,
427				<0x80e8 0x18>,
428				<0x8120 0x18>,
429				<0x8030 0x38>;
430			reg-names = "mux", "pull", "pull-enable", "gpio";
431			gpio-controller;
432			#gpio-cells = <2>;
433			gpio-ranges = <&pinctrl_cbus 0 0 83>;
434		};
435
436		eth_rgmii_pins: eth-rgmii {
437			mux {
438				groups = "eth_tx_clk",
439					 "eth_tx_en",
440					 "eth_txd1_0",
441					 "eth_txd0_0",
442					 "eth_rx_clk",
443					 "eth_rx_dv",
444					 "eth_rxd1",
445					 "eth_rxd0",
446					 "eth_mdio_en",
447					 "eth_mdc",
448					 "eth_ref_clk",
449					 "eth_txd2",
450					 "eth_txd3",
451					 "eth_rxd3",
452					 "eth_rxd2";
453				function = "ethernet";
454				bias-disable;
455			};
456		};
457
458		eth_rmii_pins: eth-rmii {
459			mux {
460				groups = "eth_tx_en",
461					 "eth_txd1_0",
462					 "eth_txd0_0",
463					 "eth_rx_clk",
464					 "eth_rx_dv",
465					 "eth_rxd1",
466					 "eth_rxd0",
467					 "eth_mdio_en",
468					 "eth_mdc";
469				function = "ethernet";
470				bias-disable;
471			};
472		};
473
474		i2c_a_pins: i2c-a {
475			mux {
476				groups = "i2c_sda_a", "i2c_sck_a";
477				function = "i2c_a";
478				bias-disable;
479			};
480		};
481
482		sd_b_pins: sd-b {
483			mux {
484				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
485					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
486				function = "sd_b";
487				bias-disable;
488			};
489		};
490
491		sdxc_c_pins: sdxc-c {
492			mux {
493				groups = "sdxc_d0_c", "sdxc_d13_c",
494					 "sdxc_d47_c", "sdxc_clk_c",
495					 "sdxc_cmd_c";
496				function = "sdxc_c";
497				bias-pull-up;
498			};
499		};
500
501		pwm_c1_pins: pwm-c1 {
502			mux {
503				groups = "pwm_c1";
504				function = "pwm_c";
505				bias-disable;
506			};
507		};
508
509		pwm_d_pins: pwm-d {
510			mux {
511				groups = "pwm_d";
512				function = "pwm_d";
513				bias-disable;
514			};
515		};
516
517		uart_b0_pins: uart-b0 {
518			mux {
519				groups = "uart_tx_b0",
520				       "uart_rx_b0";
521				function = "uart_b";
522				bias-disable;
523			};
524		};
525
526		uart_b0_cts_rts_pins: uart-b0-cts-rts {
527			mux {
528				groups = "uart_cts_b0",
529				       "uart_rts_b0";
530				function = "uart_b";
531				bias-disable;
532			};
533		};
534	};
535};
536
537&ahb_sram {
538	ao_arc_sram: ao-arc-sram@0 {
539		compatible = "amlogic,meson8b-ao-arc-sram";
540		reg = <0x0 0x8000>;
541		pool;
542	};
543
544	smp-sram@1ff80 {
545		compatible = "amlogic,meson8b-smp-sram";
546		reg = <0x1ff80 0x8>;
547	};
548};
549
550
551&efuse {
552	compatible = "amlogic,meson8b-efuse";
553	clocks = <&clkc CLKID_EFUSE>;
554	clock-names = "core";
555
556	temperature_calib: calib@1f4 {
557		/* only the upper two bytes are relevant */
558		reg = <0x1f4 0x4>;
559	};
560};
561
562&ethmac {
563	compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
564
565	reg = <0xc9410000 0x10000
566	       0xc1108140 0x4>;
567
568	clocks = <&clkc CLKID_ETH>,
569		 <&clkc CLKID_MPLL2>,
570		 <&clkc CLKID_MPLL2>,
571		 <&clkc CLKID_FCLK_DIV2>;
572	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
573	rx-fifo-depth = <4096>;
574	tx-fifo-depth = <2048>;
575
576	resets = <&reset RESET_ETHERNET>;
577	reset-names = "stmmaceth";
578
579	power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
580};
581
582&gpio_intc {
583	compatible = "amlogic,meson8b-gpio-intc",
584		     "amlogic,meson-gpio-intc";
585	status = "okay";
586};
587
588&hhi {
589	clkc: clock-controller {
590		compatible = "amlogic,meson8b-clkc";
591		clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
592		clock-names = "xtal", "ddr_pll";
593		#clock-cells = <1>;
594		#reset-cells = <1>;
595	};
596
597	pwrc: power-controller {
598		compatible = "amlogic,meson8b-pwrc";
599		#power-domain-cells = <1>;
600		amlogic,ao-sysctrl = <&pmu>;
601		resets = <&reset RESET_DBLK>,
602			 <&reset RESET_PIC_DC>,
603			 <&reset RESET_HDMI_APB>,
604			 <&reset RESET_HDMI_SYSTEM_RESET>,
605			 <&reset RESET_VENCI>,
606			 <&reset RESET_VENCP>,
607			 <&reset RESET_VDAC_4>,
608			 <&reset RESET_VENCL>,
609			 <&reset RESET_VIU>,
610			 <&reset RESET_VENC>,
611			 <&reset RESET_RDMA>;
612		reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
613			      "venci", "vencp", "vdac", "vencl", "viu",
614			      "venc", "rdma";
615		clocks = <&clkc CLKID_VPU>;
616		clock-names = "vpu";
617		assigned-clocks = <&clkc CLKID_VPU>;
618		assigned-clock-rates = <182142857>;
619	};
620};
621
622&hwrng {
623	clocks = <&clkc CLKID_RNG0>;
624	clock-names = "core";
625};
626
627&i2c_AO {
628	clocks = <&clkc CLKID_CLK81>;
629};
630
631&i2c_A {
632	clocks = <&clkc CLKID_I2C>;
633};
634
635&i2c_B {
636	clocks = <&clkc CLKID_I2C>;
637};
638
639&L2 {
640	arm,data-latency = <3 3 3>;
641	arm,tag-latency = <2 2 2>;
642	arm,filter-ranges = <0x100000 0xc0000000>;
643	prefetch-data = <1>;
644	prefetch-instr = <1>;
645	arm,prefetch-offset = <7>;
646	arm,double-linefill = <1>;
647	arm,prefetch-drop = <1>;
648	arm,shared-override;
649};
650
651&periph {
652	scu@0 {
653		compatible = "arm,cortex-a5-scu";
654		reg = <0x0 0x100>;
655	};
656
657	timer@200 {
658		compatible = "arm,cortex-a5-global-timer";
659		reg = <0x200 0x20>;
660		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
661		clocks = <&clkc CLKID_PERIPH>;
662
663		/*
664		 * the arm_global_timer driver currently does not handle clock
665		 * rate changes. Keep it disabled for now.
666		 */
667		status = "disabled";
668	};
669
670	timer@600 {
671		compatible = "arm,cortex-a5-twd-timer";
672		reg = <0x600 0x20>;
673		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
674		clocks = <&clkc CLKID_PERIPH>;
675	};
676};
677
678&pwm_ab {
679	compatible = "amlogic,meson8b-pwm";
680};
681
682&pwm_cd {
683	compatible = "amlogic,meson8b-pwm";
684};
685
686&rtc {
687	compatible = "amlogic,meson8b-rtc";
688	resets = <&reset RESET_RTC>;
689};
690
691&saradc {
692	compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
693	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
694	clock-names = "clkin", "core";
695	amlogic,hhi-sysctrl = <&hhi>;
696	nvmem-cells = <&temperature_calib>;
697	nvmem-cell-names = "temperature_calib";
698};
699
700&sdhc {
701	compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
702	clocks = <&xtal>,
703		 <&clkc CLKID_FCLK_DIV4>,
704		 <&clkc CLKID_FCLK_DIV3>,
705		 <&clkc CLKID_FCLK_DIV5>,
706		 <&clkc CLKID_SDHC>;
707	clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
708};
709
710&secbus {
711	secbus2: system-controller@4000 {
712		compatible = "amlogic,meson8b-secbus2", "syscon";
713		reg = <0x4000 0x2000>;
714	};
715};
716
717&sdio {
718	compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
719	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
720	clock-names = "core", "clkin";
721};
722
723&timer_abcde {
724	clocks = <&xtal>, <&clkc CLKID_CLK81>;
725	clock-names = "xtal", "pclk";
726};
727
728&uart_AO {
729	compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart";
730	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
731	clock-names = "xtal", "pclk", "baud";
732};
733
734&uart_A {
735	compatible = "amlogic,meson8b-uart";
736	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
737	clock-names = "xtal", "pclk", "baud";
738};
739
740&uart_B {
741	compatible = "amlogic,meson8b-uart";
742	clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>;
743	clock-names = "xtal", "pclk", "baud";
744};
745
746&uart_C {
747	compatible = "amlogic,meson8b-uart";
748	clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>;
749	clock-names = "xtal", "pclk", "baud";
750};
751
752&usb0 {
753	compatible = "amlogic,meson8b-usb", "snps,dwc2";
754	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
755	clock-names = "otg";
756};
757
758&usb1 {
759	compatible = "amlogic,meson8b-usb", "snps,dwc2";
760	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
761	clock-names = "otg";
762};
763
764&usb0_phy {
765	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
766	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
767	clock-names = "usb_general", "usb";
768	resets = <&reset RESET_USB_OTG>;
769};
770
771&usb1_phy {
772	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
773	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
774	clock-names = "usb_general", "usb";
775	resets = <&reset RESET_USB_OTG>;
776};
777
778&wdt {
779	compatible = "amlogic,meson8b-wdt";
780};
781