1/* SPDX-License-Identifier: GPL-2.0 */ 2/* $Id: newport.h,v 1.5 1999/08/04 06:01:51 ulfc Exp $ 3 * 4 * newport.h: Defines and register layout for NEWPORT graphics 5 * hardware. 6 * 7 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 8 * 9 * Ulf Carlsson - Compatibility with the IRIX structures added 10 */ 11 12#ifndef _SGI_NEWPORT_H 13#define _SGI_NEWPORT_H 14 15 16typedef volatile unsigned int npireg_t; 17 18union npfloat { 19 volatile float flt; 20 npireg_t word; 21}; 22 23typedef union npfloat npfreg_t; 24 25union np_dcb { 26 npireg_t byword; 27 struct { volatile unsigned short s0, s1; } byshort; 28 struct { volatile unsigned char b0, b1, b2, b3; } bybytes; 29}; 30 31struct newport_rexregs { 32 npireg_t drawmode1; /* GL extra mode bits */ 33 34#define DM1_PLANES 0x00000007 35#define DM1_NOPLANES 0x00000000 36#define DM1_RGBPLANES 0x00000001 37#define DM1_RGBAPLANES 0x00000002 38#define DM1_OLAYPLANES 0x00000004 39#define DM1_PUPPLANES 0x00000005 40#define DM1_CIDPLANES 0x00000006 41 42#define NPORT_DMODE1_DDMASK 0x00000018 43#define NPORT_DMODE1_DD4 0x00000000 44#define NPORT_DMODE1_DD8 0x00000008 45#define NPORT_DMODE1_DD12 0x00000010 46#define NPORT_DMODE1_DD24 0x00000018 47#define NPORT_DMODE1_DSRC 0x00000020 48#define NPORT_DMODE1_YFLIP 0x00000040 49#define NPORT_DMODE1_RWPCKD 0x00000080 50#define NPORT_DMODE1_HDMASK 0x00000300 51#define NPORT_DMODE1_HD4 0x00000000 52#define NPORT_DMODE1_HD8 0x00000100 53#define NPORT_DMODE1_HD12 0x00000200 54#define NPORT_DMODE1_HD32 0x00000300 55#define NPORT_DMODE1_RWDBL 0x00000400 56#define NPORT_DMODE1_ESWAP 0x00000800 /* Endian swap */ 57#define NPORT_DMODE1_CCMASK 0x00007000 58#define NPORT_DMODE1_CCLT 0x00001000 59#define NPORT_DMODE1_CCEQ 0x00002000 60#define NPORT_DMODE1_CCGT 0x00004000 61#define NPORT_DMODE1_RGBMD 0x00008000 62#define NPORT_DMODE1_DENAB 0x00010000 /* Dither enable */ 63#define NPORT_DMODE1_FCLR 0x00020000 /* Fast clear */ 64#define NPORT_DMODE1_BENAB 0x00040000 /* Blend enable */ 65#define NPORT_DMODE1_SFMASK 0x00380000 66#define NPORT_DMODE1_SF0 0x00000000 67#define NPORT_DMODE1_SF1 0x00080000 68#define NPORT_DMODE1_SFDC 0x00100000 69#define NPORT_DMODE1_SFMDC 0x00180000 70#define NPORT_DMODE1_SFSA 0x00200000 71#define NPORT_DMODE1_SFMSA 0x00280000 72#define NPORT_DMODE1_DFMASK 0x01c00000 73#define NPORT_DMODE1_DF0 0x00000000 74#define NPORT_DMODE1_DF1 0x00400000 75#define NPORT_DMODE1_DFSC 0x00800000 76#define NPORT_DMODE1_DFMSC 0x00c00000 77#define NPORT_DMODE1_DFSA 0x01000000 78#define NPORT_DMODE1_DFMSA 0x01400000 79#define NPORT_DMODE1_BBENAB 0x02000000 /* Back blend enable */ 80#define NPORT_DMODE1_PFENAB 0x04000000 /* Pre-fetch enable */ 81#define NPORT_DMODE1_ABLEND 0x08000000 /* Alpha blend */ 82#define NPORT_DMODE1_LOMASK 0xf0000000 83#define NPORT_DMODE1_LOZERO 0x00000000 84#define NPORT_DMODE1_LOAND 0x10000000 85#define NPORT_DMODE1_LOANDR 0x20000000 86#define NPORT_DMODE1_LOSRC 0x30000000 87#define NPORT_DMODE1_LOANDI 0x40000000 88#define NPORT_DMODE1_LODST 0x50000000 89#define NPORT_DMODE1_LOXOR 0x60000000 90#define NPORT_DMODE1_LOOR 0x70000000 91#define NPORT_DMODE1_LONOR 0x80000000 92#define NPORT_DMODE1_LOXNOR 0x90000000 93#define NPORT_DMODE1_LONDST 0xa0000000 94#define NPORT_DMODE1_LOORR 0xb0000000 95#define NPORT_DMODE1_LONSRC 0xc0000000 96#define NPORT_DMODE1_LOORI 0xd0000000 97#define NPORT_DMODE1_LONAND 0xe0000000 98#define NPORT_DMODE1_LOONE 0xf0000000 99 100 npireg_t drawmode0; /* REX command register */ 101 102 /* These bits define the graphics opcode being performed. */ 103#define NPORT_DMODE0_OPMASK 0x00000003 /* Opcode mask */ 104#define NPORT_DMODE0_NOP 0x00000000 /* No operation */ 105#define NPORT_DMODE0_RD 0x00000001 /* Read operation */ 106#define NPORT_DMODE0_DRAW 0x00000002 /* Draw operation */ 107#define NPORT_DMODE0_S2S 0x00000003 /* Screen to screen operation */ 108 109 /* The following decide what addressing mode(s) are to be used */ 110#define NPORT_DMODE0_AMMASK 0x0000001c /* Address mode mask */ 111#define NPORT_DMODE0_SPAN 0x00000000 /* Spanning address mode */ 112#define NPORT_DMODE0_BLOCK 0x00000004 /* Block address mode */ 113#define NPORT_DMODE0_ILINE 0x00000008 /* Iline address mode */ 114#define NPORT_DMODE0_FLINE 0x0000000c /* Fline address mode */ 115#define NPORT_DMODE0_ALINE 0x00000010 /* Aline address mode */ 116#define NPORT_DMODE0_TLINE 0x00000014 /* Tline address mode */ 117#define NPORT_DMODE0_BLINE 0x00000018 /* Bline address mode */ 118 119 /* And now some misc. operation control bits. */ 120#define NPORT_DMODE0_DOSETUP 0x00000020 121#define NPORT_DMODE0_CHOST 0x00000040 122#define NPORT_DMODE0_AHOST 0x00000080 123#define NPORT_DMODE0_STOPX 0x00000100 124#define NPORT_DMODE0_STOPY 0x00000200 125#define NPORT_DMODE0_SK1ST 0x00000400 126#define NPORT_DMODE0_SKLST 0x00000800 127#define NPORT_DMODE0_ZPENAB 0x00001000 128#define NPORT_DMODE0_LISPENAB 0x00002000 129#define NPORT_DMODE0_LISLST 0x00004000 130#define NPORT_DMODE0_L32 0x00008000 131#define NPORT_DMODE0_ZOPQ 0x00010000 132#define NPORT_DMODE0_LISOPQ 0x00020000 133#define NPORT_DMODE0_SHADE 0x00040000 134#define NPORT_DMODE0_LRONLY 0x00080000 135#define NPORT_DMODE0_XYOFF 0x00100000 136#define NPORT_DMODE0_CLAMP 0x00200000 137#define NPORT_DMODE0_ENDPF 0x00400000 138#define NPORT_DMODE0_YSTR 0x00800000 139 140 npireg_t lsmode; /* Mode for line stipple ops */ 141 npireg_t lspattern; /* Pattern for line stipple ops */ 142 npireg_t lspatsave; /* Backup save pattern */ 143 npireg_t zpattern; /* Pixel zpattern */ 144 npireg_t colorback; /* Background color */ 145 npireg_t colorvram; /* Clear color for fast vram */ 146 npireg_t alpharef; /* Reference value for afunctions */ 147 unsigned int pad0; 148 npireg_t smask0x; /* Window GL relative screen mask 0 */ 149 npireg_t smask0y; /* Window GL relative screen mask 0 */ 150 npireg_t _setup; 151 npireg_t _stepz; 152 npireg_t _lsrestore; 153 npireg_t _lssave; 154 155 unsigned int _pad1[0x30]; 156 157 /* Iterators, full state for context switch */ 158 npfreg_t _xstart; /* X-start point (current) */ 159 npfreg_t _ystart; /* Y-start point (current) */ 160 npfreg_t _xend; /* x-end point */ 161 npfreg_t _yend; /* y-end point */ 162 npireg_t xsave; /* copy of xstart integer value for BLOCk addressing MODE */ 163 npireg_t xymove; /* x.y offset from xstart, ystart for relative operations */ 164 npfreg_t bresd; 165 npfreg_t bress1; 166 npireg_t bresoctinc1; 167 volatile int bresrndinc2; 168 npireg_t brese1; 169 npireg_t bress2; 170 npireg_t aweight0; 171 npireg_t aweight1; 172 npfreg_t xstartf; 173 npfreg_t ystartf; 174 npfreg_t xendf; 175 npfreg_t yendf; 176 npireg_t xstarti; 177 npfreg_t xendf1; 178 npireg_t xystarti; 179 npireg_t xyendi; 180 npireg_t xstartendi; 181 182 unsigned int _unused2[0x29]; 183 184 npfreg_t colorred; 185 npfreg_t coloralpha; 186 npfreg_t colorgrn; 187 npfreg_t colorblue; 188 npfreg_t slopered; 189 npfreg_t slopealpha; 190 npfreg_t slopegrn; 191 npfreg_t slopeblue; 192 npireg_t wrmask; 193 npireg_t colori; 194 npfreg_t colorx; 195 npfreg_t slopered1; 196 npireg_t hostrw0; 197 npireg_t hostrw1; 198 npireg_t dcbmode; 199#define NPORT_DMODE_WMASK 0x00000003 200#define NPORT_DMODE_W4 0x00000000 201#define NPORT_DMODE_W1 0x00000001 202#define NPORT_DMODE_W2 0x00000002 203#define NPORT_DMODE_W3 0x00000003 204#define NPORT_DMODE_EDPACK 0x00000004 205#define NPORT_DMODE_ECINC 0x00000008 206#define NPORT_DMODE_CMASK 0x00000070 207#define NPORT_DMODE_AMASK 0x00000780 208#define NPORT_DMODE_AVC2 0x00000000 209#define NPORT_DMODE_ACMALL 0x00000080 210#define NPORT_DMODE_ACM0 0x00000100 211#define NPORT_DMODE_ACM1 0x00000180 212#define NPORT_DMODE_AXMALL 0x00000200 213#define NPORT_DMODE_AXM0 0x00000280 214#define NPORT_DMODE_AXM1 0x00000300 215#define NPORT_DMODE_ABT 0x00000380 216#define NPORT_DMODE_AVCC1 0x00000400 217#define NPORT_DMODE_AVAB1 0x00000480 218#define NPORT_DMODE_ALG3V0 0x00000500 219#define NPORT_DMODE_A1562 0x00000580 220#define NPORT_DMODE_ESACK 0x00000800 221#define NPORT_DMODE_EASACK 0x00001000 222#define NPORT_DMODE_CWMASK 0x0003e000 223#define NPORT_DMODE_CHMASK 0x007c0000 224#define NPORT_DMODE_CSMASK 0x0f800000 225#define NPORT_DMODE_SENDIAN 0x10000000 226 227 unsigned int _unused3; 228 229 union np_dcb dcbdata0; 230 npireg_t dcbdata1; 231}; 232 233struct newport_cregs { 234 npireg_t smask1x; 235 npireg_t smask1y; 236 npireg_t smask2x; 237 npireg_t smask2y; 238 npireg_t smask3x; 239 npireg_t smask3y; 240 npireg_t smask4x; 241 npireg_t smask4y; 242 npireg_t topscan; 243 npireg_t xywin; 244 npireg_t clipmode; 245#define NPORT_CMODE_SM0 0x00000001 246#define NPORT_CMODE_SM1 0x00000002 247#define NPORT_CMODE_SM2 0x00000004 248#define NPORT_CMODE_SM3 0x00000008 249#define NPORT_CMODE_SM4 0x00000010 250#define NPORT_CMODE_CMSK 0x00001e00 251 252 unsigned int _unused0; 253 unsigned int config; 254#define NPORT_CFG_G32MD 0x00000001 255#define NPORT_CFG_BWIDTH 0x00000002 256#define NPORT_CFG_ERCVR 0x00000004 257#define NPORT_CFG_BDMSK 0x00000078 258#define NPORT_CFG_BFAINT 0x00000080 259#define NPORT_CFG_GDMSK 0x00001f80 260#define NPORT_CFG_GD0 0x00000100 261#define NPORT_CFG_GD1 0x00000200 262#define NPORT_CFG_GD2 0x00000400 263#define NPORT_CFG_GD3 0x00000800 264#define NPORT_CFG_GD4 0x00001000 265#define NPORT_CFG_GFAINT 0x00002000 266#define NPORT_CFG_TOMSK 0x0001c000 267#define NPORT_CFG_VRMSK 0x000e0000 268#define NPORT_CFG_FBTYP 0x00100000 269 270 npireg_t _unused1; 271 npireg_t status; 272#define NPORT_STAT_VERS 0x00000007 273#define NPORT_STAT_GBUSY 0x00000008 274#define NPORT_STAT_BBUSY 0x00000010 275#define NPORT_STAT_VRINT 0x00000020 276#define NPORT_STAT_VIDINT 0x00000040 277#define NPORT_STAT_GLMSK 0x00001f80 278#define NPORT_STAT_BLMSK 0x0007e000 279#define NPORT_STAT_BFIRQ 0x00080000 280#define NPORT_STAT_GFIRQ 0x00100000 281 282 npireg_t ustatus; 283 npireg_t dcbreset; 284}; 285 286struct newport_regs { 287 struct newport_rexregs set; 288 unsigned int _unused0[0x16e]; 289 struct newport_rexregs go; 290 unsigned int _unused1[0x22e]; 291 struct newport_cregs cset; 292 unsigned int _unused2[0x1ef]; 293 struct newport_cregs cgo; 294}; 295 296typedef struct { 297 unsigned int drawmode1; 298 unsigned int drawmode0; 299 unsigned int lsmode; 300 unsigned int lspattern; 301 unsigned int lspatsave; 302 unsigned int zpattern; 303 unsigned int colorback; 304 unsigned int colorvram; 305 unsigned int alpharef; 306 unsigned int smask0x; 307 unsigned int smask0y; 308 unsigned int _xstart; 309 unsigned int _ystart; 310 unsigned int _xend; 311 unsigned int _yend; 312 unsigned int xsave; 313 unsigned int xymove; 314 unsigned int bresd; 315 unsigned int bress1; 316 unsigned int bresoctinc1; 317 unsigned int bresrndinc2; 318 unsigned int brese1; 319 unsigned int bress2; 320 321 unsigned int aweight0; 322 unsigned int aweight1; 323 unsigned int colorred; 324 unsigned int coloralpha; 325 unsigned int colorgrn; 326 unsigned int colorblue; 327 unsigned int slopered; 328 unsigned int slopealpha; 329 unsigned int slopegrn; 330 unsigned int slopeblue; 331 unsigned int wrmask; 332 unsigned int hostrw0; 333 unsigned int hostrw1; 334 335 /* configregs */ 336 337 unsigned int smask1x; 338 unsigned int smask1y; 339 unsigned int smask2x; 340 unsigned int smask2y; 341 unsigned int smask3x; 342 unsigned int smask3y; 343 unsigned int smask4x; 344 unsigned int smask4y; 345 unsigned int topscan; 346 unsigned int xywin; 347 unsigned int clipmode; 348 unsigned int config; 349 350 /* dcb registers */ 351 unsigned int dcbmode; 352 unsigned int dcbdata0; 353 unsigned int dcbdata1; 354} newport_ctx; 355 356/* Reading/writing VC2 registers. */ 357#define VC2_REGADDR_INDEX 0x00000000 358#define VC2_REGADDR_IREG 0x00000010 359#define VC2_REGADDR_RAM 0x00000030 360#define VC2_PROTOCOL (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000) 361 362#define VC2_VLINET_ADDR 0x000 363#define VC2_VFRAMET_ADDR 0x400 364#define VC2_CGLYPH_ADDR 0x500 365 366/* Now the Indexed registers of the VC2. */ 367#define VC2_IREG_VENTRY 0x00 368#define VC2_IREG_CENTRY 0x01 369#define VC2_IREG_CURSX 0x02 370#define VC2_IREG_CURSY 0x03 371#define VC2_IREG_CCURSX 0x04 372#define VC2_IREG_DENTRY 0x05 373#define VC2_IREG_SLEN 0x06 374#define VC2_IREG_RADDR 0x07 375#define VC2_IREG_VFPTR 0x08 376#define VC2_IREG_VLSPTR 0x09 377#define VC2_IREG_VLIR 0x0a 378#define VC2_IREG_VLCTR 0x0b 379#define VC2_IREG_CTPTR 0x0c 380#define VC2_IREG_WCURSY 0x0d 381#define VC2_IREG_DFPTR 0x0e 382#define VC2_IREG_DLTPTR 0x0f 383#define VC2_IREG_CONTROL 0x10 384#define VC2_IREG_CONFIG 0x20 385 386static inline void newport_vc2_set(struct newport_regs *regs, 387 unsigned char vc2ireg, 388 unsigned short val) 389{ 390 regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W3 | 391 NPORT_DMODE_ECINC | VC2_PROTOCOL); 392 regs->set.dcbdata0.byword = (vc2ireg << 24) | (val << 8); 393} 394 395static inline unsigned short newport_vc2_get(struct newport_regs *regs, 396 unsigned char vc2ireg) 397{ 398 regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W1 | 399 NPORT_DMODE_ECINC | VC2_PROTOCOL); 400 regs->set.dcbdata0.bybytes.b3 = vc2ireg; 401 regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_IREG | NPORT_DMODE_W2 | 402 NPORT_DMODE_ECINC | VC2_PROTOCOL); 403 return regs->set.dcbdata0.byshort.s1; 404} 405 406/* VC2 Control register bits */ 407#define VC2_CTRL_EVIRQ 0x0001 408#define VC2_CTRL_EDISP 0x0002 409#define VC2_CTRL_EVIDEO 0x0004 410#define VC2_CTRL_EDIDS 0x0008 411#define VC2_CTRL_ECURS 0x0010 412#define VC2_CTRL_EGSYNC 0x0020 413#define VC2_CTRL_EILACE 0x0040 414#define VC2_CTRL_ECDISP 0x0080 415#define VC2_CTRL_ECCURS 0x0100 416#define VC2_CTRL_ECG64 0x0200 417#define VC2_CTRL_GLSEL 0x0400 418 419/* Controlling the color map on NEWPORT. */ 420#define NCMAP_REGADDR_AREG 0x00000000 421#define NCMAP_REGADDR_ALO 0x00000000 422#define NCMAP_REGADDR_AHI 0x00000010 423#define NCMAP_REGADDR_PBUF 0x00000020 424#define NCMAP_REGADDR_CREG 0x00000030 425#define NCMAP_REGADDR_SREG 0x00000040 426#define NCMAP_REGADDR_RREG 0x00000060 427#define NCMAP_PROTOCOL (0x00008000 | 0x00040000 | 0x00800000) 428 429static __inline__ void newport_cmap_setaddr(struct newport_regs *regs, 430 unsigned short addr) 431{ 432 regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL | 433 NPORT_DMODE_SENDIAN | NPORT_DMODE_ECINC | 434 NCMAP_REGADDR_AREG | NPORT_DMODE_W2); 435 regs->set.dcbdata0.byshort.s1 = addr; 436 regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL | 437 NCMAP_REGADDR_PBUF | NPORT_DMODE_W3); 438} 439 440static __inline__ void newport_cmap_setrgb(struct newport_regs *regs, 441 unsigned char red, 442 unsigned char green, 443 unsigned char blue) 444{ 445 regs->set.dcbdata0.byword = 446 (red << 24) | 447 (green << 16) | 448 (blue << 8); 449} 450 451/* Miscellaneous NEWPORT routines. */ 452#define BUSY_TIMEOUT 100000 453static __inline__ int newport_wait(struct newport_regs *regs) 454{ 455 int t = BUSY_TIMEOUT; 456 457 while (--t) 458 if (!(regs->cset.status & NPORT_STAT_GBUSY)) 459 break; 460 return !t; 461} 462 463static __inline__ int newport_bfwait(struct newport_regs *regs) 464{ 465 int t = BUSY_TIMEOUT; 466 467 while (--t) 468 if(!(regs->cset.status & NPORT_STAT_BBUSY)) 469 break; 470 return !t; 471} 472 473/* 474 * DCBMODE register defines: 475 */ 476 477/* Width of the data being transferred for each DCBDATA[01] word */ 478#define DCB_DATAWIDTH_4 0x0 479#define DCB_DATAWIDTH_1 0x1 480#define DCB_DATAWIDTH_2 0x2 481#define DCB_DATAWIDTH_3 0x3 482 483/* If set, all of DCBDATA will be moved, otherwise only DATAWIDTH bytes */ 484#define DCB_ENDATAPACK (1 << 2) 485 486/* Enables DCBCRS auto increment after each DCB transfer */ 487#define DCB_ENCRSINC (1 << 3) 488 489/* shift for accessing the control register select address (DBCCRS, 3 bits) */ 490#define DCB_CRS_SHIFT 4 491 492/* DCBADDR (4 bits): display bus slave address */ 493#define DCB_ADDR_SHIFT 7 494#define DCB_VC2 (0 << DCB_ADDR_SHIFT) 495#define DCB_CMAP_ALL (1 << DCB_ADDR_SHIFT) 496#define DCB_CMAP0 (2 << DCB_ADDR_SHIFT) 497#define DCB_CMAP1 (3 << DCB_ADDR_SHIFT) 498#define DCB_XMAP_ALL (4 << DCB_ADDR_SHIFT) 499#define DCB_XMAP0 (5 << DCB_ADDR_SHIFT) 500#define DCB_XMAP1 (6 << DCB_ADDR_SHIFT) 501#define DCB_BT445 (7 << DCB_ADDR_SHIFT) 502#define DCB_VCC1 (8 << DCB_ADDR_SHIFT) 503#define DCB_VAB1 (9 << DCB_ADDR_SHIFT) 504#define DCB_LG3_BDVERS0 (10 << DCB_ADDR_SHIFT) 505#define DCB_LG3_ICS1562 (11 << DCB_ADDR_SHIFT) 506#define DCB_RESERVED (15 << DCB_ADDR_SHIFT) 507 508/* DCB protocol ack types */ 509#define DCB_ENSYNCACK (1 << 11) 510#define DCB_ENASYNCACK (1 << 12) 511 512#define DCB_CSWIDTH_SHIFT 13 513#define DCB_CSHOLD_SHIFT 18 514#define DCB_CSSETUP_SHIFT 23 515 516/* XMAP9 specific defines */ 517/* XMAP9 -- registers as seen on the DCBMODE register*/ 518# define XM9_CRS_CONFIG (0 << DCB_CRS_SHIFT) 519# define XM9_PUPMODE (1 << 0) 520# define XM9_ODD_PIXEL (1 << 1) 521# define XM9_8_BITPLANES (1 << 2) 522# define XM9_SLOW_DCB (1 << 3) 523# define XM9_VIDEO_RGBMAP_MASK (3 << 4) 524# define XM9_EXPRESS_VIDEO (1 << 6) 525# define XM9_VIDEO_OPTION (1 << 7) 526# define XM9_CRS_REVISION (1 << DCB_CRS_SHIFT) 527# define XM9_CRS_FIFO_AVAIL (2 << DCB_CRS_SHIFT) 528# define XM9_FIFO_0_AVAIL 0 529# define XM9_FIFO_1_AVAIL 1 530# define XM9_FIFO_2_AVAIL 3 531# define XM9_FIFO_3_AVAIL 2 532# define XM9_FIFO_FULL XM9_FIFO_0_AVAIL 533# define XM9_FIFO_EMPTY XM9_FIFO_3_AVAIL 534# define XM9_CRS_CURS_CMAP_MSB (3 << DCB_CRS_SHIFT) 535# define XM9_CRS_PUP_CMAP_MSB (4 << DCB_CRS_SHIFT) 536# define XM9_CRS_MODE_REG_DATA (5 << DCB_CRS_SHIFT) 537# define XM9_CRS_MODE_REG_INDEX (7 << DCB_CRS_SHIFT) 538 539 540#define DCB_CYCLES(setup,hold,width) \ 541 ((hold << DCB_CSHOLD_SHIFT) | \ 542 (setup << DCB_CSSETUP_SHIFT)| \ 543 (width << DCB_CSWIDTH_SHIFT)) 544 545#define W_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 0) 546#define WSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (5, 5, 0) 547#define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0) 548#define R_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 3) 549 550static __inline__ void 551xmap9FIFOWait (struct newport_regs *rex) 552{ 553 rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL | 554 DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL; 555 newport_bfwait (rex); 556 557 while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY) 558 ; 559} 560 561static __inline__ void 562xmap9SetModeReg (struct newport_regs *rex, unsigned int modereg, unsigned int data24, int cfreq) 563{ 564 if (cfreq > 119) 565 rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | 566 DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL; 567 else if (cfreq > 59) 568 rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | 569 DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL; 570 else 571 rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | 572 DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL; 573 rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff); 574} 575 576#define BT445_PROTOCOL DCB_CYCLES(1,1,3) 577 578#define BT445_CSR_ADDR_REG (0 << DCB_CRS_SHIFT) 579#define BT445_CSR_REVISION (2 << DCB_CRS_SHIFT) 580 581#define BT445_REVISION_REG 0x01 582 583#endif /* !(_SGI_NEWPORT_H) */ 584 585