1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 4 */ 5 6#ifndef _UNIPRO_H_ 7#define _UNIPRO_H_ 8 9/* 10 * M-TX Configuration Attributes 11 */ 12#define TX_HIBERN8TIME_CAPABILITY 0x000F 13#define TX_MODE 0x0021 14#define TX_HSRATE_SERIES 0x0022 15#define TX_HSGEAR 0x0023 16#define TX_PWMGEAR 0x0024 17#define TX_AMPLITUDE 0x0025 18#define TX_HS_SLEWRATE 0x0026 19#define TX_SYNC_SOURCE 0x0027 20#define TX_HS_SYNC_LENGTH 0x0028 21#define TX_HS_PREPARE_LENGTH 0x0029 22#define TX_LS_PREPARE_LENGTH 0x002A 23#define TX_HIBERN8_CONTROL 0x002B 24#define TX_LCC_ENABLE 0x002C 25#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D 26#define TX_BYPASS_8B10B_ENABLE 0x002E 27#define TX_DRIVER_POLARITY 0x002F 28#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030 29#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031 30#define TX_LCC_SEQUENCER 0x0032 31#define TX_MIN_ACTIVATETIME 0x0033 32#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034 33#define TX_REFCLKFREQ 0x00EB 34#define TX_CFGCLKFREQVAL 0x00EC 35#define CFGEXTRATTR 0x00F0 36#define DITHERCTRL2 0x00F1 37 38/* 39 * M-RX Configuration Attributes 40 */ 41#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B 42#define RX_HS_G1_PREP_LENGTH_CAP 0x008C 43#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F 44#define RX_HIBERN8TIME_CAPABILITY 0x0092 45#define RX_HS_G2_SYNC_LENGTH_CAP 0x0094 46#define RX_HS_G3_SYNC_LENGTH_CAP 0x0095 47#define RX_HS_G2_PREP_LENGTH_CAP 0x0096 48#define RX_HS_G3_PREP_LENGTH_CAP 0x0097 49#define RX_ADV_GRANULARITY_CAP 0x0098 50#define RX_HIBERN8TIME_CAP 0x0092 51#define RX_ADV_HIBERN8TIME_CAP 0x0099 52#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A 53#define RX_MODE 0x00A1 54#define RX_HSRATE_SERIES 0x00A2 55#define RX_HSGEAR 0x00A3 56#define RX_PWMGEAR 0x00A4 57#define RX_LS_TERMINATED_ENABLE 0x00A5 58#define RX_HS_UNTERMINATED_ENABLE 0x00A6 59#define RX_ENTER_HIBERN8 0x00A7 60#define RX_BYPASS_8B10B_ENABLE 0x00A8 61#define RX_TERMINATION_FORCE_ENABLE 0x00A9 62#define RXCALCTRL 0x00B4 63#define RXSQCTRL 0x00B5 64#define CFGRXCDR8 0x00BA 65#define CFGRXOVR8 0x00BD 66#define CFGRXOVR6 0x00BF 67#define RXDIRECTCTRL2 0x00C7 68#define CFGRXOVR4 0x00E9 69#define RX_REFCLKFREQ 0x00EB 70#define RX_CFGCLKFREQVAL 0x00EC 71#define CFGWIDEINLN 0x00F0 72#define ENARXDIRECTCFG4 0x00F2 73#define ENARXDIRECTCFG3 0x00F3 74#define ENARXDIRECTCFG2 0x00F4 75 76 77#define is_mphy_tx_attr(attr) (attr < RX_MODE) 78#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1) 79#define SYNC_LEN_FINE(x) ((x) & 0x3F) 80#define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F)) 81#define PREP_LEN(x) ((x) & 0xF) 82 83#define RX_MIN_ACTIVATETIME_UNIT_US 100 84#define HIBERN8TIME_UNIT_US 100 85 86/* 87 * Common Block Attributes 88 */ 89#define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B) 90#define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF) 91#define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD) 92#define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6) 93#define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA) 94#define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0) 95#define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1) 96#define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3) 97#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8) 98#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB) 99 100#define UNIPRO_CB_OFFSET(x) (0x8000 | x) 101 102/* 103 * PHY Adapter attributes 104 */ 105#define PA_PHY_TYPE 0x1500 106#define PA_AVAILTXDATALANES 0x1520 107#define PA_MAXTXSPEEDFAST 0x1521 108#define PA_MAXTXSPEEDSLOW 0x1522 109#define PA_MAXRXSPEEDFAST 0x1541 110#define PA_MAXRXSPEEDSLOW 0x1542 111#define PA_TXLINKSTARTUPHS 0x1544 112#define PA_AVAILRXDATALANES 0x1540 113#define PA_MINRXTRAILINGCLOCKS 0x1543 114#define PA_LOCAL_TX_LCC_ENABLE 0x155E 115#define PA_ACTIVETXDATALANES 0x1560 116#define PA_CONNECTEDTXDATALANES 0x1561 117#define PA_TXFORCECLOCK 0x1562 118#define PA_TXPWRMODE 0x1563 119#define PA_TXTRAILINGCLOCKS 0x1564 120#define PA_TXSPEEDFAST 0x1565 121#define PA_TXSPEEDSLOW 0x1566 122#define PA_TXPWRSTATUS 0x1567 123#define PA_TXGEAR 0x1568 124#define PA_TXTERMINATION 0x1569 125#define PA_HSSERIES 0x156A 126#define PA_LEGACYDPHYESCDL 0x1570 127#define PA_PWRMODE 0x1571 128#define PA_ACTIVERXDATALANES 0x1580 129#define PA_CONNECTEDRXDATALANES 0x1581 130#define PA_RXPWRSTATUS 0x1582 131#define PA_RXGEAR 0x1583 132#define PA_RXTERMINATION 0x1584 133#define PA_MAXRXPWMGEAR 0x1586 134#define PA_MAXRXHSGEAR 0x1587 135#define PA_PACPREQTIMEOUT 0x1590 136#define PA_PACPREQEOBTIMEOUT 0x1591 137#define PA_REMOTEVERINFO 0x15A0 138#define PA_LOGICALLANEMAP 0x15A1 139#define PA_SLEEPNOCONFIGTIME 0x15A2 140#define PA_STALLNOCONFIGTIME 0x15A3 141#define PA_SAVECONFIGTIME 0x15A4 142#define PA_RXHSUNTERMCAP 0x15A5 143#define PA_RXLSTERMCAP 0x15A6 144#define PA_HIBERN8TIME 0x15A7 145#define PA_LOCALVERINFO 0x15A9 146#define PA_GRANULARITY 0x15AA 147#define PA_TACTIVATE 0x15A8 148#define PA_PWRMODEUSERDATA0 0x15B0 149#define PA_PWRMODEUSERDATA1 0x15B1 150#define PA_PWRMODEUSERDATA2 0x15B2 151#define PA_PWRMODEUSERDATA3 0x15B3 152#define PA_PWRMODEUSERDATA4 0x15B4 153#define PA_PWRMODEUSERDATA5 0x15B5 154#define PA_PWRMODEUSERDATA6 0x15B6 155#define PA_PWRMODEUSERDATA7 0x15B7 156#define PA_PWRMODEUSERDATA8 0x15B8 157#define PA_PWRMODEUSERDATA9 0x15B9 158#define PA_PWRMODEUSERDATA10 0x15BA 159#define PA_PWRMODEUSERDATA11 0x15BB 160#define PA_PACPFRAMECOUNT 0x15C0 161#define PA_PACPERRORCOUNT 0x15C1 162#define PA_PHYTESTCONTROL 0x15C2 163#define PA_TXHSADAPTTYPE 0x15D4 164 165/* Adpat type for PA_TXHSADAPTTYPE attribute */ 166#define PA_REFRESH_ADAPT 0x00 167#define PA_INITIAL_ADAPT 0x01 168#define PA_NO_ADAPT 0x03 169 170#define PA_TACTIVATE_TIME_UNIT_US 10 171#define PA_HIBERN8_TIME_UNIT_US 100 172 173/*Other attributes*/ 174#define VS_POWERSTATE 0xD083 175#define VS_MPHYCFGUPDT 0xD085 176#define VS_DEBUGOMC 0xD09E 177 178#define PA_GRANULARITY_MIN_VAL 1 179#define PA_GRANULARITY_MAX_VAL 6 180 181/* PHY Adapter Protocol Constants */ 182#define PA_MAXDATALANES 4 183 184#define DL_FC0ProtectionTimeOutVal_Default 8191 185#define DL_TC0ReplayTimeOutVal_Default 65535 186#define DL_AFC0ReqTimeOutVal_Default 32767 187#define DL_FC1ProtectionTimeOutVal_Default 8191 188#define DL_TC1ReplayTimeOutVal_Default 65535 189#define DL_AFC1ReqTimeOutVal_Default 32767 190 191#define DME_LocalFC0ProtectionTimeOutVal 0xD041 192#define DME_LocalTC0ReplayTimeOutVal 0xD042 193#define DME_LocalAFC0ReqTimeOutVal 0xD043 194 195/* PA power modes */ 196enum ufs_pa_pwr_mode { 197 FAST_MODE = 1, 198 SLOW_MODE = 2, 199 FASTAUTO_MODE = 4, 200 SLOWAUTO_MODE = 5, 201 UNCHANGED = 7, 202}; 203 204#define PWRMODE_MASK 0xF 205#define PWRMODE_RX_OFFSET 4 206 207/* PA TX/RX Frequency Series */ 208enum ufs_hs_gear_rate { 209 PA_HS_MODE_A = 1, 210 PA_HS_MODE_B = 2, 211}; 212 213enum ufs_pwm_gear_tag { 214 UFS_PWM_DONT_CHANGE, /* Don't change Gear */ 215 UFS_PWM_G1, /* PWM Gear 1 (default for reset) */ 216 UFS_PWM_G2, /* PWM Gear 2 */ 217 UFS_PWM_G3, /* PWM Gear 3 */ 218 UFS_PWM_G4, /* PWM Gear 4 */ 219 UFS_PWM_G5, /* PWM Gear 5 */ 220 UFS_PWM_G6, /* PWM Gear 6 */ 221 UFS_PWM_G7, /* PWM Gear 7 */ 222}; 223 224enum ufs_hs_gear_tag { 225 UFS_HS_DONT_CHANGE, /* Don't change Gear */ 226 UFS_HS_G1, /* HS Gear 1 (default for reset) */ 227 UFS_HS_G2, /* HS Gear 2 */ 228 UFS_HS_G3, /* HS Gear 3 */ 229 UFS_HS_G4, /* HS Gear 4 */ 230 UFS_HS_G5 /* HS Gear 5 */ 231}; 232 233enum ufs_lanes { 234 UFS_LANE_DONT_CHANGE, /* Don't change Lane */ 235 UFS_LANE_1, /* Lane 1 (default for reset) */ 236 UFS_LANE_2, /* Lane 2 */ 237}; 238 239enum ufs_unipro_ver { 240 UFS_UNIPRO_VER_RESERVED = 0, 241 UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */ 242 UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */ 243 UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */ 244 UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */ 245 UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */ 246 UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */ 247 /* UniPro version field mask in PA_LOCALVERINFO */ 248 UFS_UNIPRO_VER_MASK = 0xF, 249}; 250 251/* 252 * Data Link Layer Attributes 253 */ 254#define DL_TXPREEMPTIONCAP 0x2000 255#define DL_TC0TXMAXSDUSIZE 0x2001 256#define DL_TC0RXINITCREDITVAL 0x2002 257#define DL_TC1TXMAXSDUSIZE 0x2003 258#define DL_TC1RXINITCREDITVAL 0x2004 259#define DL_TC0TXBUFFERSIZE 0x2005 260#define DL_TC1TXBUFFERSIZE 0x2006 261#define DL_TC0TXFCTHRESHOLD 0x2040 262#define DL_FC0PROTTIMEOUTVAL 0x2041 263#define DL_TC0REPLAYTIMEOUTVAL 0x2042 264#define DL_AFC0REQTIMEOUTVAL 0x2043 265#define DL_AFC0CREDITTHRESHOLD 0x2044 266#define DL_TC0OUTACKTHRESHOLD 0x2045 267#define DL_PEERTC0PRESENT 0x2046 268#define DL_PEERTC0RXINITCREVAL 0x2047 269#define DL_TC1TXFCTHRESHOLD 0x2060 270#define DL_FC1PROTTIMEOUTVAL 0x2061 271#define DL_TC1REPLAYTIMEOUTVAL 0x2062 272#define DL_AFC1REQTIMEOUTVAL 0x2063 273#define DL_AFC1CREDITTHRESHOLD 0x2064 274#define DL_TC1OUTACKTHRESHOLD 0x2065 275#define DL_PEERTC1PRESENT 0x2066 276#define DL_PEERTC1RXINITCREVAL 0x2067 277 278/* 279 * Network Layer Attributes 280 */ 281#define N_DEVICEID 0x3000 282#define N_DEVICEID_VALID 0x3001 283#define N_TC0TXMAXSDUSIZE 0x3020 284#define N_TC1TXMAXSDUSIZE 0x3021 285 286/* 287 * Transport Layer Attributes 288 */ 289#define T_NUMCPORTS 0x4000 290#define T_NUMTESTFEATURES 0x4001 291#define T_CONNECTIONSTATE 0x4020 292#define T_PEERDEVICEID 0x4021 293#define T_PEERCPORTID 0x4022 294#define T_TRAFFICCLASS 0x4023 295#define T_PROTOCOLID 0x4024 296#define T_CPORTFLAGS 0x4025 297#define T_TXTOKENVALUE 0x4026 298#define T_RXTOKENVALUE 0x4027 299#define T_LOCALBUFFERSPACE 0x4028 300#define T_PEERBUFFERSPACE 0x4029 301#define T_CREDITSTOSEND 0x402A 302#define T_CPORTMODE 0x402B 303#define T_TC0TXMAXSDUSIZE 0x4060 304#define T_TC1TXMAXSDUSIZE 0x4061 305 306/* CPort setting */ 307#define E2EFC_ON (1 << 0) 308#define E2EFC_OFF (0 << 0) 309#define CSD_N_ON (0 << 1) 310#define CSD_N_OFF (1 << 1) 311#define CSV_N_ON (0 << 2) 312#define CSV_N_OFF (1 << 2) 313#define CPORT_DEF_FLAGS (CSV_N_OFF | CSD_N_OFF | E2EFC_OFF) 314 315/* CPort connection state */ 316enum { 317 CPORT_IDLE = 0, 318 CPORT_CONNECTED, 319}; 320 321#endif /* _UNIPRO_H_ */ 322