1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRM_H__ 26#define __NOUVEAU_DRM_H__ 27 28#define DRM_NOUVEAU_EVENT_NVIF 0x80000000 29 30#include "drm.h" 31 32#if defined(__cplusplus) 33extern "C" { 34#endif 35 36#define NOUVEAU_GETPARAM_PCI_VENDOR 3 37#define NOUVEAU_GETPARAM_PCI_DEVICE 4 38#define NOUVEAU_GETPARAM_BUS_TYPE 5 39#define NOUVEAU_GETPARAM_FB_SIZE 8 40#define NOUVEAU_GETPARAM_AGP_SIZE 9 41#define NOUVEAU_GETPARAM_CHIPSET_ID 11 42#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 43#define NOUVEAU_GETPARAM_GRAPH_UNITS 13 44#define NOUVEAU_GETPARAM_PTIMER_TIME 14 45#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 46#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 47 48/* 49 * NOUVEAU_GETPARAM_EXEC_PUSH_MAX - query max pushes through getparam 50 * 51 * Query the maximum amount of IBs that can be pushed through a single 52 * &drm_nouveau_exec structure and hence a single &DRM_IOCTL_NOUVEAU_EXEC 53 * ioctl(). 54 */ 55#define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17 56 57/* 58 * NOUVEAU_GETPARAM_VRAM_BAR_SIZE - query bar size 59 * 60 * Query the VRAM BAR size. 61 */ 62#define NOUVEAU_GETPARAM_VRAM_BAR_SIZE 18 63 64/* 65 * NOUVEAU_GETPARAM_VRAM_USED 66 * 67 * Get remaining VRAM size. 68 */ 69#define NOUVEAU_GETPARAM_VRAM_USED 19 70 71struct drm_nouveau_getparam { 72 __u64 param; 73 __u64 value; 74}; 75 76struct drm_nouveau_channel_alloc { 77 __u32 fb_ctxdma_handle; 78 __u32 tt_ctxdma_handle; 79 80 __s32 channel; 81 __u32 pushbuf_domains; 82 83 /* Notifier memory */ 84 __u32 notifier_handle; 85 86 /* DRM-enforced subchannel assignments */ 87 struct { 88 __u32 handle; 89 __u32 grclass; 90 } subchan[8]; 91 __u32 nr_subchan; 92}; 93 94struct drm_nouveau_channel_free { 95 __s32 channel; 96}; 97 98#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 99#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 100#define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 101#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) 102#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) 103/* The BO will never be shared via import or export. */ 104#define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5) 105 106#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ 107#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 108#define NOUVEAU_GEM_TILE_16BPP 0x00000001 109#define NOUVEAU_GEM_TILE_32BPP 0x00000002 110#define NOUVEAU_GEM_TILE_ZETA 0x00000004 111#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 112 113struct drm_nouveau_gem_info { 114 __u32 handle; 115 __u32 domain; 116 __u64 size; 117 __u64 offset; 118 __u64 map_handle; 119 __u32 tile_mode; 120 __u32 tile_flags; 121}; 122 123struct drm_nouveau_gem_new { 124 struct drm_nouveau_gem_info info; 125 __u32 channel_hint; 126 __u32 align; 127}; 128 129#define NOUVEAU_GEM_MAX_BUFFERS 1024 130struct drm_nouveau_gem_pushbuf_bo_presumed { 131 __u32 valid; 132 __u32 domain; 133 __u64 offset; 134}; 135 136struct drm_nouveau_gem_pushbuf_bo { 137 __u64 user_priv; 138 __u32 handle; 139 __u32 read_domains; 140 __u32 write_domains; 141 __u32 valid_domains; 142 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 143}; 144 145#define NOUVEAU_GEM_RELOC_LOW (1 << 0) 146#define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 147#define NOUVEAU_GEM_RELOC_OR (1 << 2) 148#define NOUVEAU_GEM_MAX_RELOCS 1024 149struct drm_nouveau_gem_pushbuf_reloc { 150 __u32 reloc_bo_index; 151 __u32 reloc_bo_offset; 152 __u32 bo_index; 153 __u32 flags; 154 __u32 data; 155 __u32 vor; 156 __u32 tor; 157}; 158 159#define NOUVEAU_GEM_MAX_PUSH 512 160struct drm_nouveau_gem_pushbuf_push { 161 __u32 bo_index; 162 __u32 pad; 163 __u64 offset; 164 __u64 length; 165#define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23) 166}; 167 168struct drm_nouveau_gem_pushbuf { 169 __u32 channel; 170 __u32 nr_buffers; 171 __u64 buffers; 172 __u32 nr_relocs; 173 __u32 nr_push; 174 __u64 relocs; 175 __u64 push; 176 __u32 suffix0; 177 __u32 suffix1; 178#define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0) 179 __u64 vram_available; 180 __u64 gart_available; 181}; 182 183#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 184#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 185struct drm_nouveau_gem_cpu_prep { 186 __u32 handle; 187 __u32 flags; 188}; 189 190struct drm_nouveau_gem_cpu_fini { 191 __u32 handle; 192}; 193 194/** 195 * struct drm_nouveau_sync - sync object 196 * 197 * This structure serves as synchronization mechanism for (potentially) 198 * asynchronous operations such as EXEC or VM_BIND. 199 */ 200struct drm_nouveau_sync { 201 /** 202 * @flags: the flags for a sync object 203 * 204 * The first 8 bits are used to determine the type of the sync object. 205 */ 206 __u32 flags; 207#define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0 208#define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1 209#define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf 210 /** 211 * @handle: the handle of the sync object 212 */ 213 __u32 handle; 214 /** 215 * @timeline_value: 216 * 217 * The timeline point of the sync object in case the syncobj is of 218 * type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ. 219 */ 220 __u64 timeline_value; 221}; 222 223/** 224 * struct drm_nouveau_vm_init - GPU VA space init structure 225 * 226 * Used to initialize the GPU's VA space for a user client, telling the kernel 227 * which portion of the VA space is managed by the UMD and kernel respectively. 228 * 229 * For the UMD to use the VM_BIND uAPI, this must be called before any BOs or 230 * channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails 231 * with -ENOSYS. 232 */ 233struct drm_nouveau_vm_init { 234 /** 235 * @kernel_managed_addr: start address of the kernel managed VA space 236 * region 237 */ 238 __u64 kernel_managed_addr; 239 /** 240 * @kernel_managed_size: size of the kernel managed VA space region in 241 * bytes 242 */ 243 __u64 kernel_managed_size; 244}; 245 246/** 247 * struct drm_nouveau_vm_bind_op - VM_BIND operation 248 * 249 * This structure represents a single VM_BIND operation. UMDs should pass 250 * an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field. 251 */ 252struct drm_nouveau_vm_bind_op { 253 /** 254 * @op: the operation type 255 * 256 * Supported values: 257 * 258 * %DRM_NOUVEAU_VM_BIND_OP_MAP - Map a GEM object to the GPU's VA 259 * space. Optionally, the &DRM_NOUVEAU_VM_BIND_SPARSE flag can be 260 * passed to instruct the kernel to create sparse mappings for the 261 * given range. 262 * 263 * %DRM_NOUVEAU_VM_BIND_OP_UNMAP - Unmap an existing mapping in the 264 * GPU's VA space. If the region the mapping is located in is a 265 * sparse region, new sparse mappings are created where the unmapped 266 * (memory backed) mapping was mapped previously. To remove a sparse 267 * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set. 268 */ 269 __u32 op; 270#define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0 271#define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1 272 /** 273 * @flags: the flags for a &drm_nouveau_vm_bind_op 274 * 275 * Supported values: 276 * 277 * %DRM_NOUVEAU_VM_BIND_SPARSE - Indicates that an allocated VA 278 * space region should be sparse. 279 */ 280 __u32 flags; 281#define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8) 282 /** 283 * @handle: the handle of the DRM GEM object to map 284 */ 285 __u32 handle; 286 /** 287 * @pad: 32 bit padding, should be 0 288 */ 289 __u32 pad; 290 /** 291 * @addr: 292 * 293 * the address the VA space region or (memory backed) mapping should be mapped to 294 */ 295 __u64 addr; 296 /** 297 * @bo_offset: the offset within the BO backing the mapping 298 */ 299 __u64 bo_offset; 300 /** 301 * @range: the size of the requested mapping in bytes 302 */ 303 __u64 range; 304}; 305 306/** 307 * struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND 308 */ 309struct drm_nouveau_vm_bind { 310 /** 311 * @op_count: the number of &drm_nouveau_vm_bind_op 312 */ 313 __u32 op_count; 314 /** 315 * @flags: the flags for a &drm_nouveau_vm_bind ioctl 316 * 317 * Supported values: 318 * 319 * %DRM_NOUVEAU_VM_BIND_RUN_ASYNC - Indicates that the given VM_BIND 320 * operation should be executed asynchronously by the kernel. 321 * 322 * If this flag is not supplied the kernel executes the associated 323 * operations synchronously and doesn't accept any &drm_nouveau_sync 324 * objects. 325 */ 326 __u32 flags; 327#define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1 328 /** 329 * @wait_count: the number of wait &drm_nouveau_syncs 330 */ 331 __u32 wait_count; 332 /** 333 * @sig_count: the number of &drm_nouveau_syncs to signal when finished 334 */ 335 __u32 sig_count; 336 /** 337 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for 338 */ 339 __u64 wait_ptr; 340 /** 341 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished 342 */ 343 __u64 sig_ptr; 344 /** 345 * @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute 346 */ 347 __u64 op_ptr; 348}; 349 350/** 351 * struct drm_nouveau_exec_push - EXEC push operation 352 * 353 * This structure represents a single EXEC push operation. UMDs should pass an 354 * array of this structure via struct drm_nouveau_exec's &push_ptr field. 355 */ 356struct drm_nouveau_exec_push { 357 /** 358 * @va: the virtual address of the push buffer mapping 359 */ 360 __u64 va; 361 /** 362 * @va_len: the length of the push buffer mapping 363 */ 364 __u32 va_len; 365 /** 366 * @flags: the flags for this push buffer mapping 367 */ 368 __u32 flags; 369#define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1 370}; 371 372/** 373 * struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC 374 */ 375struct drm_nouveau_exec { 376 /** 377 * @channel: the channel to execute the push buffer in 378 */ 379 __u32 channel; 380 /** 381 * @push_count: the number of &drm_nouveau_exec_push ops 382 */ 383 __u32 push_count; 384 /** 385 * @wait_count: the number of wait &drm_nouveau_syncs 386 */ 387 __u32 wait_count; 388 /** 389 * @sig_count: the number of &drm_nouveau_syncs to signal when finished 390 */ 391 __u32 sig_count; 392 /** 393 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for 394 */ 395 __u64 wait_ptr; 396 /** 397 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished 398 */ 399 __u64 sig_ptr; 400 /** 401 * @push_ptr: pointer to &drm_nouveau_exec_push ops 402 */ 403 __u64 push_ptr; 404}; 405 406#define DRM_NOUVEAU_GETPARAM 0x00 407#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */ 408#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 409#define DRM_NOUVEAU_CHANNEL_FREE 0x03 410#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */ 411#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */ 412#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */ 413#define DRM_NOUVEAU_NVIF 0x07 414#define DRM_NOUVEAU_SVM_INIT 0x08 415#define DRM_NOUVEAU_SVM_BIND 0x09 416#define DRM_NOUVEAU_VM_INIT 0x10 417#define DRM_NOUVEAU_VM_BIND 0x11 418#define DRM_NOUVEAU_EXEC 0x12 419#define DRM_NOUVEAU_GEM_NEW 0x40 420#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 421#define DRM_NOUVEAU_GEM_CPU_PREP 0x42 422#define DRM_NOUVEAU_GEM_CPU_FINI 0x43 423#define DRM_NOUVEAU_GEM_INFO 0x44 424 425struct drm_nouveau_svm_init { 426 __u64 unmanaged_addr; 427 __u64 unmanaged_size; 428}; 429 430struct drm_nouveau_svm_bind { 431 __u64 header; 432 __u64 va_start; 433 __u64 va_end; 434 __u64 npages; 435 __u64 stride; 436 __u64 result; 437 __u64 reserved0; 438 __u64 reserved1; 439}; 440 441#define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0 442#define NOUVEAU_SVM_BIND_COMMAND_BITS 8 443#define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1) 444#define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8 445#define NOUVEAU_SVM_BIND_PRIORITY_BITS 8 446#define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1) 447#define NOUVEAU_SVM_BIND_TARGET_SHIFT 16 448#define NOUVEAU_SVM_BIND_TARGET_BITS 32 449#define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff 450 451/* 452 * Below is use to validate ioctl argument, userspace can also use it to make 453 * sure that no bit are set beyond known fields for a given kernel version. 454 */ 455#define NOUVEAU_SVM_BIND_VALID_BITS 48 456#define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1) 457 458 459/* 460 * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory. 461 * result: number of page successfuly migrate to the target memory. 462 */ 463#define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0 464 465/* 466 * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory. 467 */ 468#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31) 469 470 471#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam) 472#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc) 473#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free) 474 475#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init) 476#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind) 477 478#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 479#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) 480#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) 481#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) 482#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) 483 484#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init) 485#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind) 486#define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec) 487#if defined(__cplusplus) 488} 489#endif 490 491#endif /* __NOUVEAU_DRM_H__ */ 492