1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright (C) 2015 Etnaviv Project
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program.  If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __ETNAVIV_DRM_H__
19#define __ETNAVIV_DRM_H__
20
21#include "drm.h"
22
23#if defined(__cplusplus)
24extern "C" {
25#endif
26
27/* Please note that modifications to all structs defined here are
28 * subject to backwards-compatibility constraints:
29 *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
30 *     user/kernel compatibility
31 *  2) Keep fields aligned to their size
32 *  3) Because of how drm_ioctl() works, we can add new fields at
33 *     the end of an ioctl if some care is taken: drm_ioctl() will
34 *     zero out the new fields at the tail of the ioctl, so a zero
35 *     value should have a backwards compatible meaning.  And for
36 *     output params, userspace won't see the newly added output
37 *     fields.. so that has to be somehow ok.
38 */
39
40/* timeouts are specified in clock-monotonic absolute times (to simplify
41 * restarting interrupted ioctls).  The following struct is logically the
42 * same as 'struct timespec' but 32/64b ABI safe.
43 */
44struct drm_etnaviv_timespec {
45	__s64 tv_sec;          /* seconds */
46	__s64 tv_nsec;         /* nanoseconds */
47};
48
49#define ETNAVIV_PARAM_GPU_MODEL                     0x01
50#define ETNAVIV_PARAM_GPU_REVISION                  0x02
51#define ETNAVIV_PARAM_GPU_FEATURES_0                0x03
52#define ETNAVIV_PARAM_GPU_FEATURES_1                0x04
53#define ETNAVIV_PARAM_GPU_FEATURES_2                0x05
54#define ETNAVIV_PARAM_GPU_FEATURES_3                0x06
55#define ETNAVIV_PARAM_GPU_FEATURES_4                0x07
56#define ETNAVIV_PARAM_GPU_FEATURES_5                0x08
57#define ETNAVIV_PARAM_GPU_FEATURES_6                0x09
58#define ETNAVIV_PARAM_GPU_FEATURES_7                0x0a
59#define ETNAVIV_PARAM_GPU_FEATURES_8                0x0b
60#define ETNAVIV_PARAM_GPU_FEATURES_9                0x0c
61#define ETNAVIV_PARAM_GPU_FEATURES_10               0x0d
62#define ETNAVIV_PARAM_GPU_FEATURES_11               0x0e
63#define ETNAVIV_PARAM_GPU_FEATURES_12               0x0f
64
65#define ETNAVIV_PARAM_GPU_STREAM_COUNT              0x10
66#define ETNAVIV_PARAM_GPU_REGISTER_MAX              0x11
67#define ETNAVIV_PARAM_GPU_THREAD_COUNT              0x12
68#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE         0x13
69#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT         0x14
70#define ETNAVIV_PARAM_GPU_PIXEL_PIPES               0x15
71#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
72#define ETNAVIV_PARAM_GPU_BUFFER_SIZE               0x17
73#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT         0x18
74#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS             0x19
75#define ETNAVIV_PARAM_GPU_NUM_VARYINGS              0x1a
76#define ETNAVIV_PARAM_SOFTPIN_START_ADDR            0x1b
77#define ETNAVIV_PARAM_GPU_PRODUCT_ID                0x1c
78#define ETNAVIV_PARAM_GPU_CUSTOMER_ID               0x1d
79#define ETNAVIV_PARAM_GPU_ECO_ID                    0x1e
80#define ETNAVIV_PARAM_GPU_NN_CORE_COUNT             0x1f
81#define ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE           0x20
82#define ETNAVIV_PARAM_GPU_TP_CORE_COUNT             0x21
83#define ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE         0x22
84#define ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE             0x23
85
86#define ETNA_MAX_PIPES 4
87
88struct drm_etnaviv_param {
89	__u32 pipe;           /* in */
90	__u32 param;          /* in, ETNAVIV_PARAM_x */
91	__u64 value;          /* out (get_param) or in (set_param) */
92};
93
94/*
95 * GEM buffers:
96 */
97
98#define ETNA_BO_CACHE_MASK   0x000f0000
99/* cache modes */
100#define ETNA_BO_CACHED       0x00010000
101#define ETNA_BO_WC           0x00020000
102#define ETNA_BO_UNCACHED     0x00040000
103/* map flags */
104#define ETNA_BO_FORCE_MMU    0x00100000
105
106struct drm_etnaviv_gem_new {
107	__u64 size;           /* in */
108	__u32 flags;          /* in, mask of ETNA_BO_x */
109	__u32 handle;         /* out */
110};
111
112struct drm_etnaviv_gem_info {
113	__u32 handle;         /* in */
114	__u32 pad;
115	__u64 offset;         /* out, offset to pass to mmap() */
116};
117
118#define ETNA_PREP_READ        0x01
119#define ETNA_PREP_WRITE       0x02
120#define ETNA_PREP_NOSYNC      0x04
121
122struct drm_etnaviv_gem_cpu_prep {
123	__u32 handle;         /* in */
124	__u32 op;             /* in, mask of ETNA_PREP_x */
125	struct drm_etnaviv_timespec timeout;   /* in */
126};
127
128struct drm_etnaviv_gem_cpu_fini {
129	__u32 handle;         /* in */
130	__u32 flags;          /* in, placeholder for now, no defined values */
131};
132
133/*
134 * Cmdstream Submission:
135 */
136
137/* The value written into the cmdstream is logically:
138 * relocbuf->gpuaddr + reloc_offset
139 *
140 * NOTE that reloc's must be sorted by order of increasing submit_offset,
141 * otherwise EINVAL.
142 */
143struct drm_etnaviv_gem_submit_reloc {
144	__u32 submit_offset;  /* in, offset from submit_bo */
145	__u32 reloc_idx;      /* in, index of reloc_bo buffer */
146	__u64 reloc_offset;   /* in, offset from start of reloc_bo */
147	__u32 flags;          /* in, placeholder for now, no defined values */
148};
149
150/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
151 * cmdstream buffer(s) themselves or reloc entries) has one (and only
152 * one) entry in the submit->bos[] table.
153 *
154 * As a optimization, the current buffer (gpu virtual address) can be
155 * passed back through the 'presumed' field.  If on a subsequent reloc,
156 * userspace passes back a 'presumed' address that is still valid,
157 * then patching the cmdstream for this entry is skipped.  This can
158 * avoid kernel needing to map/access the cmdstream bo in the common
159 * case.
160 * If the submit is a softpin submit (ETNA_SUBMIT_SOFTPIN) the 'presumed'
161 * field is interpreted as the fixed location to map the bo into the gpu
162 * virtual address space. If the kernel is unable to map the buffer at
163 * this location the submit will fail. This means userspace is responsible
164 * for the whole gpu virtual address management.
165 */
166#define ETNA_SUBMIT_BO_READ             0x0001
167#define ETNA_SUBMIT_BO_WRITE            0x0002
168struct drm_etnaviv_gem_submit_bo {
169	__u32 flags;          /* in, mask of ETNA_SUBMIT_BO_x */
170	__u32 handle;         /* in, GEM handle */
171	__u64 presumed;       /* in/out, presumed buffer address */
172};
173
174/* performance monitor request (pmr) */
175#define ETNA_PM_PROCESS_PRE             0x0001
176#define ETNA_PM_PROCESS_POST            0x0002
177struct drm_etnaviv_gem_submit_pmr {
178	__u32 flags;          /* in, when to process request (ETNA_PM_PROCESS_x) */
179	__u8  domain;         /* in, pm domain */
180	__u8  pad;
181	__u16 signal;         /* in, pm signal */
182	__u32 sequence;       /* in, sequence number */
183	__u32 read_offset;    /* in, offset from read_bo */
184	__u32 read_idx;       /* in, index of read_bo buffer */
185};
186
187/* Each cmdstream submit consists of a table of buffers involved, and
188 * one or more cmdstream buffers.  This allows for conditional execution
189 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
190 */
191#define ETNA_SUBMIT_NO_IMPLICIT         0x0001
192#define ETNA_SUBMIT_FENCE_FD_IN         0x0002
193#define ETNA_SUBMIT_FENCE_FD_OUT        0x0004
194#define ETNA_SUBMIT_SOFTPIN             0x0008
195#define ETNA_SUBMIT_FLAGS		(ETNA_SUBMIT_NO_IMPLICIT | \
196					 ETNA_SUBMIT_FENCE_FD_IN | \
197					 ETNA_SUBMIT_FENCE_FD_OUT| \
198					 ETNA_SUBMIT_SOFTPIN)
199#define ETNA_PIPE_3D      0x00
200#define ETNA_PIPE_2D      0x01
201#define ETNA_PIPE_VG      0x02
202struct drm_etnaviv_gem_submit {
203	__u32 fence;          /* out */
204	__u32 pipe;           /* in */
205	__u32 exec_state;     /* in, initial execution state (ETNA_PIPE_x) */
206	__u32 nr_bos;         /* in, number of submit_bo's */
207	__u32 nr_relocs;      /* in, number of submit_reloc's */
208	__u32 stream_size;    /* in, cmdstream size */
209	__u64 bos;            /* in, ptr to array of submit_bo's */
210	__u64 relocs;         /* in, ptr to array of submit_reloc's */
211	__u64 stream;         /* in, ptr to cmdstream */
212	__u32 flags;          /* in, mask of ETNA_SUBMIT_x */
213	__s32 fence_fd;       /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
214	__u64 pmrs;           /* in, ptr to array of submit_pmr's */
215	__u32 nr_pmrs;        /* in, number of submit_pmr's */
216	__u32 pad;
217};
218
219/* The normal way to synchronize with the GPU is just to CPU_PREP on
220 * a buffer if you need to access it from the CPU (other cmdstream
221 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
222 * handle the required synchronization under the hood).  This ioctl
223 * mainly just exists as a way to implement the gallium pipe_fence
224 * APIs without requiring a dummy bo to synchronize on.
225 */
226#define ETNA_WAIT_NONBLOCK      0x01
227struct drm_etnaviv_wait_fence {
228	__u32 pipe;           /* in */
229	__u32 fence;          /* in */
230	__u32 flags;          /* in, mask of ETNA_WAIT_x */
231	__u32 pad;
232	struct drm_etnaviv_timespec timeout;   /* in */
233};
234
235#define ETNA_USERPTR_READ	0x01
236#define ETNA_USERPTR_WRITE	0x02
237struct drm_etnaviv_gem_userptr {
238	__u64 user_ptr;	/* in, page aligned user pointer */
239	__u64 user_size;	/* in, page aligned user size */
240	__u32 flags;		/* in, flags */
241	__u32 handle;	/* out, non-zero handle */
242};
243
244struct drm_etnaviv_gem_wait {
245	__u32 pipe;				/* in */
246	__u32 handle;				/* in, bo to be waited for */
247	__u32 flags;				/* in, mask of ETNA_WAIT_x  */
248	__u32 pad;
249	struct drm_etnaviv_timespec timeout;	/* in */
250};
251
252/*
253 * Performance Monitor (PM):
254 */
255
256struct drm_etnaviv_pm_domain {
257	__u32 pipe;       /* in */
258	__u8  iter;       /* in/out, select pm domain at index iter */
259	__u8  id;         /* out, id of domain */
260	__u16 nr_signals; /* out, how many signals does this domain provide */
261	char  name[64];   /* out, name of domain */
262};
263
264struct drm_etnaviv_pm_signal {
265	__u32 pipe;       /* in */
266	__u8  domain;     /* in, pm domain index */
267	__u8  pad;
268	__u16 iter;       /* in/out, select pm source at index iter */
269	__u16 id;         /* out, id of signal */
270	char  name[64];   /* out, name of domain */
271};
272
273#define DRM_ETNAVIV_GET_PARAM          0x00
274/* placeholder:
275#define DRM_ETNAVIV_SET_PARAM          0x01
276 */
277#define DRM_ETNAVIV_GEM_NEW            0x02
278#define DRM_ETNAVIV_GEM_INFO           0x03
279#define DRM_ETNAVIV_GEM_CPU_PREP       0x04
280#define DRM_ETNAVIV_GEM_CPU_FINI       0x05
281#define DRM_ETNAVIV_GEM_SUBMIT         0x06
282#define DRM_ETNAVIV_WAIT_FENCE         0x07
283#define DRM_ETNAVIV_GEM_USERPTR        0x08
284#define DRM_ETNAVIV_GEM_WAIT           0x09
285#define DRM_ETNAVIV_PM_QUERY_DOM       0x0a
286#define DRM_ETNAVIV_PM_QUERY_SIG       0x0b
287#define DRM_ETNAVIV_NUM_IOCTLS         0x0c
288
289#define DRM_IOCTL_ETNAVIV_GET_PARAM    DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
290#define DRM_IOCTL_ETNAVIV_GEM_NEW      DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
291#define DRM_IOCTL_ETNAVIV_GEM_INFO     DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
292#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
293#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
294#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
295#define DRM_IOCTL_ETNAVIV_WAIT_FENCE   DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
296#define DRM_IOCTL_ETNAVIV_GEM_USERPTR  DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
297#define DRM_IOCTL_ETNAVIV_GEM_WAIT     DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
298#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
299#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
300
301#if defined(__cplusplus)
302}
303#endif
304
305#endif /* __ETNAVIV_DRM_H__ */
306