1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/sound/cs42l42.h -- Platform data for CS42L42 ALSA SoC audio driver header 4 * 5 * Copyright 2016-2022 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12#ifndef __CS42L42_H 13#define __CS42L42_H 14 15#define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */ 16#define CS42L42_WIN_START 0x00 17#define CS42L42_WIN_LEN 0x100 18#define CS42L42_RANGE_MIN 0x00 19#define CS42L42_RANGE_MAX 0x7F 20 21#define CS42L42_PAGE_10 0x1000 22#define CS42L42_PAGE_11 0x1100 23#define CS42L42_PAGE_12 0x1200 24#define CS42L42_PAGE_13 0x1300 25#define CS42L42_PAGE_15 0x1500 26#define CS42L42_PAGE_19 0x1900 27#define CS42L42_PAGE_1B 0x1B00 28#define CS42L42_PAGE_1C 0x1C00 29#define CS42L42_PAGE_1D 0x1D00 30#define CS42L42_PAGE_1F 0x1F00 31#define CS42L42_PAGE_20 0x2000 32#define CS42L42_PAGE_21 0x2100 33#define CS42L42_PAGE_23 0x2300 34#define CS42L42_PAGE_24 0x2400 35#define CS42L42_PAGE_25 0x2500 36#define CS42L42_PAGE_26 0x2600 37#define CS42L42_PAGE_27 0x2700 38#define CS42L42_PAGE_28 0x2800 39#define CS42L42_PAGE_29 0x2900 40#define CS42L42_PAGE_2A 0x2A00 41#define CS42L42_PAGE_30 0x3000 42 43#define CS42L42_CHIP_ID 0x42A42 44#define CS42L83_CHIP_ID 0x42A83 45 46/* Page 0x10 Global Registers */ 47#define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01) 48#define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02) 49#define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03) 50#define CS42L42_FABID (CS42L42_PAGE_10 + 0x04) 51#define CS42L42_REVID (CS42L42_PAGE_10 + 0x05) 52#define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06) 53 54#define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07) 55#define CS42L42_SRC_BYPASS_DAC_SHIFT 1 56#define CS42L42_SRC_BYPASS_DAC_MASK (1 << CS42L42_SRC_BYPASS_DAC_SHIFT) 57 58#define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08) 59 60#define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09) 61#define CS42L42_INTERNAL_FS_SHIFT 1 62#define CS42L42_INTERNAL_FS_MASK (1 << CS42L42_INTERNAL_FS_SHIFT) 63 64#define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A) 65#define CS42L42_SLOW_START_ENABLE (CS42L42_PAGE_10 + 0x0B) 66#define CS42L42_SLOW_START_EN_MASK GENMASK(6, 4) 67#define CS42L42_SLOW_START_EN_SHIFT 4 68#define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E) 69#define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F) 70#define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10) 71 72/* Page 0x11 Power and Headset Detect Registers */ 73#define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01) 74#define CS42L42_ASP_DAO_PDN_SHIFT 7 75#define CS42L42_ASP_DAO_PDN_MASK (1 << CS42L42_ASP_DAO_PDN_SHIFT) 76#define CS42L42_ASP_DAI_PDN_SHIFT 6 77#define CS42L42_ASP_DAI_PDN_MASK (1 << CS42L42_ASP_DAI_PDN_SHIFT) 78#define CS42L42_MIXER_PDN_SHIFT 5 79#define CS42L42_MIXER_PDN_MASK (1 << CS42L42_MIXER_PDN_SHIFT) 80#define CS42L42_EQ_PDN_SHIFT 4 81#define CS42L42_EQ_PDN_MASK (1 << CS42L42_EQ_PDN_SHIFT) 82#define CS42L42_HP_PDN_SHIFT 3 83#define CS42L42_HP_PDN_MASK (1 << CS42L42_HP_PDN_SHIFT) 84#define CS42L42_ADC_PDN_SHIFT 2 85#define CS42L42_ADC_PDN_MASK (1 << CS42L42_ADC_PDN_SHIFT) 86#define CS42L42_PDN_ALL_SHIFT 0 87#define CS42L42_PDN_ALL_MASK (1 << CS42L42_PDN_ALL_SHIFT) 88 89#define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02) 90#define CS42L42_ADC_SRC_PDNB_SHIFT 0 91#define CS42L42_ADC_SRC_PDNB_MASK (1 << CS42L42_ADC_SRC_PDNB_SHIFT) 92#define CS42L42_DAC_SRC_PDNB_SHIFT 1 93#define CS42L42_DAC_SRC_PDNB_MASK (1 << CS42L42_DAC_SRC_PDNB_SHIFT) 94#define CS42L42_ASP_DAI1_PDN_SHIFT 2 95#define CS42L42_ASP_DAI1_PDN_MASK (1 << CS42L42_ASP_DAI1_PDN_SHIFT) 96#define CS42L42_SRC_PDN_OVERRIDE_SHIFT 3 97#define CS42L42_SRC_PDN_OVERRIDE_MASK (1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT) 98#define CS42L42_DISCHARGE_FILT_SHIFT 4 99#define CS42L42_DISCHARGE_FILT_MASK (1 << CS42L42_DISCHARGE_FILT_SHIFT) 100 101#define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03) 102#define CS42L42_RING_SENSE_PDNB_SHIFT 1 103#define CS42L42_RING_SENSE_PDNB_MASK (1 << CS42L42_RING_SENSE_PDNB_SHIFT) 104#define CS42L42_VPMON_PDNB_SHIFT 2 105#define CS42L42_VPMON_PDNB_MASK (1 << CS42L42_VPMON_PDNB_SHIFT) 106#define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT 5 107#define CS42L42_SW_CLK_STP_STAT_SEL_MASK (3 << CS42L42_SW_CLK_STP_STAT_SEL_SHIFT) 108 109#define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04) 110#define CS42L42_RS_TRIM_R_SHIFT 0 111#define CS42L42_RS_TRIM_R_MASK (1 << CS42L42_RS_TRIM_R_SHIFT) 112#define CS42L42_RS_TRIM_T_SHIFT 1 113#define CS42L42_RS_TRIM_T_MASK (1 << CS42L42_RS_TRIM_T_SHIFT) 114#define CS42L42_HPREF_RS_SHIFT 2 115#define CS42L42_HPREF_RS_MASK (1 << CS42L42_HPREF_RS_SHIFT) 116#define CS42L42_HSBIAS_FILT_REF_RS_SHIFT 3 117#define CS42L42_HSBIAS_FILT_REF_RS_MASK (1 << CS42L42_HSBIAS_FILT_REF_RS_SHIFT) 118#define CS42L42_RING_SENSE_PU_HIZ_SHIFT 6 119#define CS42L42_RING_SENSE_PU_HIZ_MASK (1 << CS42L42_RING_SENSE_PU_HIZ_SHIFT) 120 121#define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05) 122#define CS42L42_TS_RS_GATE_SHIFT 7 123#define CS42L42_TS_RS_GATE_MAS (1 << CS42L42_TS_RS_GATE_SHIFT) 124 125#define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07) 126#define CS42L42_SCLK_PRESENT_SHIFT 0 127#define CS42L42_SCLK_PRESENT_MASK (1 << CS42L42_SCLK_PRESENT_SHIFT) 128 129#define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09) 130#define CS42L42_OSC_SW_SEL_STAT_SHIFT 0 131#define CS42L42_OSC_SW_SEL_STAT_MASK (3 << CS42L42_OSC_SW_SEL_STAT_SHIFT) 132#define CS42L42_OSC_PDNB_STAT_SHIFT 2 133#define CS42L42_OSC_PDNB_STAT_MASK (1 << CS42L42_OSC_SW_SEL_STAT_SHIFT) 134 135#define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12) 136#define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0 137#define CS42L42_RS_RISE_DBNCE_TIME_MASK (7 << CS42L42_RS_RISE_DBNCE_TIME_SHIFT) 138#define CS42L42_RS_FALL_DBNCE_TIME_SHIFT 3 139#define CS42L42_RS_FALL_DBNCE_TIME_MASK (7 << CS42L42_RS_FALL_DBNCE_TIME_SHIFT) 140#define CS42L42_RS_PU_EN_SHIFT 6 141#define CS42L42_RS_PU_EN_MASK (1 << CS42L42_RS_PU_EN_SHIFT) 142#define CS42L42_RS_INV_SHIFT 7 143#define CS42L42_RS_INV_MASK (1 << CS42L42_RS_INV_SHIFT) 144 145#define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13) 146#define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0 147#define CS42L42_TS_RISE_DBNCE_TIME_MASK (7 << CS42L42_TS_RISE_DBNCE_TIME_SHIFT) 148#define CS42L42_TS_FALL_DBNCE_TIME_SHIFT 3 149#define CS42L42_TS_FALL_DBNCE_TIME_MASK (7 << CS42L42_TS_FALL_DBNCE_TIME_SHIFT) 150#define CS42L42_TS_INV_SHIFT 7 151#define CS42L42_TS_INV_MASK (1 << CS42L42_TS_INV_SHIFT) 152 153#define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14) 154#define CS42L42_D_RS_PLUG_DBNC_SHIFT 0 155#define CS42L42_D_RS_PLUG_DBNC_MASK (1 << CS42L42_D_RS_PLUG_DBNC_SHIFT) 156#define CS42L42_D_RS_UNPLUG_DBNC_SHIFT 1 157#define CS42L42_D_RS_UNPLUG_DBNC_MASK (1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT) 158#define CS42L42_D_TS_PLUG_DBNC_SHIFT 2 159#define CS42L42_D_TS_PLUG_DBNC_MASK (1 << CS42L42_D_TS_PLUG_DBNC_SHIFT) 160#define CS42L42_D_TS_UNPLUG_DBNC_SHIFT 3 161#define CS42L42_D_TS_UNPLUG_DBNC_MASK (1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT) 162 163#define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15) 164#define CS42L42_RS_PLUG_DBNC_SHIFT 0 165#define CS42L42_RS_PLUG_DBNC_MASK (1 << CS42L42_RS_PLUG_DBNC_SHIFT) 166#define CS42L42_RS_UNPLUG_DBNC_SHIFT 1 167#define CS42L42_RS_UNPLUG_DBNC_MASK (1 << CS42L42_RS_UNPLUG_DBNC_SHIFT) 168#define CS42L42_TS_PLUG_DBNC_SHIFT 2 169#define CS42L42_TS_PLUG_DBNC_MASK (1 << CS42L42_TS_PLUG_DBNC_SHIFT) 170#define CS42L42_TS_UNPLUG_DBNC_SHIFT 3 171#define CS42L42_TS_UNPLUG_DBNC_MASK (1 << CS42L42_TS_UNPLUG_DBNC_SHIFT) 172 173#define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F) 174#define CS42L42_HSDET_COMP1_LVL_SHIFT 0 175#define CS42L42_HSDET_COMP1_LVL_MASK (15 << CS42L42_HSDET_COMP1_LVL_SHIFT) 176#define CS42L42_HSDET_COMP2_LVL_SHIFT 4 177#define CS42L42_HSDET_COMP2_LVL_MASK (15 << CS42L42_HSDET_COMP2_LVL_SHIFT) 178 179#define CS42L42_HSDET_COMP1_LVL_VAL 12 /* 1.25V Comparator */ 180#define CS42L42_HSDET_COMP2_LVL_VAL 2 /* 1.75V Comparator */ 181#define CS42L42_HSDET_COMP1_LVL_DEFAULT 7 /* 1V Comparator */ 182#define CS42L42_HSDET_COMP2_LVL_DEFAULT 7 /* 2V Comparator */ 183 184#define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20) 185#define CS42L42_HSDET_AUTO_TIME_SHIFT 0 186#define CS42L42_HSDET_AUTO_TIME_MASK (3 << CS42L42_HSDET_AUTO_TIME_SHIFT) 187#define CS42L42_HSBIAS_REF_SHIFT 3 188#define CS42L42_HSBIAS_REF_MASK (1 << CS42L42_HSBIAS_REF_SHIFT) 189#define CS42L42_HSDET_SET_SHIFT 4 190#define CS42L42_HSDET_SET_MASK (3 << CS42L42_HSDET_SET_SHIFT) 191#define CS42L42_HSDET_CTRL_SHIFT 6 192#define CS42L42_HSDET_CTRL_MASK (3 << CS42L42_HSDET_CTRL_SHIFT) 193 194#define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21) 195#define CS42L42_SW_GNDHS_HS4_SHIFT 0 196#define CS42L42_SW_GNDHS_HS4_MASK (1 << CS42L42_SW_GNDHS_HS4_SHIFT) 197#define CS42L42_SW_GNDHS_HS3_SHIFT 1 198#define CS42L42_SW_GNDHS_HS3_MASK (1 << CS42L42_SW_GNDHS_HS3_SHIFT) 199#define CS42L42_SW_HSB_HS4_SHIFT 2 200#define CS42L42_SW_HSB_HS4_MASK (1 << CS42L42_SW_HSB_HS4_SHIFT) 201#define CS42L42_SW_HSB_HS3_SHIFT 3 202#define CS42L42_SW_HSB_HS3_MASK (1 << CS42L42_SW_HSB_HS3_SHIFT) 203#define CS42L42_SW_HSB_FILT_HS4_SHIFT 4 204#define CS42L42_SW_HSB_FILT_HS4_MASK (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) 205#define CS42L42_SW_HSB_FILT_HS3_SHIFT 5 206#define CS42L42_SW_HSB_FILT_HS3_MASK (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) 207#define CS42L42_SW_REF_HS4_SHIFT 6 208#define CS42L42_SW_REF_HS4_MASK (1 << CS42L42_SW_REF_HS4_SHIFT) 209#define CS42L42_SW_REF_HS3_SHIFT 7 210#define CS42L42_SW_REF_HS3_MASK (1 << CS42L42_SW_REF_HS3_SHIFT) 211 212#define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24) 213#define CS42L42_HSDET_TYPE_SHIFT 0 214#define CS42L42_HSDET_TYPE_MASK (3 << CS42L42_HSDET_TYPE_SHIFT) 215#define CS42L42_HSDET_COMP1_OUT_SHIFT 6 216#define CS42L42_HSDET_COMP1_OUT_MASK (1 << CS42L42_HSDET_COMP1_OUT_SHIFT) 217#define CS42L42_HSDET_COMP2_OUT_SHIFT 7 218#define CS42L42_HSDET_COMP2_OUT_MASK (1 << CS42L42_HSDET_COMP2_OUT_SHIFT) 219#define CS42L42_PLUG_CTIA 0 220#define CS42L42_PLUG_OMTP 1 221#define CS42L42_PLUG_HEADPHONE 2 222#define CS42L42_PLUG_INVALID 3 223 224#define CS42L42_HSDET_SW_COMP1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 225 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 226 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ 227 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ 228 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 229 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 230 (0 << CS42L42_SW_REF_HS4_SHIFT) | \ 231 (1 << CS42L42_SW_REF_HS3_SHIFT)) 232#define CS42L42_HSDET_SW_COMP2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 233 (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 234 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ 235 (1 << CS42L42_SW_HSB_HS3_SHIFT) | \ 236 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 237 (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 238 (1 << CS42L42_SW_REF_HS4_SHIFT) | \ 239 (0 << CS42L42_SW_REF_HS3_SHIFT)) 240#define CS42L42_HSDET_SW_TYPE1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 241 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 242 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ 243 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ 244 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 245 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 246 (0 << CS42L42_SW_REF_HS4_SHIFT) | \ 247 (1 << CS42L42_SW_REF_HS3_SHIFT)) 248#define CS42L42_HSDET_SW_TYPE2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 249 (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 250 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ 251 (1 << CS42L42_SW_HSB_HS3_SHIFT) | \ 252 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 253 (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 254 (1 << CS42L42_SW_REF_HS4_SHIFT) | \ 255 (0 << CS42L42_SW_REF_HS3_SHIFT)) 256#define CS42L42_HSDET_SW_TYPE3 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 257 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 258 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ 259 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ 260 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 261 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 262 (1 << CS42L42_SW_REF_HS4_SHIFT) | \ 263 (1 << CS42L42_SW_REF_HS3_SHIFT)) 264#define CS42L42_HSDET_SW_TYPE4 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ 265 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ 266 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ 267 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ 268 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ 269 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ 270 (0 << CS42L42_SW_REF_HS4_SHIFT) | \ 271 (1 << CS42L42_SW_REF_HS3_SHIFT)) 272 273#define CS42L42_HSDET_COMP_TYPE1 1 274#define CS42L42_HSDET_COMP_TYPE2 2 275#define CS42L42_HSDET_COMP_TYPE3 0 276#define CS42L42_HSDET_COMP_TYPE4 3 277 278#define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29) 279#define CS42L42_HS_CLAMP_DISABLE_SHIFT 0 280#define CS42L42_HS_CLAMP_DISABLE_MASK (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT) 281 282/* Page 0x12 Clocking Registers */ 283#define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01) 284#define CS42L42_MCLKDIV_SHIFT 1 285#define CS42L42_MCLKDIV_MASK (1 << CS42L42_MCLKDIV_SHIFT) 286#define CS42L42_MCLK_SRC_SEL_SHIFT 0 287#define CS42L42_MCLK_SRC_SEL_MASK (1 << CS42L42_MCLK_SRC_SEL_SHIFT) 288 289#define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02) 290#define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03) 291 292#define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04) 293#define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0 294#define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \ 295 CS42L42_FSYNC_PULSE_WIDTH_SHIFT) 296 297#define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05) 298 299#define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06) 300#define CS42L42_FSYNC_PERIOD_SHIFT 0 301#define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT) 302 303#define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07) 304#define CS42L42_ASP_SCLK_EN_SHIFT 5 305#define CS42L42_ASP_SCLK_EN_MASK (1 << CS42L42_ASP_SCLK_EN_SHIFT) 306#define CS42L42_ASP_MASTER_MODE 0x01 307#define CS42L42_ASP_SLAVE_MODE 0x00 308#define CS42L42_ASP_MODE_SHIFT 4 309#define CS42L42_ASP_MODE_MASK (1 << CS42L42_ASP_MODE_SHIFT) 310#define CS42L42_ASP_SCPOL_SHIFT 2 311#define CS42L42_ASP_SCPOL_MASK (3 << CS42L42_ASP_SCPOL_SHIFT) 312#define CS42L42_ASP_SCPOL_NOR 3 313#define CS42L42_ASP_LCPOL_SHIFT 0 314#define CS42L42_ASP_LCPOL_MASK (3 << CS42L42_ASP_LCPOL_SHIFT) 315#define CS42L42_ASP_LCPOL_INV 3 316 317#define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08) 318#define CS42L42_ASP_STP_SHIFT 4 319#define CS42L42_ASP_STP_MASK (1 << CS42L42_ASP_STP_SHIFT) 320#define CS42L42_ASP_5050_SHIFT 3 321#define CS42L42_ASP_5050_MASK (1 << CS42L42_ASP_5050_SHIFT) 322#define CS42L42_ASP_FSD_SHIFT 0 323#define CS42L42_ASP_FSD_MASK (7 << CS42L42_ASP_FSD_SHIFT) 324#define CS42L42_ASP_FSD_0_5 1 325#define CS42L42_ASP_FSD_1_0 2 326#define CS42L42_ASP_FSD_1_5 3 327#define CS42L42_ASP_FSD_2_0 4 328 329#define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09) 330#define CS42L42_FS_EN_SHIFT 0 331#define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT) 332#define CS42L42_FS_EN_IASRC_96K 0x1 333#define CS42L42_FS_EN_OASRC_96K 0x2 334 335#define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A) 336#define CS42L42_CLK_IASRC_SEL_SHIFT 0 337#define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT) 338#define CS42L42_CLK_IASRC_SEL_6 0 339#define CS42L42_CLK_IASRC_SEL_12 1 340 341#define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B) 342#define CS42L42_CLK_OASRC_SEL_SHIFT 0 343#define CS42L42_CLK_OASRC_SEL_MASK (1 << CS42L42_CLK_OASRC_SEL_SHIFT) 344#define CS42L42_CLK_OASRC_SEL_12 1 345 346#define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C) 347#define CS42L42_SCLK_PREDIV_SHIFT 0 348#define CS42L42_SCLK_PREDIV_MASK (3 << CS42L42_SCLK_PREDIV_SHIFT) 349 350/* Page 0x13 Interrupt Registers */ 351/* Interrupts */ 352#define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01) 353#define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02) 354#define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03) 355#define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04) 356#define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05) 357#define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08) 358#define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09) 359#define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A) 360#define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B) 361#define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D) 362#define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E) 363#define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F) 364/* Masks */ 365#define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16) 366#define CS42L42_ADC_OVFL_SHIFT 0 367#define CS42L42_ADC_OVFL_MASK (1 << CS42L42_ADC_OVFL_SHIFT) 368#define CS42L42_ADC_OVFL_VAL_MASK CS42L42_ADC_OVFL_MASK 369 370#define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17) 371#define CS42L42_MIX_CHB_OVFL_SHIFT 0 372#define CS42L42_MIX_CHB_OVFL_MASK (1 << CS42L42_MIX_CHB_OVFL_SHIFT) 373#define CS42L42_MIX_CHA_OVFL_SHIFT 1 374#define CS42L42_MIX_CHA_OVFL_MASK (1 << CS42L42_MIX_CHA_OVFL_SHIFT) 375#define CS42L42_EQ_OVFL_SHIFT 2 376#define CS42L42_EQ_OVFL_MASK (1 << CS42L42_EQ_OVFL_SHIFT) 377#define CS42L42_EQ_BIQUAD_OVFL_SHIFT 3 378#define CS42L42_EQ_BIQUAD_OVFL_MASK (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT) 379#define CS42L42_MIXER_VAL_MASK (CS42L42_MIX_CHB_OVFL_MASK | \ 380 CS42L42_MIX_CHA_OVFL_MASK | \ 381 CS42L42_EQ_OVFL_MASK | \ 382 CS42L42_EQ_BIQUAD_OVFL_MASK) 383 384#define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18) 385#define CS42L42_SRC_ILK_SHIFT 0 386#define CS42L42_SRC_ILK_MASK (1 << CS42L42_SRC_ILK_SHIFT) 387#define CS42L42_SRC_OLK_SHIFT 1 388#define CS42L42_SRC_OLK_MASK (1 << CS42L42_SRC_OLK_SHIFT) 389#define CS42L42_SRC_IUNLK_SHIFT 2 390#define CS42L42_SRC_IUNLK_MASK (1 << CS42L42_SRC_IUNLK_SHIFT) 391#define CS42L42_SRC_OUNLK_SHIFT 3 392#define CS42L42_SRC_OUNLK_MASK (1 << CS42L42_SRC_OUNLK_SHIFT) 393#define CS42L42_SRC_VAL_MASK (CS42L42_SRC_ILK_MASK | \ 394 CS42L42_SRC_OLK_MASK | \ 395 CS42L42_SRC_IUNLK_MASK | \ 396 CS42L42_SRC_OUNLK_MASK) 397 398#define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19) 399#define CS42L42_ASPRX_NOLRCK_SHIFT 0 400#define CS42L42_ASPRX_NOLRCK_MASK (1 << CS42L42_ASPRX_NOLRCK_SHIFT) 401#define CS42L42_ASPRX_EARLY_SHIFT 1 402#define CS42L42_ASPRX_EARLY_MASK (1 << CS42L42_ASPRX_EARLY_SHIFT) 403#define CS42L42_ASPRX_LATE_SHIFT 2 404#define CS42L42_ASPRX_LATE_MASK (1 << CS42L42_ASPRX_LATE_SHIFT) 405#define CS42L42_ASPRX_ERROR_SHIFT 3 406#define CS42L42_ASPRX_ERROR_MASK (1 << CS42L42_ASPRX_ERROR_SHIFT) 407#define CS42L42_ASPRX_OVLD_SHIFT 4 408#define CS42L42_ASPRX_OVLD_MASK (1 << CS42L42_ASPRX_OVLD_SHIFT) 409#define CS42L42_ASP_RX_VAL_MASK (CS42L42_ASPRX_NOLRCK_MASK | \ 410 CS42L42_ASPRX_EARLY_MASK | \ 411 CS42L42_ASPRX_LATE_MASK | \ 412 CS42L42_ASPRX_ERROR_MASK | \ 413 CS42L42_ASPRX_OVLD_MASK) 414 415#define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A) 416#define CS42L42_ASPTX_NOLRCK_SHIFT 0 417#define CS42L42_ASPTX_NOLRCK_MASK (1 << CS42L42_ASPTX_NOLRCK_SHIFT) 418#define CS42L42_ASPTX_EARLY_SHIFT 1 419#define CS42L42_ASPTX_EARLY_MASK (1 << CS42L42_ASPTX_EARLY_SHIFT) 420#define CS42L42_ASPTX_LATE_SHIFT 2 421#define CS42L42_ASPTX_LATE_MASK (1 << CS42L42_ASPTX_LATE_SHIFT) 422#define CS42L42_ASPTX_SMERROR_SHIFT 3 423#define CS42L42_ASPTX_SMERROR_MASK (1 << CS42L42_ASPTX_SMERROR_SHIFT) 424#define CS42L42_ASP_TX_VAL_MASK (CS42L42_ASPTX_NOLRCK_MASK | \ 425 CS42L42_ASPTX_EARLY_MASK | \ 426 CS42L42_ASPTX_LATE_MASK | \ 427 CS42L42_ASPTX_SMERROR_MASK) 428 429#define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B) 430#define CS42L42_PDN_DONE_SHIFT 0 431#define CS42L42_PDN_DONE_MASK (1 << CS42L42_PDN_DONE_SHIFT) 432#define CS42L42_HSDET_AUTO_DONE_SHIFT 1 433#define CS42L42_HSDET_AUTO_DONE_MASK (1 << CS42L42_HSDET_AUTO_DONE_SHIFT) 434#define CS42L42_CODEC_VAL_MASK (CS42L42_PDN_DONE_MASK | \ 435 CS42L42_HSDET_AUTO_DONE_MASK) 436 437#define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C) 438#define CS42L42_SRCPL_ADC_LK_SHIFT 0 439#define CS42L42_SRCPL_ADC_LK_MASK (1 << CS42L42_SRCPL_ADC_LK_SHIFT) 440#define CS42L42_SRCPL_DAC_LK_SHIFT 2 441#define CS42L42_SRCPL_DAC_LK_MASK (1 << CS42L42_SRCPL_DAC_LK_SHIFT) 442#define CS42L42_SRCPL_ADC_UNLK_SHIFT 5 443#define CS42L42_SRCPL_ADC_UNLK_MASK (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) 444#define CS42L42_SRCPL_DAC_UNLK_SHIFT 6 445#define CS42L42_SRCPL_DAC_UNLK_MASK (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT) 446#define CS42L42_SRCPL_VAL_MASK (CS42L42_SRCPL_ADC_LK_MASK | \ 447 CS42L42_SRCPL_DAC_LK_MASK | \ 448 CS42L42_SRCPL_ADC_UNLK_MASK | \ 449 CS42L42_SRCPL_DAC_UNLK_MASK) 450 451#define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E) 452#define CS42L42_VPMON_SHIFT 0 453#define CS42L42_VPMON_MASK (1 << CS42L42_VPMON_SHIFT) 454#define CS42L42_VPMON_VAL_MASK CS42L42_VPMON_MASK 455 456#define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F) 457#define CS42L42_PLL_LOCK_SHIFT 0 458#define CS42L42_PLL_LOCK_MASK (1 << CS42L42_PLL_LOCK_SHIFT) 459#define CS42L42_PLL_LOCK_VAL_MASK CS42L42_PLL_LOCK_MASK 460 461#define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20) 462#define CS42L42_RS_PLUG_SHIFT 0 463#define CS42L42_RS_PLUG_MASK (1 << CS42L42_RS_PLUG_SHIFT) 464#define CS42L42_RS_UNPLUG_SHIFT 1 465#define CS42L42_RS_UNPLUG_MASK (1 << CS42L42_RS_UNPLUG_SHIFT) 466#define CS42L42_TS_PLUG_SHIFT 2 467#define CS42L42_TS_PLUG_MASK (1 << CS42L42_TS_PLUG_SHIFT) 468#define CS42L42_TS_UNPLUG_SHIFT 3 469#define CS42L42_TS_UNPLUG_MASK (1 << CS42L42_TS_UNPLUG_SHIFT) 470#define CS42L42_TSRS_PLUG_VAL_MASK (CS42L42_RS_PLUG_MASK | \ 471 CS42L42_RS_UNPLUG_MASK | \ 472 CS42L42_TS_PLUG_MASK | \ 473 CS42L42_TS_UNPLUG_MASK) 474#define CS42L42_TS_PLUG 3 475#define CS42L42_TS_UNPLUG 0 476#define CS42L42_TS_TRANS 1 477 478/* 479 * NOTE: PLL_START must be 0 while both ADC_PDN=1 and HP_PDN=1. 480 * Otherwise it will prevent FILT+ from charging properly. 481 */ 482#define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01) 483#define CS42L42_PLL_START_SHIFT 0 484#define CS42L42_PLL_START_MASK (1 << CS42L42_PLL_START_SHIFT) 485 486#define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02) 487#define CS42L42_PLL_DIV_FRAC_SHIFT 0 488#define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT) 489 490#define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03) 491#define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04) 492 493#define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05) 494#define CS42L42_PLL_DIV_INT_SHIFT 0 495#define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT) 496 497#define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08) 498#define CS42L42_PLL_DIVOUT_SHIFT 0 499#define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT) 500 501#define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A) 502#define CS42L42_PLL_CAL_RATIO_SHIFT 0 503#define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT) 504 505#define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B) 506#define CS42L42_PLL_MODE_SHIFT 0 507#define CS42L42_PLL_MODE_MASK (3 << CS42L42_PLL_MODE_SHIFT) 508 509/* Page 0x19 HP Load Detect Registers */ 510#define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25) 511#define CS42L42_RLA_STAT_SHIFT 0 512#define CS42L42_RLA_STAT_MASK (3 << CS42L42_RLA_STAT_SHIFT) 513#define CS42L42_RLA_STAT_15_OHM 0 514 515#define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26) 516#define CS42L42_HPLOAD_DET_DONE_SHIFT 0 517#define CS42L42_HPLOAD_DET_DONE_MASK (1 << CS42L42_HPLOAD_DET_DONE_SHIFT) 518 519#define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27) 520#define CS42L42_HP_LD_EN_SHIFT 0 521#define CS42L42_HP_LD_EN_MASK (1 << CS42L42_HP_LD_EN_SHIFT) 522 523/* Page 0x1B Headset Interface Registers */ 524#define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70) 525#define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0 526#define CS42L42_HSBIAS_SENSE_TRIP_MASK (7 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT) 527#define CS42L42_TIP_SENSE_EN_SHIFT 5 528#define CS42L42_TIP_SENSE_EN_MASK (1 << CS42L42_TIP_SENSE_EN_SHIFT) 529#define CS42L42_AUTO_HSBIAS_HIZ_SHIFT 6 530#define CS42L42_AUTO_HSBIAS_HIZ_MASK (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) 531#define CS42L42_HSBIAS_SENSE_EN_SHIFT 7 532#define CS42L42_HSBIAS_SENSE_EN_MASK (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) 533 534#define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71) 535#define CS42L42_WAKEB_CLEAR_SHIFT 0 536#define CS42L42_WAKEB_CLEAR_MASK (1 << CS42L42_WAKEB_CLEAR_SHIFT) 537#define CS42L42_WAKEB_MODE_SHIFT 5 538#define CS42L42_WAKEB_MODE_MASK (1 << CS42L42_WAKEB_MODE_SHIFT) 539#define CS42L42_M_HP_WAKE_SHIFT 6 540#define CS42L42_M_HP_WAKE_MASK (1 << CS42L42_M_HP_WAKE_SHIFT) 541#define CS42L42_M_MIC_WAKE_SHIFT 7 542#define CS42L42_M_MIC_WAKE_MASK (1 << CS42L42_M_MIC_WAKE_SHIFT) 543 544#define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72) 545#define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT 7 546#define CS42L42_ADC_DISABLE_S0_MUTE_MASK (1 << CS42L42_ADC_DISABLE_S0_MUTE_SHIFT) 547 548#define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73) 549#define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0 550#define CS42L42_TIP_SENSE_DEBOUNCE_MASK (3 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT) 551#define CS42L42_TIP_SENSE_INV_SHIFT 5 552#define CS42L42_TIP_SENSE_INV_MASK (1 << CS42L42_TIP_SENSE_INV_SHIFT) 553#define CS42L42_TIP_SENSE_CTRL_SHIFT 6 554#define CS42L42_TIP_SENSE_CTRL_MASK (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) 555 556/* 557 * NOTE: DETECT_MODE must be 0 while both ADC_PDN=1 and HP_PDN=1. 558 * Otherwise it will prevent FILT+ from charging properly. 559 */ 560#define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74) 561#define CS42L42_PDN_MIC_LVL_DET_SHIFT 0 562#define CS42L42_PDN_MIC_LVL_DET_MASK (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT) 563#define CS42L42_HSBIAS_CTL_SHIFT 1 564#define CS42L42_HSBIAS_CTL_MASK (3 << CS42L42_HSBIAS_CTL_SHIFT) 565#define CS42L42_DETECT_MODE_SHIFT 3 566#define CS42L42_DETECT_MODE_MASK (3 << CS42L42_DETECT_MODE_SHIFT) 567 568#define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75) 569#define CS42L42_HS_DET_LEVEL_SHIFT 0 570#define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT) 571#define CS42L42_EVENT_STAT_SEL_SHIFT 6 572#define CS42L42_EVENT_STAT_SEL_MASK (1 << CS42L42_EVENT_STAT_SEL_SHIFT) 573#define CS42L42_LATCH_TO_VP_SHIFT 7 574#define CS42L42_LATCH_TO_VP_MASK (1 << CS42L42_LATCH_TO_VP_SHIFT) 575 576#define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76) 577#define CS42L42_DEBOUNCE_TIME_SHIFT 5 578#define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT) 579 580#define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77) 581#define CS42L42_HSBIAS_HIZ_MODE_SHIFT 6 582#define CS42L42_HSBIAS_HIZ_MODE_MASK (1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT) 583#define CS42L42_TIP_SENSE_SHIFT 7 584#define CS42L42_TIP_SENSE_MASK (1 << CS42L42_TIP_SENSE_SHIFT) 585 586#define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78) 587#define CS42L42_SHORT_TRUE_SHIFT 0 588#define CS42L42_SHORT_TRUE_MASK (1 << CS42L42_SHORT_TRUE_SHIFT) 589#define CS42L42_HS_TRUE_SHIFT 1 590#define CS42L42_HS_TRUE_MASK (1 << CS42L42_HS_TRUE_SHIFT) 591 592#define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79) 593#define CS42L42_TIP_SENSE_UNPLUG_SHIFT 5 594#define CS42L42_TIP_SENSE_UNPLUG_MASK (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) 595#define CS42L42_TIP_SENSE_PLUG_SHIFT 6 596#define CS42L42_TIP_SENSE_PLUG_MASK (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) 597#define CS42L42_HSBIAS_SENSE_SHIFT 7 598#define CS42L42_HSBIAS_SENSE_MASK (1 << CS42L42_HSBIAS_SENSE_SHIFT) 599#define CS42L42_DET_INT_VAL1_MASK (CS42L42_TIP_SENSE_UNPLUG_MASK | \ 600 CS42L42_TIP_SENSE_PLUG_MASK | \ 601 CS42L42_HSBIAS_SENSE_MASK) 602 603#define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A) 604#define CS42L42_M_SHORT_DET_SHIFT 0 605#define CS42L42_M_SHORT_DET_MASK (1 << CS42L42_M_SHORT_DET_SHIFT) 606#define CS42L42_M_SHORT_RLS_SHIFT 1 607#define CS42L42_M_SHORT_RLS_MASK (1 << CS42L42_M_SHORT_RLS_SHIFT) 608#define CS42L42_M_HSBIAS_HIZ_SHIFT 2 609#define CS42L42_M_HSBIAS_HIZ_MASK (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) 610#define CS42L42_M_DETECT_FT_SHIFT 6 611#define CS42L42_M_DETECT_FT_MASK (1 << CS42L42_M_DETECT_FT_SHIFT) 612#define CS42L42_M_DETECT_TF_SHIFT 7 613#define CS42L42_M_DETECT_TF_MASK (1 << CS42L42_M_DETECT_TF_SHIFT) 614#define CS42L42_DET_INT_VAL2_MASK (CS42L42_M_SHORT_DET_MASK | \ 615 CS42L42_M_SHORT_RLS_MASK | \ 616 CS42L42_M_HSBIAS_HIZ_MASK | \ 617 CS42L42_M_DETECT_FT_MASK | \ 618 CS42L42_M_DETECT_TF_MASK) 619 620/* Page 0x1C Headset Bias Registers */ 621#define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03) 622#define CS42L42_HSBIAS_RAMP_SHIFT 0 623#define CS42L42_HSBIAS_RAMP_MASK (3 << CS42L42_HSBIAS_RAMP_SHIFT) 624#define CS42L42_HSBIAS_PD_SHIFT 4 625#define CS42L42_HSBIAS_PD_MASK (1 << CS42L42_HSBIAS_PD_SHIFT) 626#define CS42L42_HSBIAS_CAPLESS_SHIFT 7 627#define CS42L42_HSBIAS_CAPLESS_MASK (1 << CS42L42_HSBIAS_CAPLESS_SHIFT) 628 629/* Page 0x1D ADC Registers */ 630#define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01) 631#define CS42L42_ADC_NOTCH_DIS_SHIFT 5 632#define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT 4 633#define CS42L42_ADC_INV_SHIFT 2 634#define CS42L42_ADC_DIG_BOOST_SHIFT 0 635 636#define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03) 637#define CS42L42_ADC_VOL_SHIFT 0 638 639#define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04) 640#define CS42L42_ADC_WNF_CF_SHIFT 4 641#define CS42L42_ADC_WNF_EN_SHIFT 3 642#define CS42L42_ADC_HPF_CF_SHIFT 1 643#define CS42L42_ADC_HPF_EN_SHIFT 0 644 645/* Page 0x1F DAC Registers */ 646#define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01) 647#define CS42L42_DACB_INV_SHIFT 1 648#define CS42L42_DACA_INV_SHIFT 0 649 650#define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06) 651#define CS42L42_HPOUT_PULLDOWN_SHIFT 4 652#define CS42L42_HPOUT_PULLDOWN_MASK (15 << CS42L42_HPOUT_PULLDOWN_SHIFT) 653#define CS42L42_HPOUT_LOAD_SHIFT 3 654#define CS42L42_HPOUT_LOAD_MASK (1 << CS42L42_HPOUT_LOAD_SHIFT) 655#define CS42L42_HPOUT_CLAMP_SHIFT 2 656#define CS42L42_HPOUT_CLAMP_MASK (1 << CS42L42_HPOUT_CLAMP_SHIFT) 657#define CS42L42_DAC_HPF_EN_SHIFT 1 658#define CS42L42_DAC_HPF_EN_MASK (1 << CS42L42_DAC_HPF_EN_SHIFT) 659#define CS42L42_DAC_MON_EN_SHIFT 0 660#define CS42L42_DAC_MON_EN_MASK (1 << CS42L42_DAC_MON_EN_SHIFT) 661 662/* Page 0x20 HP CTL Registers */ 663#define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01) 664#define CS42L42_HP_ANA_BMUTE_SHIFT 3 665#define CS42L42_HP_ANA_BMUTE_MASK (1 << CS42L42_HP_ANA_BMUTE_SHIFT) 666#define CS42L42_HP_ANA_AMUTE_SHIFT 2 667#define CS42L42_HP_ANA_AMUTE_MASK (1 << CS42L42_HP_ANA_AMUTE_SHIFT) 668#define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1 669#define CS42L42_HP_FULL_SCALE_VOL_MASK (1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT) 670 671/* Page 0x21 Class H Registers */ 672#define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01) 673 674/* Page 0x23 Mixer Volume Registers */ 675#define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01) 676#define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02) 677 678#define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03) 679#define CS42L42_MIXER_CH_VOL_SHIFT 0 680#define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT) 681 682/* Page 0x24 EQ Registers */ 683#define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01) 684#define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02) 685#define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03) 686#define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04) 687#define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06) 688#define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07) 689#define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08) 690#define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09) 691#define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A) 692#define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B) 693#define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C) 694#define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E) 695 696/* Page 0x25 Audio Port Registers */ 697#define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01) 698#define CS42L42_SP_RX_CHB_SEL_SHIFT 2 699#define CS42L42_SP_RX_CHB_SEL_MASK (3 << CS42L42_SP_RX_CHB_SEL_SHIFT) 700 701#define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02) 702#define CS42L42_SP_RX_RSYNC_SHIFT 6 703#define CS42L42_SP_RX_RSYNC_MASK (1 << CS42L42_SP_RX_RSYNC_SHIFT) 704#define CS42L42_SP_RX_NSB_POS_SHIFT 3 705#define CS42L42_SP_RX_NSB_POS_MASK (7 << CS42L42_SP_RX_NSB_POS_SHIFT) 706#define CS42L42_SP_RX_NFS_NSBB_SHIFT 2 707#define CS42L42_SP_RX_NFS_NSBB_MASK (1 << CS42L42_SP_RX_NFS_NSBB_SHIFT) 708#define CS42L42_SP_RX_ISOC_MODE_SHIFT 0 709#define CS42L42_SP_RX_ISOC_MODE_MASK (3 << CS42L42_SP_RX_ISOC_MODE_SHIFT) 710 711#define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03) 712#define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04) 713#define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05) 714#define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06) 715#define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07) 716 717/* Page 0x26 SRC Registers */ 718#define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01) 719#define CS42L42_SRC_SDIN_FS_SHIFT 0 720#define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT) 721 722#define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09) 723 724/* Page 0x27 DMA */ 725#define CS42L42_SOFT_RESET_REBOOT (CS42L42_PAGE_27 + 0x01) 726#define CS42L42_SFT_RST_REBOOT_MASK BIT(1) 727 728/* Page 0x28 S/PDIF Registers */ 729#define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01) 730#define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02) 731#define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03) 732#define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04) 733 734/* Page 0x29 Serial Port TX Registers */ 735#define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01) 736#define CS42L42_ASP_TX_EN_SHIFT 0 737#define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02) 738#define CS42L42_ASP_TX0_CH2_SHIFT 1 739#define CS42L42_ASP_TX0_CH1_SHIFT 0 740 741#define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03) 742#define CS42L42_ASP_TX_CH1_AP_SHIFT 7 743#define CS42L42_ASP_TX_CH1_AP_MASK (1 << CS42L42_ASP_TX_CH1_AP_SHIFT) 744#define CS42L42_ASP_TX_CH2_AP_SHIFT 6 745#define CS42L42_ASP_TX_CH2_AP_MASK (1 << CS42L42_ASP_TX_CH2_AP_SHIFT) 746#define CS42L42_ASP_TX_CH2_RES_SHIFT 2 747#define CS42L42_ASP_TX_CH2_RES_MASK (3 << CS42L42_ASP_TX_CH2_RES_SHIFT) 748#define CS42L42_ASP_TX_CH1_RES_SHIFT 0 749#define CS42L42_ASP_TX_CH1_RES_MASK (3 << CS42L42_ASP_TX_CH1_RES_SHIFT) 750#define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04) 751#define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05) 752#define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06) 753#define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A) 754#define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B) 755 756/* Page 0x2A Serial Port RX Registers */ 757#define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01) 758#define CS42L42_ASP_RX0_CH_EN_SHIFT 2 759#define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT) 760#define CS42L42_ASP_RX0_CH1_SHIFT 2 761#define CS42L42_ASP_RX0_CH2_SHIFT 3 762#define CS42L42_ASP_RX0_CH3_SHIFT 4 763#define CS42L42_ASP_RX0_CH4_SHIFT 5 764 765#define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02) 766#define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03) 767#define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04) 768#define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05) 769#define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06) 770#define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07) 771#define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08) 772#define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09) 773#define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A) 774#define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B) 775#define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C) 776#define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D) 777#define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E) 778#define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F) 779#define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10) 780#define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11) 781#define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12) 782#define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13) 783 784#define CS42L42_ASP_RX_CH_AP_SHIFT 6 785#define CS42L42_ASP_RX_CH_AP_MASK (1 << CS42L42_ASP_RX_CH_AP_SHIFT) 786#define CS42L42_ASP_RX_CH_AP_LOW 0 787#define CS42L42_ASP_RX_CH_AP_HI 1 788#define CS42L42_ASP_RX_CH_RES_SHIFT 0 789#define CS42L42_ASP_RX_CH_RES_MASK (3 << CS42L42_ASP_RX_CH_RES_SHIFT) 790#define CS42L42_ASP_RX_CH_RES_32 3 791#define CS42L42_ASP_RX_CH_RES_16 1 792#define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0 793#define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT) 794 795/* Page 0x30 ID Registers */ 796#define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14) 797#define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14) 798 799/* Defines for fracturing values spread across multiple registers */ 800#define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff) 801#define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8) 802#define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16) 803 804#define CS42L42_NUM_SUPPLIES 5 805#define CS42L42_BOOT_TIME_US 3000 806#define CS42L42_PLL_DIVOUT_TIME_US 800 807#define CS42L42_CLOCK_SWITCH_DELAY_US 150 808#define CS42L42_PLL_LOCK_POLL_US 250 809#define CS42L42_PLL_LOCK_TIMEOUT_US 1250 810#define CS42L42_HP_ADC_EN_TIME_US 20000 811#define CS42L42_PDN_DONE_POLL_US 1000 812#define CS42L42_PDN_DONE_TIMEOUT_US 235000 813#define CS42L42_PDN_DONE_TIME_MS 65 814 815#endif /* __CS42L42_H */ 816