1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2/* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 8#ifndef _MSCC_OCELOT_HSIO_H_ 9#define _MSCC_OCELOT_HSIO_H_ 10 11#define HSIO_PLL5G_CFG0 0x0000 12#define HSIO_PLL5G_CFG1 0x0004 13#define HSIO_PLL5G_CFG2 0x0008 14#define HSIO_PLL5G_CFG3 0x000c 15#define HSIO_PLL5G_CFG4 0x0010 16#define HSIO_PLL5G_CFG5 0x0014 17#define HSIO_PLL5G_CFG6 0x0018 18#define HSIO_PLL5G_STATUS0 0x001c 19#define HSIO_PLL5G_STATUS1 0x0020 20#define HSIO_PLL5G_BIST_CFG0 0x0024 21#define HSIO_PLL5G_BIST_CFG1 0x0028 22#define HSIO_PLL5G_BIST_CFG2 0x002c 23#define HSIO_PLL5G_BIST_STAT0 0x0030 24#define HSIO_PLL5G_BIST_STAT1 0x0034 25#define HSIO_RCOMP_CFG0 0x0038 26#define HSIO_RCOMP_STATUS 0x003c 27#define HSIO_SYNC_ETH_CFG 0x0040 28#define HSIO_SYNC_ETH_PLL_CFG 0x0048 29#define HSIO_S1G_DES_CFG 0x004c 30#define HSIO_S1G_IB_CFG 0x0050 31#define HSIO_S1G_OB_CFG 0x0054 32#define HSIO_S1G_SER_CFG 0x0058 33#define HSIO_S1G_COMMON_CFG 0x005c 34#define HSIO_S1G_PLL_CFG 0x0060 35#define HSIO_S1G_PLL_STATUS 0x0064 36#define HSIO_S1G_DFT_CFG0 0x0068 37#define HSIO_S1G_DFT_CFG1 0x006c 38#define HSIO_S1G_DFT_CFG2 0x0070 39#define HSIO_S1G_TP_CFG 0x0074 40#define HSIO_S1G_RC_PLL_BIST_CFG 0x0078 41#define HSIO_S1G_MISC_CFG 0x007c 42#define HSIO_S1G_DFT_STATUS 0x0080 43#define HSIO_S1G_MISC_STATUS 0x0084 44#define HSIO_MCB_S1G_ADDR_CFG 0x0088 45#define HSIO_S6G_DIG_CFG 0x008c 46#define HSIO_S6G_DFT_CFG0 0x0090 47#define HSIO_S6G_DFT_CFG1 0x0094 48#define HSIO_S6G_DFT_CFG2 0x0098 49#define HSIO_S6G_TP_CFG0 0x009c 50#define HSIO_S6G_TP_CFG1 0x00a0 51#define HSIO_S6G_RC_PLL_BIST_CFG 0x00a4 52#define HSIO_S6G_MISC_CFG 0x00a8 53#define HSIO_S6G_OB_ANEG_CFG 0x00ac 54#define HSIO_S6G_DFT_STATUS 0x00b0 55#define HSIO_S6G_ERR_CNT 0x00b4 56#define HSIO_S6G_MISC_STATUS 0x00b8 57#define HSIO_S6G_DES_CFG 0x00bc 58#define HSIO_S6G_IB_CFG 0x00c0 59#define HSIO_S6G_IB_CFG1 0x00c4 60#define HSIO_S6G_IB_CFG2 0x00c8 61#define HSIO_S6G_IB_CFG3 0x00cc 62#define HSIO_S6G_IB_CFG4 0x00d0 63#define HSIO_S6G_IB_CFG5 0x00d4 64#define HSIO_S6G_OB_CFG 0x00d8 65#define HSIO_S6G_OB_CFG1 0x00dc 66#define HSIO_S6G_SER_CFG 0x00e0 67#define HSIO_S6G_COMMON_CFG 0x00e4 68#define HSIO_S6G_PLL_CFG 0x00e8 69#define HSIO_S6G_ACJTAG_CFG 0x00ec 70#define HSIO_S6G_GP_CFG 0x00f0 71#define HSIO_S6G_IB_STATUS0 0x00f4 72#define HSIO_S6G_IB_STATUS1 0x00f8 73#define HSIO_S6G_ACJTAG_STATUS 0x00fc 74#define HSIO_S6G_PLL_STATUS 0x0100 75#define HSIO_S6G_REVID 0x0104 76#define HSIO_MCB_S6G_ADDR_CFG 0x0108 77#define HSIO_HW_CFG 0x010c 78#define HSIO_HW_QSGMII_CFG 0x0110 79#define HSIO_HW_QSGMII_STAT 0x0114 80#define HSIO_CLK_CFG 0x0118 81#define HSIO_TEMP_SENSOR_CTRL 0x011c 82#define HSIO_TEMP_SENSOR_CFG 0x0120 83#define HSIO_TEMP_SENSOR_STAT 0x0124 84 85#define HSIO_PLL5G_CFG0_ENA_ROT BIT(31) 86#define HSIO_PLL5G_CFG0_ENA_LANE BIT(30) 87#define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29) 88#define HSIO_PLL5G_CFG0_DIV4 BIT(28) 89#define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27) 90#define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23)) 91#define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23) 92#define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23) 93#define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18)) 94#define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18) 95#define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18) 96#define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16)) 97#define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16) 98#define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16) 99#define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15) 100#define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14) 101#define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13) 102#define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12) 103#define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6)) 104#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6) 105#define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6) 106#define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) 107#define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0) 108 109#define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18) 110#define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17) 111#define HSIO_PLL5G_CFG1_ROT_DIR BIT(16) 112#define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15) 113#define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14) 114#define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) 115#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6) 116#define HSIO_PLL5G_CFG1_RC_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6) 117#define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5) 118#define HSIO_PLL5G_CFG1_PWD_TX BIT(4) 119#define HSIO_PLL5G_CFG1_PWD_RX BIT(3) 120#define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2) 121#define HSIO_PLL5G_CFG1_HALF_RATE BIT(1) 122#define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0) 123 124#define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30) 125#define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29) 126#define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28) 127#define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27) 128#define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26) 129#define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25) 130#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24) 131#define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16)) 132#define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16) 133#define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16) 134#define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15) 135#define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14) 136#define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13) 137#define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12) 138#define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11) 139#define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10) 140#define HSIO_PLL5G_CFG2_GAIN_TEST(x) (((x) << 5) & GENMASK(9, 5)) 141#define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5) 142#define HSIO_PLL5G_CFG2_GAIN_TEST_X(x) (((x) & GENMASK(9, 5)) >> 5) 143#define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4) 144#define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3) 145#define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2) 146#define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1) 147#define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0) 148 149#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22)) 150#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22) 151#define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22) 152#define HSIO_PLL5G_CFG3_TESTOUT_SEL(x) (((x) << 19) & GENMASK(21, 19)) 153#define HSIO_PLL5G_CFG3_TESTOUT_SEL_M GENMASK(21, 19) 154#define HSIO_PLL5G_CFG3_TESTOUT_SEL_X(x) (((x) & GENMASK(21, 19)) >> 19) 155#define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18) 156#define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17) 157#define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16) 158#define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15) 159#define HSIO_PLL5G_CFG3_RST_FB_N BIT(14) 160#define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13) 161#define HSIO_PLL5G_CFG3_FORCE_LO BIT(12) 162#define HSIO_PLL5G_CFG3_FORCE_HI BIT(11) 163#define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10) 164#define HSIO_PLL5G_CFG3_FORCE_CP BIT(9) 165#define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8) 166#define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0)) 167#define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0) 168 169#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16)) 170#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16) 171#define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16) 172#define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0)) 173#define HSIO_PLL5G_CFG4_IB_CTRL_M GENMASK(15, 0) 174 175#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16)) 176#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16) 177#define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16) 178#define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0)) 179#define HSIO_PLL5G_CFG5_OB_CTRL_M GENMASK(15, 0) 180 181#define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23) 182#define HSIO_PLL5G_CFG6_REFCLK_SEL(x) (((x) << 20) & GENMASK(22, 20)) 183#define HSIO_PLL5G_CFG6_REFCLK_SEL_M GENMASK(22, 20) 184#define HSIO_PLL5G_CFG6_REFCLK_SEL_X(x) (((x) & GENMASK(22, 20)) >> 20) 185#define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19) 186#define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16)) 187#define HSIO_PLL5G_CFG6_POR_DEL_SEL_M GENMASK(17, 16) 188#define HSIO_PLL5G_CFG6_POR_DEL_SEL_X(x) (((x) & GENMASK(17, 16)) >> 16) 189#define HSIO_PLL5G_CFG6_DIV125REF_SEL(x) (((x) << 8) & GENMASK(15, 8)) 190#define HSIO_PLL5G_CFG6_DIV125REF_SEL_M GENMASK(15, 8) 191#define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x) (((x) & GENMASK(15, 8)) >> 8) 192#define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7) 193#define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6) 194#define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0)) 195#define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0) 196 197#define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12) 198#define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11) 199#define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10) 200#define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9) 201#define HSIO_PLL5G_STATUS0_READBACK_DATA(x) (((x) << 1) & GENMASK(8, 1)) 202#define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1) 203#define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x) (((x) & GENMASK(8, 1)) >> 1) 204#define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0) 205 206#define HSIO_PLL5G_STATUS1_SIG_DEL(x) (((x) << 21) & GENMASK(28, 21)) 207#define HSIO_PLL5G_STATUS1_SIG_DEL_M GENMASK(28, 21) 208#define HSIO_PLL5G_STATUS1_SIG_DEL_X(x) (((x) & GENMASK(28, 21)) >> 21) 209#define HSIO_PLL5G_STATUS1_GAIN_STAT(x) (((x) << 16) & GENMASK(20, 16)) 210#define HSIO_PLL5G_STATUS1_GAIN_STAT_M GENMASK(20, 16) 211#define HSIO_PLL5G_STATUS1_GAIN_STAT_X(x) (((x) & GENMASK(20, 16)) >> 16) 212#define HSIO_PLL5G_STATUS1_FBCNT_DIF(x) (((x) << 4) & GENMASK(13, 4)) 213#define HSIO_PLL5G_STATUS1_FBCNT_DIF_M GENMASK(13, 4) 214#define HSIO_PLL5G_STATUS1_FBCNT_DIF_X(x) (((x) & GENMASK(13, 4)) >> 4) 215#define HSIO_PLL5G_STATUS1_FSM_STAT(x) (((x) << 1) & GENMASK(3, 1)) 216#define HSIO_PLL5G_STATUS1_FSM_STAT_M GENMASK(3, 1) 217#define HSIO_PLL5G_STATUS1_FSM_STAT_X(x) (((x) & GENMASK(3, 1)) >> 1) 218#define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0) 219 220#define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31) 221#define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30) 222#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20)) 223#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20) 224#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20) 225#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT(x) (((x) << 16) & GENMASK(19, 16)) 226#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M GENMASK(19, 16) 227#define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X(x) (((x) & GENMASK(19, 16)) >> 16) 228#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0)) 229#define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M GENMASK(15, 0) 230 231#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT(x) (((x) << 4) & GENMASK(7, 4)) 232#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M GENMASK(7, 4) 233#define HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X(x) (((x) & GENMASK(7, 4)) >> 4) 234#define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2) 235#define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1) 236#define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0) 237 238#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT(x) (((x) << 16) & GENMASK(31, 16)) 239#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M GENMASK(31, 16) 240#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X(x) (((x) & GENMASK(31, 16)) >> 16) 241#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF(x) ((x) & GENMASK(15, 0)) 242#define HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M GENMASK(15, 0) 243 244#define HSIO_RCOMP_CFG0_PWD_ENA BIT(13) 245#define HSIO_RCOMP_CFG0_RUN_CAL BIT(12) 246#define HSIO_RCOMP_CFG0_SPEED_SEL(x) (((x) << 10) & GENMASK(11, 10)) 247#define HSIO_RCOMP_CFG0_SPEED_SEL_M GENMASK(11, 10) 248#define HSIO_RCOMP_CFG0_SPEED_SEL_X(x) (((x) & GENMASK(11, 10)) >> 10) 249#define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8)) 250#define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8) 251#define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8) 252#define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4) 253#define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0)) 254#define HSIO_RCOMP_CFG0_RCOMP_VAL_M GENMASK(3, 0) 255 256#define HSIO_RCOMP_STATUS_BUSY BIT(12) 257#define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7) 258#define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0)) 259#define HSIO_RCOMP_STATUS_RCOMP_M GENMASK(3, 0) 260 261#define HSIO_SYNC_ETH_CFG_RSZ 0x4 262 263#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC(x) (((x) << 4) & GENMASK(7, 4)) 264#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M GENMASK(7, 4) 265#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X(x) (((x) & GENMASK(7, 4)) >> 4) 266#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV(x) (((x) << 1) & GENMASK(3, 1)) 267#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M GENMASK(3, 1) 268#define HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X(x) (((x) & GENMASK(3, 1)) >> 1) 269#define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0) 270 271#define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0) 272 273#define HSIO_S1G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13)) 274#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13) 275#define HSIO_S1G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) 276#define HSIO_S1G_DES_CFG_DES_CPMD_SEL(x) (((x) << 11) & GENMASK(12, 11)) 277#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_M GENMASK(12, 11) 278#define HSIO_S1G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(12, 11)) >> 11) 279#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 8) & GENMASK(10, 8)) 280#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M GENMASK(10, 8) 281#define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(10, 8)) >> 8) 282#define HSIO_S1G_DES_CFG_DES_BW_ANA(x) (((x) << 5) & GENMASK(7, 5)) 283#define HSIO_S1G_DES_CFG_DES_BW_ANA_M GENMASK(7, 5) 284#define HSIO_S1G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(7, 5)) >> 5) 285#define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4) 286#define HSIO_S1G_DES_CFG_DES_BW_HYST(x) (((x) << 1) & GENMASK(3, 1)) 287#define HSIO_S1G_DES_CFG_DES_BW_HYST_M GENMASK(3, 1) 288#define HSIO_S1G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(3, 1)) >> 1) 289#define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0) 290 291#define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27) 292#define HSIO_S1G_IB_CFG_ACJTAG_HYST(x) (((x) << 24) & GENMASK(26, 24)) 293#define HSIO_S1G_IB_CFG_ACJTAG_HYST_M GENMASK(26, 24) 294#define HSIO_S1G_IB_CFG_ACJTAG_HYST_X(x) (((x) & GENMASK(26, 24)) >> 24) 295#define HSIO_S1G_IB_CFG_IB_DET_LEV(x) (((x) << 19) & GENMASK(21, 19)) 296#define HSIO_S1G_IB_CFG_IB_DET_LEV_M GENMASK(21, 19) 297#define HSIO_S1G_IB_CFG_IB_DET_LEV_X(x) (((x) & GENMASK(21, 19)) >> 19) 298#define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14) 299#define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13) 300#define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12) 301#define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11) 302#define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10) 303#define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9) 304#define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x) (((x) << 6) & GENMASK(8, 6)) 305#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M GENMASK(8, 6) 306#define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x) (((x) & GENMASK(8, 6)) >> 6) 307#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ(x) (((x) << 4) & GENMASK(5, 4)) 308#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M GENMASK(5, 4) 309#define HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X(x) (((x) & GENMASK(5, 4)) >> 4) 310#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) 311#define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M GENMASK(3, 0) 312 313#define HSIO_S1G_OB_CFG_OB_SLP(x) (((x) << 17) & GENMASK(18, 17)) 314#define HSIO_S1G_OB_CFG_OB_SLP_M GENMASK(18, 17) 315#define HSIO_S1G_OB_CFG_OB_SLP_X(x) (((x) & GENMASK(18, 17)) >> 17) 316#define HSIO_S1G_OB_CFG_OB_AMP_CTRL(x) (((x) << 13) & GENMASK(16, 13)) 317#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_M GENMASK(16, 13) 318#define HSIO_S1G_OB_CFG_OB_AMP_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) 319#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL(x) (((x) << 10) & GENMASK(12, 10)) 320#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M GENMASK(12, 10) 321#define HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10) 322#define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9) 323#define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8) 324#define HSIO_S1G_OB_CFG_OB_VCM_CTRL(x) (((x) << 4) & GENMASK(7, 4)) 325#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_M GENMASK(7, 4) 326#define HSIO_S1G_OB_CFG_OB_VCM_CTRL_X(x) (((x) & GENMASK(7, 4)) >> 4) 327#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) 328#define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0) 329 330#define HSIO_S1G_SER_CFG_SER_IDLE BIT(9) 331#define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8) 332#define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7) 333#define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6) 334#define HSIO_S1G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4)) 335#define HSIO_S1G_SER_CFG_SER_ALISEL_M GENMASK(5, 4) 336#define HSIO_S1G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4) 337#define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3) 338#define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2) 339#define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1) 340#define HSIO_S1G_SER_CFG_SER_ENALI BIT(0) 341 342#define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31) 343#define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21) 344#define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18) 345#define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17) 346#define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16) 347#define HSIO_S1G_COMMON_CFG_LANE_CTRL(x) (((x) << 13) & GENMASK(15, 13)) 348#define HSIO_S1G_COMMON_CFG_LANE_CTRL_M GENMASK(15, 13) 349#define HSIO_S1G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(15, 13)) >> 13) 350#define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12) 351#define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11) 352#define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10) 353#define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9) 354#define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8) 355#define HSIO_S1G_COMMON_CFG_HRATE BIT(7) 356#define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0) 357 358#define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22) 359#define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21) 360#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 8) & GENMASK(15, 8)) 361#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(15, 8) 362#define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(15, 8)) >> 8) 363#define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7) 364#define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6) 365#define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5) 366#define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3) 367 368#define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12) 369#define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11) 370#define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10) 371#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0)) 372#define HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0) 373 374#define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31) 375#define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23) 376#define HSIO_S1G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20)) 377#define HSIO_S1G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20) 378#define HSIO_S1G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20) 379#define HSIO_S1G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16)) 380#define HSIO_S1G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16) 381#define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16) 382#define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4) 383#define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3) 384#define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2) 385#define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0) 386 387#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) 388#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8) 389#define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) 390#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) 391#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4) 392#define HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) 393#define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3) 394#define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2) 395#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1) 396#define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0) 397 398#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) 399#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8) 400#define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) 401#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) 402#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4) 403#define HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) 404#define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3) 405#define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2) 406#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1) 407#define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0) 408 409#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20) 410#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(17, 16)) 411#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(17, 16) 412#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(17, 16)) >> 16) 413#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8)) 414#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8) 415#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8) 416#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0)) 417#define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0) 418 419#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11)) 420#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11) 421#define HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11) 422#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10) 423#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9) 424#define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8) 425#define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5) 426#define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4) 427#define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3) 428#define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2) 429#define HSIO_S1G_MISC_CFG_LANE_RST BIT(0) 430 431#define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7) 432#define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6) 433#define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5) 434#define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3) 435#define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2) 436#define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1) 437#define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0) 438 439#define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0) 440 441#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31) 442#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30) 443#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0)) 444#define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0) 445 446#define HSIO_S6G_DIG_CFG_GP(x) (((x) << 16) & GENMASK(18, 16)) 447#define HSIO_S6G_DIG_CFG_GP_M GENMASK(18, 16) 448#define HSIO_S6G_DIG_CFG_GP_X(x) (((x) & GENMASK(18, 16)) >> 16) 449#define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7) 450#define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6) 451#define HSIO_S6G_DIG_CFG_SIGDET_AST(x) (((x) << 3) & GENMASK(5, 3)) 452#define HSIO_S6G_DIG_CFG_SIGDET_AST_M GENMASK(5, 3) 453#define HSIO_S6G_DIG_CFG_SIGDET_AST_X(x) (((x) & GENMASK(5, 3)) >> 3) 454#define HSIO_S6G_DIG_CFG_SIGDET_DST(x) ((x) & GENMASK(2, 0)) 455#define HSIO_S6G_DIG_CFG_SIGDET_DST_M GENMASK(2, 0) 456 457#define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31) 458#define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23) 459#define HSIO_S6G_DFT_CFG0_PRBS_SEL(x) (((x) << 20) & GENMASK(21, 20)) 460#define HSIO_S6G_DFT_CFG0_PRBS_SEL_M GENMASK(21, 20) 461#define HSIO_S6G_DFT_CFG0_PRBS_SEL_X(x) (((x) & GENMASK(21, 20)) >> 20) 462#define HSIO_S6G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16)) 463#define HSIO_S6G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16) 464#define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16) 465#define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4) 466#define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3) 467#define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2) 468#define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0) 469 470#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) 471#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8) 472#define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) 473#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) 474#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M GENMASK(7, 4) 475#define HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) 476#define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3) 477#define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2) 478#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1) 479#define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0) 480 481#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8)) 482#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8) 483#define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8) 484#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ(x) (((x) << 4) & GENMASK(7, 4)) 485#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M GENMASK(7, 4) 486#define HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X(x) (((x) & GENMASK(7, 4)) >> 4) 487#define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3) 488#define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2) 489#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1) 490#define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0) 491 492#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20) 493#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH(x) (((x) << 16) & GENMASK(19, 16)) 494#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M GENMASK(19, 16) 495#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X(x) (((x) & GENMASK(19, 16)) >> 16) 496#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8)) 497#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8) 498#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8) 499#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW(x) ((x) & GENMASK(7, 0)) 500#define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M GENMASK(7, 0) 501 502#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK(x) (((x) << 13) & GENMASK(14, 13)) 503#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M GENMASK(14, 13) 504#define HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X(x) (((x) & GENMASK(14, 13)) >> 13) 505#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE(x) (((x) << 11) & GENMASK(12, 11)) 506#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M GENMASK(12, 11) 507#define HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X(x) (((x) & GENMASK(12, 11)) >> 11) 508#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10) 509#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9) 510#define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8) 511#define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7) 512#define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6) 513#define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5) 514#define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4) 515#define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3) 516#define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2) 517#define HSIO_S6G_MISC_CFG_LANE_RST BIT(0) 518 519#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23)) 520#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23) 521#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23) 522#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x) (((x) << 18) & GENMASK(22, 18)) 523#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M GENMASK(22, 18) 524#define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x) (((x) & GENMASK(22, 18)) >> 18) 525#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC(x) (((x) << 13) & GENMASK(17, 13)) 526#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M GENMASK(17, 13) 527#define HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X(x) (((x) & GENMASK(17, 13)) >> 13) 528#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6)) 529#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M GENMASK(8, 6) 530#define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6) 531#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV(x) ((x) & GENMASK(5, 0)) 532#define HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M GENMASK(5, 0) 533 534#define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8) 535#define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7) 536#define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6) 537#define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5) 538#define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3) 539#define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2) 540#define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1) 541#define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0) 542 543#define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0) 544 545#define HSIO_S6G_DES_CFG_DES_PHS_CTRL(x) (((x) << 13) & GENMASK(16, 13)) 546#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_M GENMASK(16, 13) 547#define HSIO_S6G_DES_CFG_DES_PHS_CTRL_X(x) (((x) & GENMASK(16, 13)) >> 13) 548#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 10) & GENMASK(12, 10)) 549#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M GENMASK(12, 10) 550#define HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(12, 10)) >> 10) 551#define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8)) 552#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8) 553#define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8) 554#define HSIO_S6G_DES_CFG_DES_BW_HYST(x) (((x) << 5) & GENMASK(7, 5)) 555#define HSIO_S6G_DES_CFG_DES_BW_HYST_M GENMASK(7, 5) 556#define HSIO_S6G_DES_CFG_DES_BW_HYST_X(x) (((x) & GENMASK(7, 5)) >> 5) 557#define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4) 558#define HSIO_S6G_DES_CFG_DES_BW_ANA(x) (((x) << 1) & GENMASK(3, 1)) 559#define HSIO_S6G_DES_CFG_DES_BW_ANA_M GENMASK(3, 1) 560#define HSIO_S6G_DES_CFG_DES_BW_ANA_X(x) (((x) & GENMASK(3, 1)) >> 1) 561#define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0) 562 563#define HSIO_S6G_IB_CFG_IB_SOFSI(x) (((x) << 29) & GENMASK(30, 29)) 564#define HSIO_S6G_IB_CFG_IB_SOFSI_M GENMASK(30, 29) 565#define HSIO_S6G_IB_CFG_IB_SOFSI_X(x) (((x) & GENMASK(30, 29)) >> 29) 566#define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28) 567#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ(x) (((x) << 24) & GENMASK(27, 24)) 568#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M GENMASK(27, 24) 569#define HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X(x) (((x) & GENMASK(27, 24)) >> 24) 570#define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20)) 571#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20) 572#define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20) 573#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x) (((x) << 18) & GENMASK(19, 18)) 574#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M GENMASK(19, 18) 575#define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x) (((x) & GENMASK(19, 18)) >> 18) 576#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(x) (((x) << 15) & GENMASK(17, 15)) 577#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M GENMASK(17, 15) 578#define HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X(x) (((x) & GENMASK(17, 15)) >> 15) 579#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP(x) (((x) << 13) & GENMASK(14, 13)) 580#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M GENMASK(14, 13) 581#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X(x) (((x) & GENMASK(14, 13)) >> 13) 582#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID(x) (((x) << 11) & GENMASK(12, 11)) 583#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M GENMASK(12, 11) 584#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X(x) (((x) & GENMASK(12, 11)) >> 11) 585#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP(x) (((x) << 9) & GENMASK(10, 9)) 586#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M GENMASK(10, 9) 587#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X(x) (((x) & GENMASK(10, 9)) >> 9) 588#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x) (((x) << 7) & GENMASK(8, 7)) 589#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M GENMASK(8, 7) 590#define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x) (((x) & GENMASK(8, 7)) >> 7) 591#define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6) 592#define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5) 593#define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4) 594#define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3) 595#define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2) 596#define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1) 597#define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0) 598 599#define HSIO_S6G_IB_CFG1_IB_TJTAG(x) (((x) << 17) & GENMASK(21, 17)) 600#define HSIO_S6G_IB_CFG1_IB_TJTAG_M GENMASK(21, 17) 601#define HSIO_S6G_IB_CFG1_IB_TJTAG_X(x) (((x) & GENMASK(21, 17)) >> 17) 602#define HSIO_S6G_IB_CFG1_IB_TSDET(x) (((x) << 12) & GENMASK(16, 12)) 603#define HSIO_S6G_IB_CFG1_IB_TSDET_M GENMASK(16, 12) 604#define HSIO_S6G_IB_CFG1_IB_TSDET_X(x) (((x) & GENMASK(16, 12)) >> 12) 605#define HSIO_S6G_IB_CFG1_IB_SCALY(x) (((x) << 8) & GENMASK(11, 8)) 606#define HSIO_S6G_IB_CFG1_IB_SCALY_M GENMASK(11, 8) 607#define HSIO_S6G_IB_CFG1_IB_SCALY_X(x) (((x) & GENMASK(11, 8)) >> 8) 608#define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7) 609#define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6) 610#define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5) 611#define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4) 612#define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3) 613#define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2) 614#define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1) 615#define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0) 616 617#define HSIO_S6G_IB_CFG2_IB_TINFV(x) (((x) << 27) & GENMASK(29, 27)) 618#define HSIO_S6G_IB_CFG2_IB_TINFV_M GENMASK(29, 27) 619#define HSIO_S6G_IB_CFG2_IB_TINFV_X(x) (((x) & GENMASK(29, 27)) >> 27) 620#define HSIO_S6G_IB_CFG2_IB_OINFI(x) (((x) << 22) & GENMASK(26, 22)) 621#define HSIO_S6G_IB_CFG2_IB_OINFI_M GENMASK(26, 22) 622#define HSIO_S6G_IB_CFG2_IB_OINFI_X(x) (((x) & GENMASK(26, 22)) >> 22) 623#define HSIO_S6G_IB_CFG2_IB_TAUX(x) (((x) << 19) & GENMASK(21, 19)) 624#define HSIO_S6G_IB_CFG2_IB_TAUX_M GENMASK(21, 19) 625#define HSIO_S6G_IB_CFG2_IB_TAUX_X(x) (((x) & GENMASK(21, 19)) >> 19) 626#define HSIO_S6G_IB_CFG2_IB_OINFS(x) (((x) << 16) & GENMASK(18, 16)) 627#define HSIO_S6G_IB_CFG2_IB_OINFS_M GENMASK(18, 16) 628#define HSIO_S6G_IB_CFG2_IB_OINFS_X(x) (((x) & GENMASK(18, 16)) >> 16) 629#define HSIO_S6G_IB_CFG2_IB_OCALS(x) (((x) << 10) & GENMASK(15, 10)) 630#define HSIO_S6G_IB_CFG2_IB_OCALS_M GENMASK(15, 10) 631#define HSIO_S6G_IB_CFG2_IB_OCALS_X(x) (((x) & GENMASK(15, 10)) >> 10) 632#define HSIO_S6G_IB_CFG2_IB_TCALV(x) (((x) << 5) & GENMASK(9, 5)) 633#define HSIO_S6G_IB_CFG2_IB_TCALV_M GENMASK(9, 5) 634#define HSIO_S6G_IB_CFG2_IB_TCALV_X(x) (((x) & GENMASK(9, 5)) >> 5) 635#define HSIO_S6G_IB_CFG2_IB_UMAX(x) (((x) << 3) & GENMASK(4, 3)) 636#define HSIO_S6G_IB_CFG2_IB_UMAX_M GENMASK(4, 3) 637#define HSIO_S6G_IB_CFG2_IB_UMAX_X(x) (((x) & GENMASK(4, 3)) >> 3) 638#define HSIO_S6G_IB_CFG2_IB_UREG(x) ((x) & GENMASK(2, 0)) 639#define HSIO_S6G_IB_CFG2_IB_UREG_M GENMASK(2, 0) 640 641#define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18)) 642#define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18) 643#define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) 644#define HSIO_S6G_IB_CFG3_IB_INI_MID(x) (((x) << 12) & GENMASK(17, 12)) 645#define HSIO_S6G_IB_CFG3_IB_INI_MID_M GENMASK(17, 12) 646#define HSIO_S6G_IB_CFG3_IB_INI_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) 647#define HSIO_S6G_IB_CFG3_IB_INI_LP(x) (((x) << 6) & GENMASK(11, 6)) 648#define HSIO_S6G_IB_CFG3_IB_INI_LP_M GENMASK(11, 6) 649#define HSIO_S6G_IB_CFG3_IB_INI_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) 650#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET(x) ((x) & GENMASK(5, 0)) 651#define HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M GENMASK(5, 0) 652 653#define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18)) 654#define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18) 655#define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) 656#define HSIO_S6G_IB_CFG4_IB_MAX_MID(x) (((x) << 12) & GENMASK(17, 12)) 657#define HSIO_S6G_IB_CFG4_IB_MAX_MID_M GENMASK(17, 12) 658#define HSIO_S6G_IB_CFG4_IB_MAX_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) 659#define HSIO_S6G_IB_CFG4_IB_MAX_LP(x) (((x) << 6) & GENMASK(11, 6)) 660#define HSIO_S6G_IB_CFG4_IB_MAX_LP_M GENMASK(11, 6) 661#define HSIO_S6G_IB_CFG4_IB_MAX_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) 662#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET(x) ((x) & GENMASK(5, 0)) 663#define HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M GENMASK(5, 0) 664 665#define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18)) 666#define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18) 667#define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18) 668#define HSIO_S6G_IB_CFG5_IB_MIN_MID(x) (((x) << 12) & GENMASK(17, 12)) 669#define HSIO_S6G_IB_CFG5_IB_MIN_MID_M GENMASK(17, 12) 670#define HSIO_S6G_IB_CFG5_IB_MIN_MID_X(x) (((x) & GENMASK(17, 12)) >> 12) 671#define HSIO_S6G_IB_CFG5_IB_MIN_LP(x) (((x) << 6) & GENMASK(11, 6)) 672#define HSIO_S6G_IB_CFG5_IB_MIN_LP_M GENMASK(11, 6) 673#define HSIO_S6G_IB_CFG5_IB_MIN_LP_X(x) (((x) & GENMASK(11, 6)) >> 6) 674#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET(x) ((x) & GENMASK(5, 0)) 675#define HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M GENMASK(5, 0) 676 677#define HSIO_S6G_OB_CFG_OB_IDLE BIT(31) 678#define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30) 679#define HSIO_S6G_OB_CFG_OB_POL BIT(29) 680#define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23)) 681#define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23) 682#define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23) 683#define HSIO_S6G_OB_CFG_OB_PREC(x) (((x) << 18) & GENMASK(22, 18)) 684#define HSIO_S6G_OB_CFG_OB_PREC_M GENMASK(22, 18) 685#define HSIO_S6G_OB_CFG_OB_PREC_X(x) (((x) & GENMASK(22, 18)) >> 18) 686#define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17) 687#define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16) 688#define HSIO_S6G_OB_CFG_OB_POST1(x) (((x) << 11) & GENMASK(15, 11)) 689#define HSIO_S6G_OB_CFG_OB_POST1_M GENMASK(15, 11) 690#define HSIO_S6G_OB_CFG_OB_POST1_X(x) (((x) & GENMASK(15, 11)) >> 11) 691#define HSIO_S6G_OB_CFG_OB_R_COR BIT(10) 692#define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9) 693#define HSIO_S6G_OB_CFG_OB_SR_H BIT(8) 694#define HSIO_S6G_OB_CFG_OB_SR(x) (((x) << 4) & GENMASK(7, 4)) 695#define HSIO_S6G_OB_CFG_OB_SR_M GENMASK(7, 4) 696#define HSIO_S6G_OB_CFG_OB_SR_X(x) (((x) & GENMASK(7, 4)) >> 4) 697#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) 698#define HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M GENMASK(3, 0) 699 700#define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6)) 701#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M GENMASK(8, 6) 702#define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6) 703#define HSIO_S6G_OB_CFG1_OB_LEV(x) ((x) & GENMASK(5, 0)) 704#define HSIO_S6G_OB_CFG1_OB_LEV_M GENMASK(5, 0) 705 706#define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8) 707#define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7) 708#define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6) 709#define HSIO_S6G_SER_CFG_SER_ALISEL(x) (((x) << 4) & GENMASK(5, 4)) 710#define HSIO_S6G_SER_CFG_SER_ALISEL_M GENMASK(5, 4) 711#define HSIO_S6G_SER_CFG_SER_ALISEL_X(x) (((x) & GENMASK(5, 4)) >> 4) 712#define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3) 713#define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2) 714#define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1) 715#define HSIO_S6G_SER_CFG_SER_ENALI BIT(0) 716 717#define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17) 718#define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16) 719#define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15) 720#define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14) 721#define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13) 722#define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12) 723#define HSIO_S6G_COMMON_CFG_LANE_CTRL(x) (((x) << 9) & GENMASK(11, 9)) 724#define HSIO_S6G_COMMON_CFG_LANE_CTRL_M GENMASK(11, 9) 725#define HSIO_S6G_COMMON_CFG_LANE_CTRL_X(x) (((x) & GENMASK(11, 9)) >> 9) 726#define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8) 727#define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7) 728#define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6) 729#define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5) 730#define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4) 731#define HSIO_S6G_COMMON_CFG_HRATE BIT(3) 732#define HSIO_S6G_COMMON_CFG_QRATE BIT(2) 733#define HSIO_S6G_COMMON_CFG_IF_MODE(x) ((x) & GENMASK(1, 0)) 734#define HSIO_S6G_COMMON_CFG_IF_MODE_M GENMASK(1, 0) 735 736#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS(x) (((x) << 16) & GENMASK(17, 16)) 737#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M GENMASK(17, 16) 738#define HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X(x) (((x) & GENMASK(17, 16)) >> 16) 739#define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15) 740#define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14) 741#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) 742#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(13, 6) 743#define HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(13, 6)) >> 6) 744#define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5) 745#define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4) 746#define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3) 747#define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2) 748#define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1) 749#define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0) 750 751#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5) 752#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4) 753#define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3) 754#define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2) 755#define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1) 756#define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0) 757 758#define HSIO_S6G_GP_CFG_GP_MSB(x) (((x) << 16) & GENMASK(31, 16)) 759#define HSIO_S6G_GP_CFG_GP_MSB_M GENMASK(31, 16) 760#define HSIO_S6G_GP_CFG_GP_MSB_X(x) (((x) & GENMASK(31, 16)) >> 16) 761#define HSIO_S6G_GP_CFG_GP_LSB(x) ((x) & GENMASK(15, 0)) 762#define HSIO_S6G_GP_CFG_GP_LSB_M GENMASK(15, 0) 763 764#define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8) 765#define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7) 766#define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6) 767#define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5) 768#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4) 769#define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3) 770#define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2) 771#define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1) 772#define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0) 773 774#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18)) 775#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18) 776#define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18) 777#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT(x) (((x) << 12) & GENMASK(17, 12)) 778#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M GENMASK(17, 12) 779#define HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X(x) (((x) & GENMASK(17, 12)) >> 12) 780#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT(x) (((x) << 6) & GENMASK(11, 6)) 781#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M GENMASK(11, 6) 782#define HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X(x) (((x) & GENMASK(11, 6)) >> 6) 783#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT(x) ((x) & GENMASK(5, 0)) 784#define HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M GENMASK(5, 0) 785 786#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2) 787#define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1) 788#define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0) 789 790#define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10) 791#define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9) 792#define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8) 793#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA(x) ((x) & GENMASK(7, 0)) 794#define HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M GENMASK(7, 0) 795 796#define HSIO_S6G_REVID_SERDES_REV(x) (((x) << 26) & GENMASK(31, 26)) 797#define HSIO_S6G_REVID_SERDES_REV_M GENMASK(31, 26) 798#define HSIO_S6G_REVID_SERDES_REV_X(x) (((x) & GENMASK(31, 26)) >> 26) 799#define HSIO_S6G_REVID_RCPLL_REV(x) (((x) << 21) & GENMASK(25, 21)) 800#define HSIO_S6G_REVID_RCPLL_REV_M GENMASK(25, 21) 801#define HSIO_S6G_REVID_RCPLL_REV_X(x) (((x) & GENMASK(25, 21)) >> 21) 802#define HSIO_S6G_REVID_SER_REV(x) (((x) << 16) & GENMASK(20, 16)) 803#define HSIO_S6G_REVID_SER_REV_M GENMASK(20, 16) 804#define HSIO_S6G_REVID_SER_REV_X(x) (((x) & GENMASK(20, 16)) >> 16) 805#define HSIO_S6G_REVID_DES_REV(x) (((x) << 10) & GENMASK(15, 10)) 806#define HSIO_S6G_REVID_DES_REV_M GENMASK(15, 10) 807#define HSIO_S6G_REVID_DES_REV_X(x) (((x) & GENMASK(15, 10)) >> 10) 808#define HSIO_S6G_REVID_OB_REV(x) (((x) << 5) & GENMASK(9, 5)) 809#define HSIO_S6G_REVID_OB_REV_M GENMASK(9, 5) 810#define HSIO_S6G_REVID_OB_REV_X(x) (((x) & GENMASK(9, 5)) >> 5) 811#define HSIO_S6G_REVID_IB_REV(x) ((x) & GENMASK(4, 0)) 812#define HSIO_S6G_REVID_IB_REV_M GENMASK(4, 0) 813 814#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31) 815#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30) 816#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(x) ((x) & GENMASK(24, 0)) 817#define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M GENMASK(24, 0) 818 819#define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6) 820#define HSIO_HW_CFG_DEV1G_9_MODE BIT(5) 821#define HSIO_HW_CFG_DEV1G_6_MODE BIT(4) 822#define HSIO_HW_CFG_DEV1G_5_MODE BIT(3) 823#define HSIO_HW_CFG_DEV1G_4_MODE BIT(2) 824#define HSIO_HW_CFG_PCIE_ENA BIT(1) 825#define HSIO_HW_CFG_QSGMII_ENA BIT(0) 826 827#define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3) 828#define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2) 829#define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1) 830#define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0) 831 832#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS(x) (((x) << 1) & GENMASK(6, 1)) 833#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M GENMASK(6, 1) 834#define HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X(x) (((x) & GENMASK(6, 1)) >> 1) 835#define HSIO_HW_QSGMII_STAT_SYNC BIT(0) 836 837#define HSIO_CLK_CFG_CLKDIV_PHY(x) (((x) << 1) & GENMASK(8, 1)) 838#define HSIO_CLK_CFG_CLKDIV_PHY_M GENMASK(8, 1) 839#define HSIO_CLK_CFG_CLKDIV_PHY_X(x) (((x) & GENMASK(8, 1)) >> 1) 840#define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0) 841 842#define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5) 843#define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4) 844#define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3) 845#define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2) 846#define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1) 847#define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0) 848 849#define HSIO_TEMP_SENSOR_CFG_RUN_WID(x) (((x) << 8) & GENMASK(15, 8)) 850#define HSIO_TEMP_SENSOR_CFG_RUN_WID_M GENMASK(15, 8) 851#define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x) (((x) & GENMASK(15, 8)) >> 8) 852#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER(x) ((x) & GENMASK(7, 0)) 853#define HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M GENMASK(7, 0) 854 855#define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8) 856#define HSIO_TEMP_SENSOR_STAT_TEMP(x) ((x) & GENMASK(7, 0)) 857#define HSIO_TEMP_SENSOR_STAT_TEMP_M GENMASK(7, 0) 858 859#endif 860