1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7#ifndef __ETH_COMMON__ 8#define __ETH_COMMON__ 9 10/********************/ 11/* ETH FW CONSTANTS */ 12/********************/ 13 14#define ETH_HSI_VER_MAJOR 3 15#define ETH_HSI_VER_MINOR 11 16 17#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5 18/* Maximum number of pinned L2 connections (CIDs) */ 19#define ETH_PINNED_CONN_MAX_NUM 32 20 21#define ETH_CACHE_LINE_SIZE 64 22#define ETH_RX_CQE_GAP 32 23#define ETH_MAX_RAMROD_PER_CON 8 24#define ETH_TX_BD_PAGE_SIZE_BYTES 4096 25#define ETH_RX_BD_PAGE_SIZE_BYTES 4096 26#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096 27#define ETH_RX_NUM_NEXT_PAGE_BDS 2 28 29#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253 30#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251 31 32#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1 33#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18 34#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255 35#define ETH_TX_MAX_LSO_HDR_NBD 4 36#define ETH_TX_MIN_BDS_PER_LSO_PKT 3 37#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3 38#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2 39#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2 40#define ETH_TX_MIN_BDS_PER_PKT_W_VPORT_FORWARDING 4 41#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8)) 42#define ETH_TX_MAX_LSO_HDR_BYTES 510 43#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1) 44#define ETH_TX_LSO_WINDOW_MIN_LEN 9700 45#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000 46#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320 47#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF 48 49#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS 50#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \ 51 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2) 52#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \ 53 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4) 54 55#define ETH_RX_MAX_BUFF_PER_PKT 5 56#define ETH_RX_BD_THRESHOLD 16 57 58/* Num of MAC/VLAN filters */ 59#define ETH_NUM_MAC_FILTERS 512 60#define ETH_NUM_VLAN_FILTERS 512 61 62/* Approx. multicast constants */ 63#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0 64#define ETH_MULTICAST_MAC_BINS 256 65#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32) 66 67/* Ethernet vport update constants */ 68#define ETH_FILTER_RULES_COUNT 10 69#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128 70#define ETH_RSS_IND_TABLE_MASK_SIZE_REGS (ETH_RSS_IND_TABLE_ENTRIES_NUM / 32) 71#define ETH_RSS_KEY_SIZE_REGS 10 72#define ETH_RSS_ENGINE_NUM_K2 207 73#define ETH_RSS_ENGINE_NUM_BB 127 74 75/* TPA constants */ 76#define ETH_TPA_MAX_AGGS_NUM 64 77#define ETH_TPA_CQE_START_BW_LEN_LIST_SIZE 2 78#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6 79#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4 80 81/* Control frame check constants */ 82#define ETH_CTL_FRAME_ETH_TYPE_NUM 4 83 84/* GFS constants */ 85#define ETH_GFT_TRASHCAN_VPORT 0x1FF /* GFT drop flow vport number */ 86 87/* Destination port mode */ 88enum dst_port_mode { 89 DST_PORT_PHY, 90 DST_PORT_LOOPBACK, 91 DST_PORT_PHY_LOOPBACK, 92 DST_PORT_DROP, 93 MAX_DST_PORT_MODE 94}; 95 96/* Ethernet address type */ 97enum eth_addr_type { 98 BROADCAST_ADDRESS, 99 MULTICAST_ADDRESS, 100 UNICAST_ADDRESS, 101 UNKNOWN_ADDRESS, 102 MAX_ETH_ADDR_TYPE 103}; 104 105struct eth_tx_1st_bd_flags { 106 u8 bitfields; 107#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1 108#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0 109#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1 110#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1 111#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1 112#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2 113#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1 114#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3 115#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1 116#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4 117#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1 118#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5 119#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1 120#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6 121#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1 122#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7 123}; 124 125/* The parsing information data fo rthe first tx bd of a given packet */ 126struct eth_tx_data_1st_bd { 127 __le16 vlan; 128 u8 nbds; 129 struct eth_tx_1st_bd_flags bd_flags; 130 __le16 bitfields; 131#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1 132#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0 133#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1 134#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1 135#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF 136#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2 137}; 138 139/* The parsing information data for the second tx bd of a given packet */ 140struct eth_tx_data_2nd_bd { 141 __le16 tunn_ip_size; 142 __le16 bitfields1; 143#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF 144#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0 145#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3 146#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4 147#define ETH_TX_DATA_2ND_BD_DST_PORT_MODE_MASK 0x3 148#define ETH_TX_DATA_2ND_BD_DST_PORT_MODE_SHIFT 6 149#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1 150#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8 151#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3 152#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9 153#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1 154#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11 155#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1 156#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12 157#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1 158#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13 159#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1 160#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14 161#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1 162#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15 163 __le16 bitfields2; 164#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF 165#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0 166#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7 167#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13 168}; 169 170/* Firmware data for L2-EDPM packet */ 171struct eth_edpm_fw_data { 172 struct eth_tx_data_1st_bd data_1st_bd; 173 struct eth_tx_data_2nd_bd data_2nd_bd; 174 __le32 reserved; 175}; 176 177/* Tunneling parsing flags */ 178struct eth_tunnel_parsing_flags { 179 u8 flags; 180#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3 181#define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0 182#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1 183#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2 184#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3 185#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3 186#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1 187#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5 188#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1 189#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6 190#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1 191#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7 192}; 193 194/* PMD flow control bits */ 195struct eth_pmd_flow_flags { 196 u8 flags; 197#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1 198#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0 199#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1 200#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1 201#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F 202#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2 203}; 204 205/* Regular ETH Rx FP CQE */ 206struct eth_fast_path_rx_reg_cqe { 207 u8 type; 208 u8 bitfields; 209#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7 210#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0 211#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF 212#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3 213#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1 214#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7 215 __le16 pkt_len; 216 struct parsing_and_err_flags pars_flags; 217 __le16 vlan_tag; 218 __le32 rss_hash; 219 __le16 len_on_first_bd; 220 u8 placement_offset; 221 struct eth_tunnel_parsing_flags tunnel_pars_flags; 222 u8 bd_num; 223 u8 reserved; 224 __le16 reserved2; 225 __le32 flow_id_or_resource_id; 226 u8 reserved1[7]; 227 struct eth_pmd_flow_flags pmd_flags; 228}; 229 230/* TPA-continue ETH Rx FP CQE */ 231struct eth_fast_path_rx_tpa_cont_cqe { 232 u8 type; 233 u8 tpa_agg_index; 234 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]; 235 u8 reserved; 236 u8 reserved1; 237 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]; 238 u8 reserved3[3]; 239 struct eth_pmd_flow_flags pmd_flags; 240}; 241 242/* TPA-end ETH Rx FP CQE */ 243struct eth_fast_path_rx_tpa_end_cqe { 244 u8 type; 245 u8 tpa_agg_index; 246 __le16 total_packet_len; 247 u8 num_of_bds; 248 u8 end_reason; 249 __le16 num_of_coalesced_segs; 250 __le32 ts_delta; 251 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE]; 252 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE]; 253 __le16 reserved1; 254 u8 reserved2; 255 struct eth_pmd_flow_flags pmd_flags; 256}; 257 258/* TPA-start ETH Rx FP CQE */ 259struct eth_fast_path_rx_tpa_start_cqe { 260 u8 type; 261 u8 bitfields; 262#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7 263#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0 264#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF 265#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3 266#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1 267#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7 268 __le16 seg_len; 269 struct parsing_and_err_flags pars_flags; 270 __le16 vlan_tag; 271 __le32 rss_hash; 272 __le16 len_on_first_bd; 273 u8 placement_offset; 274 struct eth_tunnel_parsing_flags tunnel_pars_flags; 275 u8 tpa_agg_index; 276 u8 header_len; 277 __le16 bw_ext_bd_len_list[ETH_TPA_CQE_START_BW_LEN_LIST_SIZE]; 278 __le16 reserved2; 279 __le32 flow_id_or_resource_id; 280 u8 reserved[3]; 281 struct eth_pmd_flow_flags pmd_flags; 282}; 283 284/* The L4 pseudo checksum mode for Ethernet */ 285enum eth_l4_pseudo_checksum_mode { 286 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH, 287 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH, 288 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE 289}; 290 291struct eth_rx_bd { 292 struct regpair addr; 293}; 294 295/* Regular ETH Rx SP CQE */ 296struct eth_slow_path_rx_cqe { 297 u8 type; 298 u8 ramrod_cmd_id; 299 u8 error_flag; 300 u8 reserved[25]; 301 __le16 echo; 302 u8 reserved1; 303 struct eth_pmd_flow_flags pmd_flags; 304}; 305 306/* Union for all ETH Rx CQE types */ 307union eth_rx_cqe { 308 struct eth_fast_path_rx_reg_cqe fast_path_regular; 309 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start; 310 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont; 311 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end; 312 struct eth_slow_path_rx_cqe slow_path; 313}; 314 315/* ETH Rx CQE type */ 316enum eth_rx_cqe_type { 317 ETH_RX_CQE_TYPE_UNUSED, 318 ETH_RX_CQE_TYPE_REGULAR, 319 ETH_RX_CQE_TYPE_SLOW_PATH, 320 ETH_RX_CQE_TYPE_TPA_START, 321 ETH_RX_CQE_TYPE_TPA_CONT, 322 ETH_RX_CQE_TYPE_TPA_END, 323 MAX_ETH_RX_CQE_TYPE 324}; 325 326struct eth_rx_pmd_cqe { 327 union eth_rx_cqe cqe; 328 u8 reserved[ETH_RX_CQE_GAP]; 329}; 330 331enum eth_rx_tunn_type { 332 ETH_RX_NO_TUNN, 333 ETH_RX_TUNN_GENEVE, 334 ETH_RX_TUNN_GRE, 335 ETH_RX_TUNN_VXLAN, 336 MAX_ETH_RX_TUNN_TYPE 337}; 338 339/* Aggregation end reason. */ 340enum eth_tpa_end_reason { 341 ETH_AGG_END_UNUSED, 342 ETH_AGG_END_SP_UPDATE, 343 ETH_AGG_END_MAX_LEN, 344 ETH_AGG_END_LAST_SEG, 345 ETH_AGG_END_TIMEOUT, 346 ETH_AGG_END_NOT_CONSISTENT, 347 ETH_AGG_END_OUT_OF_ORDER, 348 ETH_AGG_END_NON_TPA_SEG, 349 MAX_ETH_TPA_END_REASON 350}; 351 352/* The first tx bd of a given packet */ 353struct eth_tx_1st_bd { 354 struct regpair addr; 355 __le16 nbytes; 356 struct eth_tx_data_1st_bd data; 357}; 358 359/* The second tx bd of a given packet */ 360struct eth_tx_2nd_bd { 361 struct regpair addr; 362 __le16 nbytes; 363 struct eth_tx_data_2nd_bd data; 364}; 365 366/* The parsing information data for the third tx bd of a given packet */ 367struct eth_tx_data_3rd_bd { 368 __le16 lso_mss; 369 __le16 bitfields; 370#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF 371#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0 372#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF 373#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4 374#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1 375#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8 376#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F 377#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9 378 u8 tunn_l4_hdr_start_offset_w; 379 u8 tunn_hdr_size_w; 380}; 381 382/* The third tx bd of a given packet */ 383struct eth_tx_3rd_bd { 384 struct regpair addr; 385 __le16 nbytes; 386 struct eth_tx_data_3rd_bd data; 387}; 388 389/* The parsing information data for the forth tx bd of a given packet. */ 390struct eth_tx_data_4th_bd { 391 u8 dst_vport_id; 392 u8 reserved4; 393 __le16 bitfields; 394#define ETH_TX_DATA_4TH_BD_DST_VPORT_ID_VALID_MASK 0x1 395#define ETH_TX_DATA_4TH_BD_DST_VPORT_ID_VALID_SHIFT 0 396#define ETH_TX_DATA_4TH_BD_RESERVED1_MASK 0x7F 397#define ETH_TX_DATA_4TH_BD_RESERVED1_SHIFT 1 398#define ETH_TX_DATA_4TH_BD_START_BD_MASK 0x1 399#define ETH_TX_DATA_4TH_BD_START_BD_SHIFT 8 400#define ETH_TX_DATA_4TH_BD_RESERVED2_MASK 0x7F 401#define ETH_TX_DATA_4TH_BD_RESERVED2_SHIFT 9 402 __le16 reserved3; 403}; 404 405/* The forth tx bd of a given packet */ 406struct eth_tx_4th_bd { 407 struct regpair addr; /* Single continuous buffer */ 408 __le16 nbytes; /* Number of bytes in this BD */ 409 struct eth_tx_data_4th_bd data; /* Parsing information data */ 410}; 411 412/* Complementary information for the regular tx bd of a given packet */ 413struct eth_tx_data_bd { 414 __le16 reserved0; 415 __le16 bitfields; 416#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF 417#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0 418#define ETH_TX_DATA_BD_START_BD_MASK 0x1 419#define ETH_TX_DATA_BD_START_BD_SHIFT 8 420#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F 421#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9 422 __le16 reserved3; 423}; 424 425/* The common non-special TX BD ring element */ 426struct eth_tx_bd { 427 struct regpair addr; 428 __le16 nbytes; 429 struct eth_tx_data_bd data; 430}; 431 432union eth_tx_bd_types { 433 struct eth_tx_1st_bd first_bd; 434 struct eth_tx_2nd_bd second_bd; 435 struct eth_tx_3rd_bd third_bd; 436 struct eth_tx_4th_bd fourth_bd; 437 struct eth_tx_bd reg_bd; 438}; 439 440/* Mstorm Queue Zone */ 441enum eth_tx_tunn_type { 442 ETH_TX_TUNN_GENEVE, 443 ETH_TX_TUNN_TTAG, 444 ETH_TX_TUNN_GRE, 445 ETH_TX_TUNN_VXLAN, 446 MAX_ETH_TX_TUNN_TYPE 447}; 448 449/* Mstorm Queue Zone */ 450struct mstorm_eth_queue_zone { 451 struct eth_rx_prod_data rx_producers; 452 __le32 reserved[3]; 453}; 454 455/* Ystorm Queue Zone */ 456struct xstorm_eth_queue_zone { 457 struct coalescing_timeset int_coalescing_timeset; 458 u8 reserved[7]; 459}; 460 461/* ETH doorbell data */ 462struct eth_db_data { 463 u8 params; 464#define ETH_DB_DATA_DEST_MASK 0x3 465#define ETH_DB_DATA_DEST_SHIFT 0 466#define ETH_DB_DATA_AGG_CMD_MASK 0x3 467#define ETH_DB_DATA_AGG_CMD_SHIFT 2 468#define ETH_DB_DATA_BYPASS_EN_MASK 0x1 469#define ETH_DB_DATA_BYPASS_EN_SHIFT 4 470#define ETH_DB_DATA_RESERVED_MASK 0x1 471#define ETH_DB_DATA_RESERVED_SHIFT 5 472#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3 473#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6 474 u8 agg_flags; 475 __le16 bd_prod; 476}; 477 478/* RSS hash type */ 479enum rss_hash_type { 480 RSS_HASH_TYPE_DEFAULT = 0, 481 RSS_HASH_TYPE_IPV4 = 1, 482 RSS_HASH_TYPE_TCP_IPV4 = 2, 483 RSS_HASH_TYPE_IPV6 = 3, 484 RSS_HASH_TYPE_TCP_IPV6 = 4, 485 RSS_HASH_TYPE_UDP_IPV4 = 5, 486 RSS_HASH_TYPE_UDP_IPV6 = 6, 487 MAX_RSS_HASH_TYPE 488}; 489 490#endif /* __ETH_COMMON__ */ 491