1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) ST Ericsson SA 2011 4 * 5 * STE Ux500 PRCMU API 6 */ 7#ifndef __MACH_PRCMU_H 8#define __MACH_PRCMU_H 9 10#include <linux/interrupt.h> 11#include <linux/notifier.h> 12#include <linux/err.h> 13 14#include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */ 15 16/* Offset for the firmware version within the TCPM */ 17#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4 18#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8 19 20/* PRCMU Wakeup defines */ 21enum prcmu_wakeup_index { 22 PRCMU_WAKEUP_INDEX_RTC, 23 PRCMU_WAKEUP_INDEX_RTT0, 24 PRCMU_WAKEUP_INDEX_RTT1, 25 PRCMU_WAKEUP_INDEX_HSI0, 26 PRCMU_WAKEUP_INDEX_HSI1, 27 PRCMU_WAKEUP_INDEX_USB, 28 PRCMU_WAKEUP_INDEX_ABB, 29 PRCMU_WAKEUP_INDEX_ABB_FIFO, 30 PRCMU_WAKEUP_INDEX_ARM, 31 PRCMU_WAKEUP_INDEX_CD_IRQ, 32 NUM_PRCMU_WAKEUP_INDICES 33}; 34#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) 35 36/* EPOD (power domain) IDs */ 37 38/* 39 * DB8500 EPODs 40 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP 41 * - EPOD_ID_SVAPIPE: power domain for SVA pipe 42 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP 43 * - EPOD_ID_SIAPIPE: power domain for SIA pipe 44 * - EPOD_ID_SGA: power domain for SGA 45 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE 46 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 47 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 48 * - NUM_EPOD_ID: number of power domains 49 * 50 * TODO: These should be prefixed. 51 */ 52#define EPOD_ID_SVAMMDSP 0 53#define EPOD_ID_SVAPIPE 1 54#define EPOD_ID_SIAMMDSP 2 55#define EPOD_ID_SIAPIPE 3 56#define EPOD_ID_SGA 4 57#define EPOD_ID_B2R2_MCDE 5 58#define EPOD_ID_ESRAM12 6 59#define EPOD_ID_ESRAM34 7 60#define NUM_EPOD_ID 8 61 62/* 63 * state definition for EPOD (power domain) 64 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged 65 * - EPOD_STATE_OFF: The EPOD is switched off 66 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in 67 * retention 68 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off 69 * - EPOD_STATE_ON: Same as above, but with clock enabled 70 */ 71#define EPOD_STATE_NO_CHANGE 0x00 72#define EPOD_STATE_OFF 0x01 73#define EPOD_STATE_RAMRET 0x02 74#define EPOD_STATE_ON_CLK_OFF 0x03 75#define EPOD_STATE_ON 0x04 76 77/* 78 * CLKOUT sources 79 */ 80#define PRCMU_CLKSRC_CLK38M 0x00 81#define PRCMU_CLKSRC_ACLK 0x01 82#define PRCMU_CLKSRC_SYSCLK 0x02 83#define PRCMU_CLKSRC_LCDCLK 0x03 84#define PRCMU_CLKSRC_SDMMCCLK 0x04 85#define PRCMU_CLKSRC_TVCLK 0x05 86#define PRCMU_CLKSRC_TIMCLK 0x06 87#define PRCMU_CLKSRC_CLK009 0x07 88/* These are only valid for CLKOUT1: */ 89#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 90#define PRCMU_CLKSRC_I2CCLK 0x41 91#define PRCMU_CLKSRC_MSP02CLK 0x42 92#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 93#define PRCMU_CLKSRC_HSIRXCLK 0x44 94#define PRCMU_CLKSRC_HSITXCLK 0x45 95#define PRCMU_CLKSRC_ARMCLKFIX 0x46 96#define PRCMU_CLKSRC_HDMICLK 0x47 97 98/** 99 * enum prcmu_wdog_id - PRCMU watchdog IDs 100 * @PRCMU_WDOG_ALL: use all timers 101 * @PRCMU_WDOG_CPU1: use first CPU timer only 102 * @PRCMU_WDOG_CPU2: use second CPU timer conly 103 */ 104enum prcmu_wdog_id { 105 PRCMU_WDOG_ALL = 0x00, 106 PRCMU_WDOG_CPU1 = 0x01, 107 PRCMU_WDOG_CPU2 = 0x02, 108}; 109 110/** 111 * enum ape_opp - APE OPP states definition 112 * @APE_OPP_INIT: 113 * @APE_NO_CHANGE: The APE operating point is unchanged 114 * @APE_100_OPP: The new APE operating point is ape100opp 115 * @APE_50_OPP: 50% 116 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. 117 */ 118enum ape_opp { 119 APE_OPP_INIT = 0x00, 120 APE_NO_CHANGE = 0x01, 121 APE_100_OPP = 0x02, 122 APE_50_OPP = 0x03, 123 APE_50_PARTLY_25_OPP = 0xFF, 124}; 125 126/** 127 * enum arm_opp - ARM OPP states definition 128 * @ARM_OPP_INIT: 129 * @ARM_NO_CHANGE: The ARM operating point is unchanged 130 * @ARM_100_OPP: The new ARM operating point is arm100opp 131 * @ARM_50_OPP: The new ARM operating point is arm50opp 132 * @ARM_MAX_OPP: Operating point is "max" (more than 100) 133 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 134 * @ARM_EXTCLK: The new ARM operating point is armExtClk 135 */ 136enum arm_opp { 137 ARM_OPP_INIT = 0x00, 138 ARM_NO_CHANGE = 0x01, 139 ARM_100_OPP = 0x02, 140 ARM_50_OPP = 0x03, 141 ARM_MAX_OPP = 0x04, 142 ARM_MAX_FREQ100OPP = 0x05, 143 ARM_EXTCLK = 0x07 144}; 145 146/** 147 * enum ddr_opp - DDR OPP states definition 148 * @DDR_100_OPP: The new DDR operating point is ddr100opp 149 * @DDR_50_OPP: The new DDR operating point is ddr50opp 150 * @DDR_25_OPP: The new DDR operating point is ddr25opp 151 */ 152enum ddr_opp { 153 DDR_100_OPP = 0x00, 154 DDR_50_OPP = 0x01, 155 DDR_25_OPP = 0x02, 156}; 157 158/* 159 * Definitions for controlling ESRAM0 in deep sleep. 160 */ 161#define ESRAM0_DEEP_SLEEP_STATE_OFF 1 162#define ESRAM0_DEEP_SLEEP_STATE_RET 2 163 164/** 165 * enum ddr_pwrst - DDR power states definition 166 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged 167 * @DDR_PWR_STATE_ON: 168 * @DDR_PWR_STATE_OFFLOWLAT: 169 * @DDR_PWR_STATE_OFFHIGHLAT: 170 */ 171enum ddr_pwrst { 172 DDR_PWR_STATE_UNCHANGED = 0x00, 173 DDR_PWR_STATE_ON = 0x01, 174 DDR_PWR_STATE_OFFLOWLAT = 0x02, 175 DDR_PWR_STATE_OFFHIGHLAT = 0x03 176}; 177 178#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4 179 180#define PRCMU_FW_PROJECT_U8500 2 181#define PRCMU_FW_PROJECT_U8400 3 182#define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */ 183#define PRCMU_FW_PROJECT_U8500_MBB 5 184#define PRCMU_FW_PROJECT_U8500_C1 6 185#define PRCMU_FW_PROJECT_U8500_C2 7 186#define PRCMU_FW_PROJECT_U8500_C3 8 187#define PRCMU_FW_PROJECT_U8500_C4 9 188#define PRCMU_FW_PROJECT_U9500_MBL 10 189#define PRCMU_FW_PROJECT_U8500_SSG1 11 /* Samsung specific */ 190#define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */ 191#define PRCMU_FW_PROJECT_U8520 13 192#define PRCMU_FW_PROJECT_U8420 14 193#define PRCMU_FW_PROJECT_U8500_SSG2 15 /* Samsung specific */ 194#define PRCMU_FW_PROJECT_U8420_SYSCLK 17 195#define PRCMU_FW_PROJECT_A9420 20 196/* [32..63] 9540 and derivatives */ 197#define PRCMU_FW_PROJECT_U9540 32 198/* [64..95] 8540 and derivatives */ 199#define PRCMU_FW_PROJECT_L8540 64 200/* [96..126] 8580 and derivatives */ 201#define PRCMU_FW_PROJECT_L8580 96 202 203#define PRCMU_FW_PROJECT_NAME_LEN 20 204struct prcmu_fw_version { 205 u32 project; /* Notice, project shifted with 8 on ux540 */ 206 u8 api_version; 207 u8 func_version; 208 u8 errata; 209 char project_name[PRCMU_FW_PROJECT_NAME_LEN]; 210}; 211 212#include <linux/mfd/db8500-prcmu.h> 213 214#if defined(CONFIG_UX500_SOC_DB8500) 215 216static inline void prcmu_early_init(void) 217{ 218 return db8500_prcmu_early_init(); 219} 220 221static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 222 bool keep_ap_pll) 223{ 224 return db8500_prcmu_set_power_state(state, keep_ulp_clk, 225 keep_ap_pll); 226} 227 228static inline u8 prcmu_get_power_state_result(void) 229{ 230 return db8500_prcmu_get_power_state_result(); 231} 232 233static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 234{ 235 return db8500_prcmu_set_epod(epod_id, epod_state); 236} 237 238static inline void prcmu_enable_wakeups(u32 wakeups) 239{ 240 db8500_prcmu_enable_wakeups(wakeups); 241} 242 243static inline void prcmu_disable_wakeups(void) 244{ 245 prcmu_enable_wakeups(0); 246} 247 248static inline void prcmu_config_abb_event_readout(u32 abb_events) 249{ 250 db8500_prcmu_config_abb_event_readout(abb_events); 251} 252 253static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 254{ 255 db8500_prcmu_get_abb_event_buffer(buf); 256} 257 258int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 259int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); 260int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size); 261 262int prcmu_config_clkout(u8 clkout, u8 source, u8 div); 263 264static inline int prcmu_request_clock(u8 clock, bool enable) 265{ 266 return db8500_prcmu_request_clock(clock, enable); 267} 268 269unsigned long prcmu_clock_rate(u8 clock); 270long prcmu_round_clock_rate(u8 clock, unsigned long rate); 271int prcmu_set_clock_rate(u8 clock, unsigned long rate); 272 273static inline int prcmu_get_ddr_opp(void) 274{ 275 return db8500_prcmu_get_ddr_opp(); 276} 277 278static inline int prcmu_set_arm_opp(u8 opp) 279{ 280 return db8500_prcmu_set_arm_opp(opp); 281} 282 283static inline int prcmu_get_arm_opp(void) 284{ 285 return db8500_prcmu_get_arm_opp(); 286} 287 288static inline int prcmu_set_ape_opp(u8 opp) 289{ 290 return db8500_prcmu_set_ape_opp(opp); 291} 292 293static inline int prcmu_get_ape_opp(void) 294{ 295 return db8500_prcmu_get_ape_opp(); 296} 297 298static inline int prcmu_request_ape_opp_100_voltage(bool enable) 299{ 300 return db8500_prcmu_request_ape_opp_100_voltage(enable); 301} 302 303static inline void prcmu_system_reset(u16 reset_code) 304{ 305 return db8500_prcmu_system_reset(reset_code); 306} 307 308static inline u16 prcmu_get_reset_code(void) 309{ 310 return db8500_prcmu_get_reset_code(); 311} 312 313int prcmu_ac_wake_req(void); 314void prcmu_ac_sleep_req(void); 315static inline void prcmu_modem_reset(void) 316{ 317 return db8500_prcmu_modem_reset(); 318} 319 320static inline bool prcmu_is_ac_wake_requested(void) 321{ 322 return db8500_prcmu_is_ac_wake_requested(); 323} 324 325static inline int prcmu_config_esram0_deep_sleep(u8 state) 326{ 327 return db8500_prcmu_config_esram0_deep_sleep(state); 328} 329 330static inline int prcmu_config_hotdog(u8 threshold) 331{ 332 return db8500_prcmu_config_hotdog(threshold); 333} 334 335static inline int prcmu_config_hotmon(u8 low, u8 high) 336{ 337 return db8500_prcmu_config_hotmon(low, high); 338} 339 340static inline int prcmu_start_temp_sense(u16 cycles32k) 341{ 342 return db8500_prcmu_start_temp_sense(cycles32k); 343} 344 345static inline int prcmu_stop_temp_sense(void) 346{ 347 return db8500_prcmu_stop_temp_sense(); 348} 349 350static inline u32 prcmu_read(unsigned int reg) 351{ 352 return db8500_prcmu_read(reg); 353} 354 355static inline void prcmu_write(unsigned int reg, u32 value) 356{ 357 db8500_prcmu_write(reg, value); 358} 359 360static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 361{ 362 db8500_prcmu_write_masked(reg, mask, value); 363} 364 365static inline int prcmu_enable_a9wdog(u8 id) 366{ 367 return db8500_prcmu_enable_a9wdog(id); 368} 369 370static inline int prcmu_disable_a9wdog(u8 id) 371{ 372 return db8500_prcmu_disable_a9wdog(id); 373} 374 375static inline int prcmu_kick_a9wdog(u8 id) 376{ 377 return db8500_prcmu_kick_a9wdog(id); 378} 379 380static inline int prcmu_load_a9wdog(u8 id, u32 timeout) 381{ 382 return db8500_prcmu_load_a9wdog(id, timeout); 383} 384 385static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 386{ 387 return db8500_prcmu_config_a9wdog(num, sleep_auto_off); 388} 389#else 390 391static inline void prcmu_early_init(void) {} 392 393static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 394 bool keep_ap_pll) 395{ 396 return 0; 397} 398 399static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 400{ 401 return 0; 402} 403 404static inline void prcmu_enable_wakeups(u32 wakeups) {} 405 406static inline void prcmu_disable_wakeups(void) {} 407 408static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 409{ 410 return -ENOSYS; 411} 412 413static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 414{ 415 return -ENOSYS; 416} 417 418static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, 419 u8 size) 420{ 421 return -ENOSYS; 422} 423 424static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 425{ 426 return 0; 427} 428 429static inline int prcmu_request_clock(u8 clock, bool enable) 430{ 431 return 0; 432} 433 434static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) 435{ 436 return 0; 437} 438 439static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) 440{ 441 return 0; 442} 443 444static inline unsigned long prcmu_clock_rate(u8 clock) 445{ 446 return 0; 447} 448 449static inline int prcmu_set_ape_opp(u8 opp) 450{ 451 return 0; 452} 453 454static inline int prcmu_get_ape_opp(void) 455{ 456 return APE_100_OPP; 457} 458 459static inline int prcmu_request_ape_opp_100_voltage(bool enable) 460{ 461 return 0; 462} 463 464static inline int prcmu_set_arm_opp(u8 opp) 465{ 466 return 0; 467} 468 469static inline int prcmu_get_arm_opp(void) 470{ 471 return ARM_100_OPP; 472} 473 474static inline int prcmu_get_ddr_opp(void) 475{ 476 return DDR_100_OPP; 477} 478 479static inline void prcmu_system_reset(u16 reset_code) {} 480 481static inline u16 prcmu_get_reset_code(void) 482{ 483 return 0; 484} 485 486static inline int prcmu_ac_wake_req(void) 487{ 488 return 0; 489} 490 491static inline void prcmu_ac_sleep_req(void) {} 492 493static inline void prcmu_modem_reset(void) {} 494 495static inline bool prcmu_is_ac_wake_requested(void) 496{ 497 return false; 498} 499 500static inline int prcmu_config_esram0_deep_sleep(u8 state) 501{ 502 return 0; 503} 504 505static inline void prcmu_config_abb_event_readout(u32 abb_events) {} 506 507static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 508{ 509 *buf = NULL; 510} 511 512static inline int prcmu_config_hotdog(u8 threshold) 513{ 514 return 0; 515} 516 517static inline int prcmu_config_hotmon(u8 low, u8 high) 518{ 519 return 0; 520} 521 522static inline int prcmu_start_temp_sense(u16 cycles32k) 523{ 524 return 0; 525} 526 527static inline int prcmu_stop_temp_sense(void) 528{ 529 return 0; 530} 531 532static inline u32 prcmu_read(unsigned int reg) 533{ 534 return 0; 535} 536 537static inline void prcmu_write(unsigned int reg, u32 value) {} 538 539static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} 540 541#endif 542 543static inline void prcmu_set(unsigned int reg, u32 bits) 544{ 545 prcmu_write_masked(reg, bits, bits); 546} 547 548static inline void prcmu_clear(unsigned int reg, u32 bits) 549{ 550 prcmu_write_masked(reg, bits, 0); 551} 552 553/* PRCMU QoS APE OPP class */ 554#define PRCMU_QOS_APE_OPP 1 555#define PRCMU_QOS_DDR_OPP 2 556#define PRCMU_QOS_ARM_OPP 3 557#define PRCMU_QOS_DEFAULT_VALUE -1 558 559static inline int prcmu_qos_add_requirement(int prcmu_qos_class, 560 char *name, s32 value) 561{ 562 return 0; 563} 564 565static inline int prcmu_qos_update_requirement(int prcmu_qos_class, 566 char *name, s32 new_value) 567{ 568 return 0; 569} 570 571static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) 572{ 573} 574 575#endif /* __MACH_PRCMU_H */ 576