1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Marvell 88PM80x Interface
4 *
5 * Copyright (C) 2012 Marvell International Ltd.
6 * Qiao Zhou <zhouqiao@marvell.com>
7 */
8
9#ifndef __LINUX_MFD_88PM80X_H
10#define __LINUX_MFD_88PM80X_H
11
12#include <linux/platform_device.h>
13#include <linux/interrupt.h>
14#include <linux/regmap.h>
15#include <linux/atomic.h>
16
17enum {
18	CHIP_INVALID = 0,
19	CHIP_PM800,
20	CHIP_PM805,
21	CHIP_PM860,
22	CHIP_MAX,
23};
24
25enum {
26	PM800_ID_BUCK1 = 0,
27	PM800_ID_BUCK2,
28	PM800_ID_BUCK3,
29	PM800_ID_BUCK4,
30	PM800_ID_BUCK5,
31
32	PM800_ID_LDO1,
33	PM800_ID_LDO2,
34	PM800_ID_LDO3,
35	PM800_ID_LDO4,
36	PM800_ID_LDO5,
37	PM800_ID_LDO6,
38	PM800_ID_LDO7,
39	PM800_ID_LDO8,
40	PM800_ID_LDO9,
41	PM800_ID_LDO10,
42	PM800_ID_LDO11,
43	PM800_ID_LDO12,
44	PM800_ID_LDO13,
45	PM800_ID_LDO14,
46	PM800_ID_LDO15,
47	PM800_ID_LDO16,
48	PM800_ID_LDO17,
49	PM800_ID_LDO18,
50	PM800_ID_LDO19,
51
52	PM800_ID_RG_MAX,
53};
54#define PM800_MAX_REGULATOR	PM800_ID_RG_MAX	/* 5 Bucks, 19 LDOs */
55#define PM800_NUM_BUCK (5)	/*5 Bucks */
56#define PM800_NUM_LDO (19)	/*19 Bucks */
57
58/* page 0 basic: slave adder 0x60 */
59
60#define PM800_STATUS_1			(0x01)
61#define PM800_ONKEY_STS1		BIT(0)
62#define PM800_EXTON_STS1		BIT(1)
63#define PM800_CHG_STS1			BIT(2)
64#define PM800_BAT_STS1			BIT(3)
65#define PM800_VBUS_STS1			BIT(4)
66#define PM800_LDO_PGOOD_STS1		BIT(5)
67#define PM800_BUCK_PGOOD_STS1		BIT(6)
68
69#define PM800_STATUS_2			(0x02)
70#define PM800_RTC_ALARM_STS2		BIT(0)
71
72/* Wakeup Registers */
73#define PM800_WAKEUP1			(0x0D)
74
75#define PM800_WAKEUP2			(0x0E)
76#define PM800_WAKEUP2_INV_INT		BIT(0)
77#define PM800_WAKEUP2_INT_CLEAR		BIT(1)
78#define PM800_WAKEUP2_INT_MASK		BIT(2)
79
80#define PM800_POWER_UP_LOG		(0x10)
81
82/* Referance and low power registers */
83#define PM800_LOW_POWER1		(0x20)
84#define PM800_LOW_POWER2		(0x21)
85#define PM800_LOW_POWER_CONFIG3		(0x22)
86#define PM800_LOW_POWER_CONFIG4		(0x23)
87
88/* GPIO register */
89#define PM800_GPIO_0_1_CNTRL		(0x30)
90#define PM800_GPIO0_VAL			BIT(0)
91#define PM800_GPIO0_GPIO_MODE(x)	(x << 1)
92#define PM800_GPIO1_VAL			BIT(4)
93#define PM800_GPIO1_GPIO_MODE(x)	(x << 5)
94
95#define PM800_GPIO_2_3_CNTRL		(0x31)
96#define PM800_GPIO2_VAL			BIT(0)
97#define PM800_GPIO2_GPIO_MODE(x)	(x << 1)
98#define PM800_GPIO3_VAL			BIT(4)
99#define PM800_GPIO3_GPIO_MODE(x)	(x << 5)
100#define PM800_GPIO3_MODE_MASK		0x1F
101#define PM800_GPIO3_HEADSET_MODE	PM800_GPIO3_GPIO_MODE(6)
102
103#define PM800_GPIO_4_CNTRL		(0x32)
104#define PM800_GPIO4_VAL			BIT(0)
105#define PM800_GPIO4_GPIO_MODE(x)	(x << 1)
106
107#define PM800_HEADSET_CNTRL		(0x38)
108#define PM800_HEADSET_DET_EN		BIT(7)
109#define PM800_HSDET_SLP			BIT(1)
110/* PWM register */
111#define PM800_PWM1			(0x40)
112#define PM800_PWM2			(0x41)
113#define PM800_PWM3			(0x42)
114#define PM800_PWM4			(0x43)
115
116/* RTC Registers */
117#define PM800_RTC_CONTROL		(0xD0)
118#define PM800_RTC_MISC1			(0xE1)
119#define PM800_RTC_MISC2			(0xE2)
120#define PM800_RTC_MISC3			(0xE3)
121#define PM800_RTC_MISC4			(0xE4)
122#define PM800_RTC_MISC5			(0xE7)
123/* bit definitions of RTC Register 1 (0xD0) */
124#define PM800_ALARM1_EN			BIT(0)
125#define PM800_ALARM_WAKEUP		BIT(4)
126#define PM800_ALARM			BIT(5)
127#define PM800_RTC1_USE_XO		BIT(7)
128
129/* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */
130
131/* buck registers */
132#define PM800_SLEEP_BUCK1		(0x30)
133
134/* BUCK Sleep Mode Register 1: BUCK[1..4] */
135#define PM800_BUCK_SLP1			(0x5A)
136#define PM800_BUCK1_SLP1_SHIFT		0
137#define PM800_BUCK1_SLP1_MASK		(0x3 << PM800_BUCK1_SLP1_SHIFT)
138
139/* page 2 GPADC: slave adder 0x02 */
140#define PM800_GPADC_MEAS_EN1		(0x01)
141#define PM800_MEAS_EN1_VBAT		BIT(2)
142#define PM800_GPADC_MEAS_EN2		(0x02)
143#define PM800_MEAS_EN2_RFTMP		BIT(0)
144#define PM800_MEAS_GP0_EN		BIT(2)
145#define PM800_MEAS_GP1_EN		BIT(3)
146#define PM800_MEAS_GP2_EN		BIT(4)
147#define PM800_MEAS_GP3_EN		BIT(5)
148#define PM800_MEAS_GP4_EN		BIT(6)
149
150#define PM800_GPADC_MISC_CONFIG1	(0x05)
151#define PM800_GPADC_MISC_CONFIG2	(0x06)
152#define PM800_GPADC_MISC_GPFSM_EN	BIT(0)
153#define PM800_GPADC_SLOW_MODE(x)	(x << 3)
154
155#define PM800_GPADC_MISC_CONFIG3	(0x09)
156#define PM800_GPADC_MISC_CONFIG4	(0x0A)
157
158#define PM800_GPADC_PREBIAS1		(0x0F)
159#define PM800_GPADC0_GP_PREBIAS_TIME(x)	(x << 0)
160#define PM800_GPADC_PREBIAS2		(0x10)
161
162#define PM800_GP_BIAS_ENA1		(0x14)
163#define PM800_GPADC_GP_BIAS_EN0		BIT(0)
164#define PM800_GPADC_GP_BIAS_EN1		BIT(1)
165#define PM800_GPADC_GP_BIAS_EN2		BIT(2)
166#define PM800_GPADC_GP_BIAS_EN3		BIT(3)
167
168#define PM800_GP_BIAS_OUT1		(0x15)
169#define PM800_BIAS_OUT_GP0		BIT(0)
170#define PM800_BIAS_OUT_GP1		BIT(1)
171#define PM800_BIAS_OUT_GP2		BIT(2)
172#define PM800_BIAS_OUT_GP3		BIT(3)
173
174#define PM800_GPADC0_LOW_TH		0x20
175#define PM800_GPADC1_LOW_TH		0x21
176#define PM800_GPADC2_LOW_TH		0x22
177#define PM800_GPADC3_LOW_TH		0x23
178#define PM800_GPADC4_LOW_TH		0x24
179
180#define PM800_GPADC0_UPP_TH		0x30
181#define PM800_GPADC1_UPP_TH		0x31
182#define PM800_GPADC2_UPP_TH		0x32
183#define PM800_GPADC3_UPP_TH		0x33
184#define PM800_GPADC4_UPP_TH		0x34
185
186#define PM800_VBBAT_MEAS1		0x40
187#define PM800_VBBAT_MEAS2		0x41
188#define PM800_VBAT_MEAS1		0x42
189#define PM800_VBAT_MEAS2		0x43
190#define PM800_VSYS_MEAS1		0x44
191#define PM800_VSYS_MEAS2		0x45
192#define PM800_VCHG_MEAS1		0x46
193#define PM800_VCHG_MEAS2		0x47
194#define PM800_TINT_MEAS1		0x50
195#define PM800_TINT_MEAS2		0x51
196#define PM800_PMOD_MEAS1		0x52
197#define PM800_PMOD_MEAS2		0x53
198
199#define PM800_GPADC0_MEAS1		0x54
200#define PM800_GPADC0_MEAS2		0x55
201#define PM800_GPADC1_MEAS1		0x56
202#define PM800_GPADC1_MEAS2		0x57
203#define PM800_GPADC2_MEAS1		0x58
204#define PM800_GPADC2_MEAS2		0x59
205#define PM800_GPADC3_MEAS1		0x5A
206#define PM800_GPADC3_MEAS2		0x5B
207#define PM800_GPADC4_MEAS1		0x5C
208#define PM800_GPADC4_MEAS2		0x5D
209
210#define PM800_GPADC4_AVG1		0xA8
211#define PM800_GPADC4_AVG2		0xA9
212
213/* 88PM805 Registers */
214#define PM805_MAIN_POWERUP		(0x01)
215#define PM805_INT_STATUS0		(0x02)	/* for ena/dis all interrupts */
216
217#define PM805_STATUS0_INT_CLEAR		(1 << 0)
218#define PM805_STATUS0_INV_INT		(1 << 1)
219#define PM800_STATUS0_INT_MASK		(1 << 2)
220
221#define PM805_INT_STATUS1		(0x03)
222
223#define PM805_INT1_HP1_SHRT		BIT(0)
224#define PM805_INT1_HP2_SHRT		BIT(1)
225#define PM805_INT1_MIC_CONFLICT		BIT(2)
226#define PM805_INT1_CLIP_FAULT		BIT(3)
227#define PM805_INT1_LDO_OFF		BIT(4)
228#define PM805_INT1_SRC_DPLL_LOCK	BIT(5)
229
230#define PM805_INT_STATUS2		(0x04)
231
232#define PM805_INT2_MIC_DET		BIT(0)
233#define PM805_INT2_SHRT_BTN_DET		BIT(1)
234#define PM805_INT2_VOLM_BTN_DET		BIT(2)
235#define PM805_INT2_VOLP_BTN_DET		BIT(3)
236#define PM805_INT2_RAW_PLL_FAULT	BIT(4)
237#define PM805_INT2_FINE_PLL_FAULT	BIT(5)
238
239#define PM805_INT_MASK1			(0x05)
240#define PM805_INT_MASK2			(0x06)
241#define PM805_SHRT_BTN_DET		BIT(1)
242
243/* number of status and int reg in a row */
244#define PM805_INT_REG_NUM		(2)
245
246#define PM805_MIC_DET1			(0x07)
247#define PM805_MIC_DET_EN_MIC_DET	BIT(0)
248#define PM805_MIC_DET2			(0x08)
249#define PM805_MIC_DET_STATUS1		(0x09)
250
251#define PM805_MIC_DET_STATUS3		(0x0A)
252#define PM805_AUTO_SEQ_STATUS1		(0x0B)
253#define PM805_AUTO_SEQ_STATUS2		(0x0C)
254
255#define PM805_ADC_SETTING1		(0x10)
256#define PM805_ADC_SETTING2		(0x11)
257#define PM805_ADC_SETTING3		(0x11)
258#define PM805_ADC_GAIN1			(0x12)
259#define PM805_ADC_GAIN2			(0x13)
260#define PM805_DMIC_SETTING		(0x15)
261#define PM805_DWS_SETTING		(0x16)
262#define PM805_MIC_CONFLICT_STS		(0x17)
263
264#define PM805_PDM_SETTING1		(0x20)
265#define PM805_PDM_SETTING2		(0x21)
266#define PM805_PDM_SETTING3		(0x22)
267#define PM805_PDM_CONTROL1		(0x23)
268#define PM805_PDM_CONTROL2		(0x24)
269#define PM805_PDM_CONTROL3		(0x25)
270
271#define PM805_HEADPHONE_SETTING		(0x26)
272#define PM805_HEADPHONE_GAIN_A2A	(0x27)
273#define PM805_HEADPHONE_SHORT_STATE	(0x28)
274#define PM805_EARPHONE_SETTING		(0x29)
275#define PM805_AUTO_SEQ_SETTING		(0x2A)
276
277struct pm80x_rtc_pdata {
278	int		vrtc;
279	int		rtc_wakeup;
280};
281
282struct pm80x_subchip {
283	struct i2c_client *power_page;	/* chip client for power page */
284	struct i2c_client *gpadc_page;	/* chip client for gpadc page */
285	struct regmap *regmap_power;
286	struct regmap *regmap_gpadc;
287	unsigned short power_page_addr;	/* power page I2C address */
288	unsigned short gpadc_page_addr;	/* gpadc page I2C address */
289};
290
291struct pm80x_chip {
292	struct pm80x_subchip *subchip;
293	struct device *dev;
294	struct i2c_client *client;
295	struct i2c_client *companion;
296	struct regmap *regmap;
297	struct regmap_irq_chip *regmap_irq_chip;
298	struct regmap_irq_chip_data *irq_data;
299	int type;
300	int irq;
301	int irq_mode;
302	unsigned long wu_flag;
303	spinlock_t lock;
304};
305
306struct pm80x_platform_data {
307	struct pm80x_rtc_pdata *rtc;
308	/*
309	 * For the regulator not defined, set regulators[not_defined] to be
310	 * NULL. num_regulators are the number of regulators supposed to be
311	 * initialized. If all regulators are not defined, set num_regulators
312	 * to be 0.
313	 */
314	struct regulator_init_data *regulators[PM800_ID_RG_MAX];
315	unsigned int num_regulators;
316	int irq_mode;		/* Clear interrupt by read/write(0/1) */
317	int batt_det;		/* enable/disable */
318	int (*plat_config)(struct pm80x_chip *chip,
319				struct pm80x_platform_data *pdata);
320};
321
322extern const struct dev_pm_ops pm80x_pm_ops;
323extern const struct regmap_config pm80x_regmap_config;
324
325static inline int pm80x_request_irq(struct pm80x_chip *pm80x, int irq,
326				     irq_handler_t handler, unsigned long flags,
327				     const char *name, void *data)
328{
329	if (!pm80x->irq_data)
330		return -EINVAL;
331	return request_threaded_irq(regmap_irq_get_virq(pm80x->irq_data, irq),
332				    NULL, handler, flags, name, data);
333}
334
335static inline void pm80x_free_irq(struct pm80x_chip *pm80x, int irq, void *data)
336{
337	if (!pm80x->irq_data)
338		return;
339	free_irq(regmap_irq_get_virq(pm80x->irq_data, irq), data);
340}
341
342#ifdef CONFIG_PM
343static inline int pm80x_dev_suspend(struct device *dev)
344{
345	struct platform_device *pdev = to_platform_device(dev);
346	struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
347	int irq = platform_get_irq(pdev, 0);
348
349	if (device_may_wakeup(dev))
350		set_bit(irq, &chip->wu_flag);
351
352	return 0;
353}
354
355static inline int pm80x_dev_resume(struct device *dev)
356{
357	struct platform_device *pdev = to_platform_device(dev);
358	struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
359	int irq = platform_get_irq(pdev, 0);
360
361	if (device_may_wakeup(dev))
362		clear_bit(irq, &chip->wu_flag);
363
364	return 0;
365}
366#endif
367
368extern int pm80x_init(struct i2c_client *client);
369extern int pm80x_deinit(void);
370#endif /* __LINUX_MFD_88PM80X_H */
371