1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef LINUX_BCMA_DRIVER_PCIE2_H_ 3#define LINUX_BCMA_DRIVER_PCIE2_H_ 4 5#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000 6#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */ 7#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */ 8#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */ 9#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010 10#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */ 11#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */ 12#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */ 13#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004 14#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008 15#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C 16#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010 17#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014 18#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018 19#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C 20#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020 21#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100 22#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104 23#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108 24#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C 25#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120 26#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124 27#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128 28#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C 29#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130 30#define BCMA_CORE_PCIE2_DATAINTF 0x0180 31#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188 32#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c 33#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190 34#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194 35#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198 36#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c 37#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */ 38#define PCIE2_LTR_ACTIVE 2 39#define PCIE2_LTR_ACTIVE_IDLE 1 40#define PCIE2_LTR_SLEEP 0 41#define PCIE2_LTR_FINAL_MASK 0x300 42#define PCIE2_LTR_FINAL_SHIFT 8 43#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4 44#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8 45#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8 46#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC 47#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200 48#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204 49#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208 50#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210 51#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214 52#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218 53#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C 54#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220 55#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224 56#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250 57#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254 58#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258 59#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C 60#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260 61#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264 62#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268 63#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C 64#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270 65#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274 66#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278 67#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C 68#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330 69#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334 70#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340 71#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344 72#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348 73#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350 74#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354 75#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358 76#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C 77#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360 78#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364 79#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370 80#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374 81#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) 82#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00 83#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04 84#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08 85#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C 86#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10 87#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14 88#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18 89#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C 90#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20 91#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24 92#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28 93#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C 94#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30 95#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34 96#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38 97#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C 98#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80 99#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88 100#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0 101#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8 102#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00 103#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04 104#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08 105#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C 106#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10 107#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14 108#define BCMA_CORE_PCIE2_OARR0 0x0D20 109#define BCMA_CORE_PCIE2_OARR1 0x0D28 110#define BCMA_CORE_PCIE2_OARR2 0x0D30 111#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40 112#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44 113#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48 114#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C 115#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50 116#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54 117#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58 118#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C 119#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00 120#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04 121#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08 122#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C 123#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10 124#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14 125#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18 126#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C 127#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20 128#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24 129#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28 130#define BCMA_CORE_PCIE2_INTR_EN 0x0F30 131#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34 132#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38 133 134/* PCIE gen2 config regs */ 135#define PCIE2_INTSTATUS 0x090 136#define PCIE2_INTMASK 0x094 137#define PCIE2_SBMBX 0x098 138 139#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */ 140 141#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4 142#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400 143#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c 144 145struct bcma_drv_pcie2 { 146 struct bcma_device *core; 147 148 u16 reqsize; 149}; 150 151#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset) 152#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset) 153#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val) 154#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val) 155 156#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set) 157#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask) 158 159#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */ 160