1/*
2 * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
3 *
4 * This code is released using a dual license strategy: BSD/GPL
5 * You can choose the licence that better fits your requirements.
6 *
7 * Released under the terms of 3-clause BSD License
8 * Released under the terms of GNU General Public License Version 2.0
9 *
10 */
11
12/* LPC18xx/43xx base clock ids */
13#define BASE_SAFE_CLK		0
14#define BASE_USB0_CLK		1
15#define BASE_PERIPH_CLK		2
16#define BASE_USB1_CLK		3
17#define BASE_CPU_CLK		4
18#define BASE_SPIFI_CLK		5
19#define BASE_SPI_CLK		6
20#define BASE_PHY_RX_CLK		7
21#define BASE_PHY_TX_CLK		8
22#define BASE_APB1_CLK		9
23#define BASE_APB3_CLK		10
24#define BASE_LCD_CLK		11
25#define BASE_ADCHS_CLK		12
26#define BASE_SDIO_CLK		13
27#define BASE_SSP0_CLK		14
28#define BASE_SSP1_CLK		15
29#define BASE_UART0_CLK		16
30#define BASE_UART1_CLK		17
31#define BASE_UART2_CLK		18
32#define BASE_UART3_CLK		19
33#define BASE_OUT_CLK		20
34#define BASE_RES1_CLK		21
35#define BASE_RES2_CLK		22
36#define BASE_RES3_CLK		23
37#define BASE_RES4_CLK		24
38#define BASE_AUDIO_CLK		25
39#define BASE_CGU_OUT0_CLK	26
40#define BASE_CGU_OUT1_CLK	27
41#define BASE_CLK_MAX		(BASE_CGU_OUT1_CLK + 1)
42