1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2015 Hisilicon Limited.
4 *
5 * Author: Bintian Wang <bintian.wang@huawei.com>
6 */
7
8#ifndef __DT_BINDINGS_CLOCK_HI6220_H
9#define __DT_BINDINGS_CLOCK_HI6220_H
10
11/* clk in Hi6220 AO (always on) controller */
12#define HI6220_NONE_CLOCK	0
13
14/* fixed rate clocks */
15#define HI6220_REF32K		1
16#define HI6220_CLK_TCXO		2
17#define HI6220_MMC1_PAD		3
18#define HI6220_MMC2_PAD		4
19#define HI6220_MMC0_PAD		5
20#define HI6220_PLL_BBP		6
21#define HI6220_PLL_GPU		7
22#define HI6220_PLL1_DDR		8
23#define HI6220_PLL_SYS		9
24#define HI6220_PLL_SYS_MEDIA	10
25#define HI6220_DDR_SRC		11
26#define HI6220_PLL_MEDIA	12
27#define HI6220_PLL_DDR		13
28
29/* fixed factor clocks */
30#define HI6220_300M		14
31#define HI6220_150M		15
32#define HI6220_PICOPHY_SRC	16
33#define HI6220_MMC0_SRC_SEL	17
34#define HI6220_MMC1_SRC_SEL	18
35#define HI6220_MMC2_SRC_SEL	19
36#define HI6220_VPU_CODEC	20
37#define HI6220_MMC0_SMP		21
38#define HI6220_MMC1_SMP		22
39#define HI6220_MMC2_SMP		23
40
41/* gate clocks */
42#define HI6220_WDT0_PCLK	24
43#define HI6220_WDT1_PCLK	25
44#define HI6220_WDT2_PCLK	26
45#define HI6220_TIMER0_PCLK	27
46#define HI6220_TIMER1_PCLK	28
47#define HI6220_TIMER2_PCLK	29
48#define HI6220_TIMER3_PCLK	30
49#define HI6220_TIMER4_PCLK	31
50#define HI6220_TIMER5_PCLK	32
51#define HI6220_TIMER6_PCLK	33
52#define HI6220_TIMER7_PCLK	34
53#define HI6220_TIMER8_PCLK	35
54#define HI6220_UART0_PCLK	36
55#define HI6220_RTC0_PCLK	37
56#define HI6220_RTC1_PCLK	38
57#define HI6220_AO_NR_CLKS	39
58
59/* clk in Hi6220 systrl */
60/* gate clock */
61#define HI6220_MMC0_CLK		1
62#define HI6220_MMC0_CIUCLK	2
63#define HI6220_MMC1_CLK		3
64#define HI6220_MMC1_CIUCLK	4
65#define HI6220_MMC2_CLK		5
66#define HI6220_MMC2_CIUCLK	6
67#define HI6220_USBOTG_HCLK	7
68#define HI6220_CLK_PICOPHY	8
69#define HI6220_HIFI		9
70#define HI6220_DACODEC_PCLK	10
71#define HI6220_EDMAC_ACLK	11
72#define HI6220_CS_ATB		12
73#define HI6220_I2C0_CLK		13
74#define HI6220_I2C1_CLK		14
75#define HI6220_I2C2_CLK		15
76#define HI6220_I2C3_CLK		16
77#define HI6220_UART1_PCLK	17
78#define HI6220_UART2_PCLK	18
79#define HI6220_UART3_PCLK	19
80#define HI6220_UART4_PCLK	20
81#define HI6220_SPI_CLK		21
82#define HI6220_TSENSOR_CLK	22
83#define HI6220_MMU_CLK		23
84#define HI6220_HIFI_SEL		24
85#define HI6220_MMC0_SYSPLL	25
86#define HI6220_MMC1_SYSPLL	26
87#define HI6220_MMC2_SYSPLL	27
88#define HI6220_MMC0_SEL		28
89#define HI6220_MMC1_SEL		29
90#define HI6220_BBPPLL_SEL	30
91#define HI6220_MEDIA_PLL_SRC	31
92#define HI6220_MMC2_SEL		32
93#define HI6220_CS_ATB_SYSPLL	33
94
95/* mux clocks */
96#define HI6220_MMC0_SRC		34
97#define HI6220_MMC0_SMP_IN	35
98#define HI6220_MMC1_SRC		36
99#define HI6220_MMC1_SMP_IN	37
100#define HI6220_MMC2_SRC		38
101#define HI6220_MMC2_SMP_IN	39
102#define HI6220_HIFI_SRC		40
103#define HI6220_UART1_SRC	41
104#define HI6220_UART2_SRC	42
105#define HI6220_UART3_SRC	43
106#define HI6220_UART4_SRC	44
107#define HI6220_MMC0_MUX0	45
108#define HI6220_MMC1_MUX0	46
109#define HI6220_MMC2_MUX0	47
110#define HI6220_MMC0_MUX1	48
111#define HI6220_MMC1_MUX1	49
112#define HI6220_MMC2_MUX1	50
113
114/* divider clocks */
115#define HI6220_CLK_BUS		51
116#define HI6220_MMC0_DIV		52
117#define HI6220_MMC1_DIV		53
118#define HI6220_MMC2_DIV		54
119#define HI6220_HIFI_DIV		55
120#define HI6220_BBPPLL0_DIV	56
121#define HI6220_CS_DAPB		57
122#define HI6220_CS_ATB_DIV	58
123
124/* gate clock */
125#define HI6220_DAPB_CLK		59
126
127#define HI6220_SYS_NR_CLKS	60
128
129/* clk in Hi6220 media controller */
130/* gate clocks */
131#define HI6220_DSI_PCLK		1
132#define HI6220_G3D_PCLK		2
133#define HI6220_ACLK_CODEC_VPU	3
134#define HI6220_ISP_SCLK		4
135#define HI6220_ADE_CORE		5
136#define HI6220_MED_MMU		6
137#define HI6220_CFG_CSI4PHY	7
138#define HI6220_CFG_CSI2PHY	8
139#define HI6220_ISP_SCLK_GATE	9
140#define HI6220_ISP_SCLK_GATE1	10
141#define HI6220_ADE_CORE_GATE	11
142#define HI6220_CODEC_VPU_GATE	12
143#define HI6220_MED_SYSPLL	13
144
145/* mux clocks */
146#define HI6220_1440_1200	14
147#define HI6220_1000_1200	15
148#define HI6220_1000_1440	16
149
150/* divider clocks */
151#define HI6220_CODEC_JPEG	17
152#define HI6220_ISP_SCLK_SRC	18
153#define HI6220_ISP_SCLK1	19
154#define HI6220_ADE_CORE_SRC	20
155#define HI6220_ADE_PIX_SRC	21
156#define HI6220_G3D_CLK		22
157#define HI6220_CODEC_VPU_SRC	23
158
159#define HI6220_MEDIA_NR_CLKS	24
160
161/* clk in Hi6220 power controller */
162/* gate clocks */
163#define HI6220_PLL_GPU_GATE	1
164#define HI6220_PLL1_DDR_GATE	2
165#define HI6220_PLL_DDR_GATE	3
166#define HI6220_PLL_MEDIA_GATE	4
167#define HI6220_PLL0_BBP_GATE	5
168
169/* divider clocks */
170#define HI6220_DDRC_SRC		6
171#define HI6220_DDRC_AXI1	7
172
173#define HI6220_POWER_NR_CLKS	8
174
175/* clk in Hi6220 acpu sctrl */
176#define HI6220_ACPU_SFT_AT_S		0
177
178#endif
179