1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Watchdog driver for Atmel AT91SAM9x processors.
4 *
5 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
6 *
7 */
8
9/*
10 * The Watchdog Timer Mode Register can be only written to once. If the
11 * timeout need to be set from Linux, be sure that the bootstrap or the
12 * bootloader doesn't write to this register.
13 */
14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/clk.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/platform_device.h>
26#include <linux/reboot.h>
27#include <linux/types.h>
28#include <linux/watchdog.h>
29#include <linux/jiffies.h>
30#include <linux/timer.h>
31#include <linux/bitops.h>
32#include <linux/uaccess.h>
33#include <linux/of.h>
34#include <linux/of_irq.h>
35
36#include "at91sam9_wdt.h"
37
38#define DRV_NAME "AT91SAM9 Watchdog"
39
40#define wdt_read(wdt, field) \
41	readl_relaxed((wdt)->base + (field))
42#define wdt_write(wtd, field, val) \
43	writel_relaxed((val), (wdt)->base + (field))
44
45/* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
46 * use this to convert a watchdog
47 * value from/to milliseconds.
48 */
49#define ticks_to_hz_rounddown(t)	((((t) + 1) * HZ) >> 8)
50#define ticks_to_hz_roundup(t)		(((((t) + 1) * HZ) + 255) >> 8)
51#define ticks_to_secs(t)		(((t) + 1) >> 8)
52#define secs_to_ticks(s)		((s) ? (((s) << 8) - 1) : 0)
53
54#define WDT_MR_RESET	0x3FFF2FFF
55
56/* Watchdog max counter value in ticks */
57#define WDT_COUNTER_MAX_TICKS	0xFFF
58
59/* Watchdog max delta/value in secs */
60#define WDT_COUNTER_MAX_SECS	ticks_to_secs(WDT_COUNTER_MAX_TICKS)
61
62/* Hardware timeout in seconds */
63#define WDT_HW_TIMEOUT 2
64
65/* Timer heartbeat (500ms) */
66#define WDT_TIMEOUT	(HZ/2)
67
68/* User land timeout */
69#define WDT_HEARTBEAT 15
70static int heartbeat;
71module_param(heartbeat, int, 0);
72MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. "
73	"(default = " __MODULE_STRING(WDT_HEARTBEAT) ")");
74
75static bool nowayout = WATCHDOG_NOWAYOUT;
76module_param(nowayout, bool, 0);
77MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
78	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
79
80#define to_wdt(wdd) container_of(wdd, struct at91wdt, wdd)
81struct at91wdt {
82	struct watchdog_device wdd;
83	void __iomem *base;
84	unsigned long next_heartbeat;	/* the next_heartbeat for the timer */
85	struct timer_list timer;	/* The timer that pings the watchdog */
86	u32 mr;
87	u32 mr_mask;
88	unsigned long heartbeat;	/* WDT heartbeat in jiffies */
89	bool nowayout;
90	unsigned int irq;
91	struct clk *sclk;
92};
93
94/* ......................................................................... */
95
96static irqreturn_t wdt_interrupt(int irq, void *dev_id)
97{
98	struct at91wdt *wdt = (struct at91wdt *)dev_id;
99
100	if (wdt_read(wdt, AT91_WDT_SR)) {
101		pr_crit("at91sam9 WDT software reset\n");
102		emergency_restart();
103		pr_crit("Reboot didn't ?????\n");
104	}
105
106	return IRQ_HANDLED;
107}
108
109/*
110 * Reload the watchdog timer.  (ie, pat the watchdog)
111 */
112static inline void at91_wdt_reset(struct at91wdt *wdt)
113{
114	wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
115}
116
117/*
118 * Timer tick
119 */
120static void at91_ping(struct timer_list *t)
121{
122	struct at91wdt *wdt = from_timer(wdt, t, timer);
123	if (time_before(jiffies, wdt->next_heartbeat) ||
124	    !watchdog_active(&wdt->wdd)) {
125		at91_wdt_reset(wdt);
126		mod_timer(&wdt->timer, jiffies + wdt->heartbeat);
127	} else {
128		pr_crit("I will reset your machine !\n");
129	}
130}
131
132static int at91_wdt_start(struct watchdog_device *wdd)
133{
134	struct at91wdt *wdt = to_wdt(wdd);
135	/* calculate when the next userspace timeout will be */
136	wdt->next_heartbeat = jiffies + wdd->timeout * HZ;
137	return 0;
138}
139
140static int at91_wdt_stop(struct watchdog_device *wdd)
141{
142	/* The watchdog timer hardware can not be stopped... */
143	return 0;
144}
145
146static int at91_wdt_set_timeout(struct watchdog_device *wdd, unsigned int new_timeout)
147{
148	wdd->timeout = new_timeout;
149	return at91_wdt_start(wdd);
150}
151
152static int at91_wdt_init(struct platform_device *pdev, struct at91wdt *wdt)
153{
154	u32 tmp;
155	u32 delta;
156	u32 value;
157	int err;
158	u32 mask = wdt->mr_mask;
159	unsigned long min_heartbeat = 1;
160	unsigned long max_heartbeat;
161	struct device *dev = &pdev->dev;
162
163	tmp = wdt_read(wdt, AT91_WDT_MR);
164	if ((tmp & mask) != (wdt->mr & mask)) {
165		if (tmp == WDT_MR_RESET) {
166			wdt_write(wdt, AT91_WDT_MR, wdt->mr);
167			tmp = wdt_read(wdt, AT91_WDT_MR);
168		}
169	}
170
171	if (tmp & AT91_WDT_WDDIS) {
172		if (wdt->mr & AT91_WDT_WDDIS)
173			return 0;
174		dev_err(dev, "watchdog is disabled\n");
175		return -EINVAL;
176	}
177
178	value = tmp & AT91_WDT_WDV;
179	delta = (tmp & AT91_WDT_WDD) >> 16;
180
181	if (delta < value)
182		min_heartbeat = ticks_to_hz_roundup(value - delta);
183
184	max_heartbeat = ticks_to_hz_rounddown(value);
185	if (!max_heartbeat) {
186		dev_err(dev,
187			"heartbeat is too small for the system to handle it correctly\n");
188		return -EINVAL;
189	}
190
191	/*
192	 * Try to reset the watchdog counter 4 or 2 times more often than
193	 * actually requested, to avoid spurious watchdog reset.
194	 * If this is not possible because of the min_heartbeat value, reset
195	 * it at the min_heartbeat period.
196	 */
197	if ((max_heartbeat / 4) >= min_heartbeat)
198		wdt->heartbeat = max_heartbeat / 4;
199	else if ((max_heartbeat / 2) >= min_heartbeat)
200		wdt->heartbeat = max_heartbeat / 2;
201	else
202		wdt->heartbeat = min_heartbeat;
203
204	if (max_heartbeat < min_heartbeat + 4)
205		dev_warn(dev,
206			 "min heartbeat and max heartbeat might be too close for the system to handle it correctly\n");
207
208	if ((tmp & AT91_WDT_WDFIEN) && wdt->irq) {
209		err = devm_request_irq(dev, wdt->irq, wdt_interrupt,
210				       IRQF_SHARED | IRQF_IRQPOLL | IRQF_NO_SUSPEND,
211				       pdev->name, wdt);
212		if (err)
213			return err;
214	}
215
216	if ((tmp & wdt->mr_mask) != (wdt->mr & wdt->mr_mask))
217		dev_warn(dev,
218			 "watchdog already configured differently (mr = %x expecting %x)\n",
219			 tmp & wdt->mr_mask, wdt->mr & wdt->mr_mask);
220
221	timer_setup(&wdt->timer, at91_ping, 0);
222
223	/*
224	 * Use min_heartbeat the first time to avoid spurious watchdog reset:
225	 * we don't know for how long the watchdog counter is running, and
226	 *  - resetting it right now might trigger a watchdog fault reset
227	 *  - waiting for heartbeat time might lead to a watchdog timeout
228	 *    reset
229	 */
230	mod_timer(&wdt->timer, jiffies + min_heartbeat);
231
232	/* Try to set timeout from device tree first */
233	if (watchdog_init_timeout(&wdt->wdd, 0, dev))
234		watchdog_init_timeout(&wdt->wdd, heartbeat, dev);
235	watchdog_set_nowayout(&wdt->wdd, wdt->nowayout);
236	err = watchdog_register_device(&wdt->wdd);
237	if (err)
238		goto out_stop_timer;
239
240	wdt->next_heartbeat = jiffies + wdt->wdd.timeout * HZ;
241
242	return 0;
243
244out_stop_timer:
245	del_timer(&wdt->timer);
246	return err;
247}
248
249/* ......................................................................... */
250
251static const struct watchdog_info at91_wdt_info = {
252	.identity	= DRV_NAME,
253	.options	= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
254						WDIOF_MAGICCLOSE,
255};
256
257static const struct watchdog_ops at91_wdt_ops = {
258	.owner =	THIS_MODULE,
259	.start =	at91_wdt_start,
260	.stop =		at91_wdt_stop,
261	.set_timeout =	at91_wdt_set_timeout,
262};
263
264#if defined(CONFIG_OF)
265static int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt)
266{
267	u32 min = 0;
268	u32 max = WDT_COUNTER_MAX_SECS;
269	const char *tmp;
270
271	/* Get the interrupts property */
272	wdt->irq = irq_of_parse_and_map(np, 0);
273	if (!wdt->irq)
274		dev_warn(wdt->wdd.parent, "failed to get IRQ from DT\n");
275
276	if (!of_property_read_u32_index(np, "atmel,max-heartbeat-sec", 0,
277					&max)) {
278		if (!max || max > WDT_COUNTER_MAX_SECS)
279			max = WDT_COUNTER_MAX_SECS;
280
281		if (!of_property_read_u32_index(np, "atmel,min-heartbeat-sec",
282						0, &min)) {
283			if (min >= max)
284				min = max - 1;
285		}
286	}
287
288	min = secs_to_ticks(min);
289	max = secs_to_ticks(max);
290
291	wdt->mr_mask = 0x3FFFFFFF;
292	wdt->mr = 0;
293	if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
294	    !strcmp(tmp, "software")) {
295		wdt->mr |= AT91_WDT_WDFIEN;
296		wdt->mr_mask &= ~AT91_WDT_WDRPROC;
297	} else {
298		wdt->mr |= AT91_WDT_WDRSTEN;
299	}
300
301	if (!of_property_read_string(np, "atmel,reset-type", &tmp) &&
302	    !strcmp(tmp, "proc"))
303		wdt->mr |= AT91_WDT_WDRPROC;
304
305	if (of_property_read_bool(np, "atmel,disable")) {
306		wdt->mr |= AT91_WDT_WDDIS;
307		wdt->mr_mask &= AT91_WDT_WDDIS;
308	}
309
310	if (of_property_read_bool(np, "atmel,idle-halt"))
311		wdt->mr |= AT91_WDT_WDIDLEHLT;
312
313	if (of_property_read_bool(np, "atmel,dbg-halt"))
314		wdt->mr |= AT91_WDT_WDDBGHLT;
315
316	wdt->mr |= max | ((max - min) << 16);
317
318	return 0;
319}
320#else
321static inline int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt)
322{
323	return 0;
324}
325#endif
326
327static int at91wdt_probe(struct platform_device *pdev)
328{
329	int err;
330	struct at91wdt *wdt;
331
332	wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
333	if (!wdt)
334		return -ENOMEM;
335
336	wdt->mr = (WDT_HW_TIMEOUT * 256) | AT91_WDT_WDRSTEN | AT91_WDT_WDD |
337		  AT91_WDT_WDDBGHLT | AT91_WDT_WDIDLEHLT;
338	wdt->mr_mask = 0x3FFFFFFF;
339	wdt->nowayout = nowayout;
340	wdt->wdd.parent = &pdev->dev;
341	wdt->wdd.info = &at91_wdt_info;
342	wdt->wdd.ops = &at91_wdt_ops;
343	wdt->wdd.timeout = WDT_HEARTBEAT;
344	wdt->wdd.min_timeout = 1;
345	wdt->wdd.max_timeout = 0xFFFF;
346
347	wdt->base = devm_platform_ioremap_resource(pdev, 0);
348	if (IS_ERR(wdt->base))
349		return PTR_ERR(wdt->base);
350
351	wdt->sclk = devm_clk_get_enabled(&pdev->dev, NULL);
352	if (IS_ERR(wdt->sclk)) {
353		dev_err(&pdev->dev, "Could not enable slow clock\n");
354		return PTR_ERR(wdt->sclk);
355	}
356
357	if (pdev->dev.of_node) {
358		err = of_at91wdt_init(pdev->dev.of_node, wdt);
359		if (err)
360			return err;
361	}
362
363	err = at91_wdt_init(pdev, wdt);
364	if (err)
365		return err;
366
367	platform_set_drvdata(pdev, wdt);
368
369	pr_info("enabled (heartbeat=%d sec, nowayout=%d)\n",
370		wdt->wdd.timeout, wdt->nowayout);
371
372	return 0;
373}
374
375static void at91wdt_remove(struct platform_device *pdev)
376{
377	struct at91wdt *wdt = platform_get_drvdata(pdev);
378	watchdog_unregister_device(&wdt->wdd);
379
380	pr_warn("I quit now, hardware will probably reboot!\n");
381	del_timer(&wdt->timer);
382}
383
384#if defined(CONFIG_OF)
385static const struct of_device_id at91_wdt_dt_ids[] = {
386	{ .compatible = "atmel,at91sam9260-wdt" },
387	{ /* sentinel */ }
388};
389
390MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids);
391#endif
392
393static struct platform_driver at91wdt_driver = {
394	.probe		= at91wdt_probe,
395	.remove_new	= at91wdt_remove,
396	.driver		= {
397		.name	= "at91_wdt",
398		.of_match_table = of_match_ptr(at91_wdt_dt_ids),
399	},
400};
401module_platform_driver(at91wdt_driver);
402
403MODULE_AUTHOR("Renaud CERRATO <r.cerrato@til-technologies.fr>");
404MODULE_DESCRIPTION("Watchdog driver for Atmel AT91SAM9x processors");
405MODULE_LICENSE("GPL");
406