1/* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D fb driver for sparc64 systems
2 *
3 * License: GPL
4 *
5 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
6 */
7
8#include <linux/aperture.h>
9#include <linux/kernel.h>
10#include <linux/fb.h>
11#include <linux/pci.h>
12#include <linux/init.h>
13#include <linux/of.h>
14
15#include <asm/io.h>
16
17/* XXX This device has a 'dev-comm' property which apparently is
18 * XXX a pointer into the openfirmware's address space which is
19 * XXX a shared area the kernel driver can use to keep OBP
20 * XXX informed about the current resolution setting.  The idea
21 * XXX is that the kernel can change resolutions, and as long
22 * XXX as the values in the 'dev-comm' area are accurate then
23 * XXX OBP can still render text properly to the console.
24 * XXX
25 * XXX I'm still working out the layout of this and whether there
26 * XXX are any signatures we need to look for etc.
27 */
28struct e3d_info {
29	struct fb_info		*info;
30	struct pci_dev		*pdev;
31
32	spinlock_t		lock;
33
34	char __iomem		*fb_base;
35	unsigned long		fb_base_phys;
36
37	unsigned long		fb8_buf_diff;
38	unsigned long		regs_base_phys;
39
40	void __iomem		*ramdac;
41
42	struct device_node	*of_node;
43
44	unsigned int		width;
45	unsigned int		height;
46	unsigned int		depth;
47	unsigned int		fb_size;
48
49	u32			fb_base_reg;
50	u32			fb8_0_off;
51	u32			fb8_1_off;
52
53	u32			pseudo_palette[16];
54};
55
56static int e3d_get_props(struct e3d_info *ep)
57{
58	ep->width = of_getintprop_default(ep->of_node, "width", 0);
59	ep->height = of_getintprop_default(ep->of_node, "height", 0);
60	ep->depth = of_getintprop_default(ep->of_node, "depth", 8);
61
62	if (!ep->width || !ep->height) {
63		printk(KERN_ERR "e3d: Critical properties missing for %s\n",
64		       pci_name(ep->pdev));
65		return -EINVAL;
66	}
67
68	return 0;
69}
70
71/* My XVR-500 comes up, at 1280x768 and a FB base register value of
72 * 0x04000000, the following video layout register values:
73 *
74 * RAMDAC_VID_WH	0x03ff04ff
75 * RAMDAC_VID_CFG	0x1a0b0088
76 * RAMDAC_VID_32FB_0	0x04000000
77 * RAMDAC_VID_32FB_1	0x04800000
78 * RAMDAC_VID_8FB_0	0x05000000
79 * RAMDAC_VID_8FB_1	0x05200000
80 * RAMDAC_VID_XXXFB	0x05400000
81 * RAMDAC_VID_YYYFB	0x05c00000
82 * RAMDAC_VID_ZZZFB	0x05e00000
83 */
84/* Video layout registers */
85#define RAMDAC_VID_WH		0x00000070UL /* (height-1)<<16 | (width-1) */
86#define RAMDAC_VID_CFG		0x00000074UL /* 0x1a000088|(linesz_log2<<16) */
87#define RAMDAC_VID_32FB_0	0x00000078UL /* PCI base 32bpp FB buffer 0 */
88#define RAMDAC_VID_32FB_1	0x0000007cUL /* PCI base 32bpp FB buffer 1 */
89#define RAMDAC_VID_8FB_0	0x00000080UL /* PCI base 8bpp FB buffer 0 */
90#define RAMDAC_VID_8FB_1	0x00000084UL /* PCI base 8bpp FB buffer 1 */
91#define RAMDAC_VID_XXXFB	0x00000088UL /* PCI base of XXX FB */
92#define RAMDAC_VID_YYYFB	0x0000008cUL /* PCI base of YYY FB */
93#define RAMDAC_VID_ZZZFB	0x00000090UL /* PCI base of ZZZ FB */
94
95/* CLUT registers */
96#define RAMDAC_INDEX		0x000000bcUL
97#define RAMDAC_DATA		0x000000c0UL
98
99static void e3d_clut_write(struct e3d_info *ep, int index, u32 val)
100{
101	void __iomem *ramdac = ep->ramdac;
102	unsigned long flags;
103
104	spin_lock_irqsave(&ep->lock, flags);
105
106	writel(index, ramdac + RAMDAC_INDEX);
107	writel(val, ramdac + RAMDAC_DATA);
108
109	spin_unlock_irqrestore(&ep->lock, flags);
110}
111
112static int e3d_setcolreg(unsigned regno,
113			 unsigned red, unsigned green, unsigned blue,
114			 unsigned transp, struct fb_info *info)
115{
116	struct e3d_info *ep = info->par;
117	u32 red_8, green_8, blue_8;
118	u32 red_10, green_10, blue_10;
119	u32 value;
120
121	if (regno >= 256)
122		return 1;
123
124	red_8 = red >> 8;
125	green_8 = green >> 8;
126	blue_8 = blue >> 8;
127
128	value = (blue_8 << 24) | (green_8 << 16) | (red_8 << 8);
129
130	if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16)
131		((u32 *)info->pseudo_palette)[regno] = value;
132
133
134	red_10 = red >> 6;
135	green_10 = green >> 6;
136	blue_10 = blue >> 6;
137
138	value = (blue_10 << 20) | (green_10 << 10) | (red_10 << 0);
139	e3d_clut_write(ep, regno, value);
140
141	return 0;
142}
143
144/* XXX This is a bit of a hack.  I can't figure out exactly how the
145 * XXX two 8bpp areas of the framebuffer work.  I imagine there is
146 * XXX a WID attribute somewhere else in the framebuffer which tells
147 * XXX the ramdac which of the two 8bpp framebuffer regions to take
148 * XXX the pixel from.  So, for now, render into both regions to make
149 * XXX sure the pixel shows up.
150 */
151static void e3d_imageblit(struct fb_info *info, const struct fb_image *image)
152{
153	struct e3d_info *ep = info->par;
154	unsigned long flags;
155
156	spin_lock_irqsave(&ep->lock, flags);
157	cfb_imageblit(info, image);
158	info->screen_base += ep->fb8_buf_diff;
159	cfb_imageblit(info, image);
160	info->screen_base -= ep->fb8_buf_diff;
161	spin_unlock_irqrestore(&ep->lock, flags);
162}
163
164static void e3d_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
165{
166	struct e3d_info *ep = info->par;
167	unsigned long flags;
168
169	spin_lock_irqsave(&ep->lock, flags);
170	cfb_fillrect(info, rect);
171	info->screen_base += ep->fb8_buf_diff;
172	cfb_fillrect(info, rect);
173	info->screen_base -= ep->fb8_buf_diff;
174	spin_unlock_irqrestore(&ep->lock, flags);
175}
176
177static void e3d_copyarea(struct fb_info *info, const struct fb_copyarea *area)
178{
179	struct e3d_info *ep = info->par;
180	unsigned long flags;
181
182	spin_lock_irqsave(&ep->lock, flags);
183	cfb_copyarea(info, area);
184	info->screen_base += ep->fb8_buf_diff;
185	cfb_copyarea(info, area);
186	info->screen_base -= ep->fb8_buf_diff;
187	spin_unlock_irqrestore(&ep->lock, flags);
188}
189
190static const struct fb_ops e3d_ops = {
191	.owner			= THIS_MODULE,
192	__FB_DEFAULT_IOMEM_OPS_RDWR,
193	.fb_setcolreg		= e3d_setcolreg,
194	.fb_fillrect		= e3d_fillrect,
195	.fb_copyarea		= e3d_copyarea,
196	.fb_imageblit		= e3d_imageblit,
197	__FB_DEFAULT_IOMEM_OPS_MMAP,
198};
199
200static int e3d_set_fbinfo(struct e3d_info *ep)
201{
202	struct fb_info *info = ep->info;
203	struct fb_var_screeninfo *var = &info->var;
204
205	info->fbops = &e3d_ops;
206	info->screen_base = ep->fb_base;
207	info->screen_size = ep->fb_size;
208
209	info->pseudo_palette = ep->pseudo_palette;
210
211	/* Fill fix common fields */
212	strscpy(info->fix.id, "e3d", sizeof(info->fix.id));
213        info->fix.smem_start = ep->fb_base_phys;
214        info->fix.smem_len = ep->fb_size;
215        info->fix.type = FB_TYPE_PACKED_PIXELS;
216	if (ep->depth == 32 || ep->depth == 24)
217		info->fix.visual = FB_VISUAL_TRUECOLOR;
218	else
219		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
220
221	var->xres = ep->width;
222	var->yres = ep->height;
223	var->xres_virtual = var->xres;
224	var->yres_virtual = var->yres;
225	var->bits_per_pixel = ep->depth;
226
227	var->red.offset = 8;
228	var->red.length = 8;
229	var->green.offset = 16;
230	var->green.length = 8;
231	var->blue.offset = 24;
232	var->blue.length = 8;
233	var->transp.offset = 0;
234	var->transp.length = 0;
235
236	if (fb_alloc_cmap(&info->cmap, 256, 0)) {
237		printk(KERN_ERR "e3d: Cannot allocate color map.\n");
238		return -ENOMEM;
239	}
240
241        return 0;
242}
243
244static int e3d_pci_register(struct pci_dev *pdev,
245			    const struct pci_device_id *ent)
246{
247	struct device_node *of_node;
248	const char *device_type;
249	struct fb_info *info;
250	struct e3d_info *ep;
251	unsigned int line_length;
252	int err;
253
254	err = aperture_remove_conflicting_pci_devices(pdev, "e3dfb");
255	if (err)
256		return err;
257
258	of_node = pci_device_to_OF_node(pdev);
259	if (!of_node) {
260		printk(KERN_ERR "e3d: Cannot find OF node of %s\n",
261		       pci_name(pdev));
262		return -ENODEV;
263	}
264
265	device_type = of_get_property(of_node, "device_type", NULL);
266	if (!device_type) {
267		printk(KERN_INFO "e3d: Ignoring secondary output device "
268		       "at %s\n", pci_name(pdev));
269		return -ENODEV;
270	}
271
272	err = pci_enable_device(pdev);
273	if (err < 0) {
274		printk(KERN_ERR "e3d: Cannot enable PCI device %s\n",
275		       pci_name(pdev));
276		goto err_out;
277	}
278
279	info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev);
280	if (!info) {
281		err = -ENOMEM;
282		goto err_disable;
283	}
284
285	ep = info->par;
286	ep->info = info;
287	ep->pdev = pdev;
288	spin_lock_init(&ep->lock);
289	ep->of_node = of_node;
290
291	/* Read the PCI base register of the frame buffer, which we
292	 * need in order to interpret the RAMDAC_VID_*FB* values in
293	 * the ramdac correctly.
294	 */
295	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
296			      &ep->fb_base_reg);
297	ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK;
298
299	ep->regs_base_phys = pci_resource_start (pdev, 1);
300	err = pci_request_region(pdev, 1, "e3d regs");
301	if (err < 0) {
302		printk("e3d: Cannot request region 1 for %s\n",
303		       pci_name(pdev));
304		goto err_release_fb;
305	}
306	ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000);
307	if (!ep->ramdac) {
308		err = -ENOMEM;
309		goto err_release_pci1;
310	}
311
312	ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0);
313	ep->fb8_0_off -= ep->fb_base_reg;
314
315	ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1);
316	ep->fb8_1_off -= ep->fb_base_reg;
317
318	ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off;
319
320	ep->fb_base_phys = pci_resource_start (pdev, 0);
321	ep->fb_base_phys += ep->fb8_0_off;
322
323	err = pci_request_region(pdev, 0, "e3d framebuffer");
324	if (err < 0) {
325		printk("e3d: Cannot request region 0 for %s\n",
326		       pci_name(pdev));
327		goto err_unmap_ramdac;
328	}
329
330	err = e3d_get_props(ep);
331	if (err)
332		goto err_release_pci0;
333
334	line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff;
335	line_length = 1 << line_length;
336
337	switch (ep->depth) {
338	case 8:
339		info->fix.line_length = line_length;
340		break;
341	case 16:
342		info->fix.line_length = line_length * 2;
343		break;
344	case 24:
345		info->fix.line_length = line_length * 3;
346		break;
347	case 32:
348		info->fix.line_length = line_length * 4;
349		break;
350	}
351	ep->fb_size = info->fix.line_length * ep->height;
352
353	ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size);
354	if (!ep->fb_base) {
355		err = -ENOMEM;
356		goto err_release_pci0;
357	}
358
359	err = e3d_set_fbinfo(ep);
360	if (err)
361		goto err_unmap_fb;
362
363	pci_set_drvdata(pdev, info);
364
365	printk("e3d: Found device at %s\n", pci_name(pdev));
366
367	err = register_framebuffer(info);
368	if (err < 0) {
369		printk(KERN_ERR "e3d: Could not register framebuffer %s\n",
370		       pci_name(pdev));
371		goto err_free_cmap;
372	}
373
374	return 0;
375
376err_free_cmap:
377	fb_dealloc_cmap(&info->cmap);
378
379err_unmap_fb:
380	iounmap(ep->fb_base);
381
382err_release_pci0:
383	pci_release_region(pdev, 0);
384
385err_unmap_ramdac:
386	iounmap(ep->ramdac);
387
388err_release_pci1:
389	pci_release_region(pdev, 1);
390
391err_release_fb:
392        framebuffer_release(info);
393
394err_disable:
395	pci_disable_device(pdev);
396
397err_out:
398	return err;
399}
400
401static const struct pci_device_id e3d_pci_table[] = {
402	{	PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a0),	},
403	{	PCI_DEVICE(0x1091, 0x7a0),			},
404	{	PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a2),	},
405	{	.vendor = PCI_VENDOR_ID_3DLABS,
406		.device = PCI_ANY_ID,
407		.subvendor = PCI_VENDOR_ID_3DLABS,
408		.subdevice = 0x0108,
409	},
410	{	.vendor = PCI_VENDOR_ID_3DLABS,
411		.device = PCI_ANY_ID,
412		.subvendor = PCI_VENDOR_ID_3DLABS,
413		.subdevice = 0x0140,
414	},
415	{	.vendor = PCI_VENDOR_ID_3DLABS,
416		.device = PCI_ANY_ID,
417		.subvendor = PCI_VENDOR_ID_3DLABS,
418		.subdevice = 0x1024,
419	},
420	{ 0, }
421};
422
423static struct pci_driver e3d_driver = {
424	.driver = {
425		.suppress_bind_attrs = true,
426	},
427	.name		= "e3d",
428	.id_table	= e3d_pci_table,
429	.probe		= e3d_pci_register,
430};
431
432static int __init e3d_init(void)
433{
434	if (fb_modesetting_disabled("e3d"))
435		return -ENODEV;
436
437	if (fb_get_options("e3d", NULL))
438		return -ENODEV;
439
440	return pci_register_driver(&e3d_driver);
441}
442device_initcall(e3d_init);
443