1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * HDMI driver definition for TI OMAP5 processors. 4 * 5 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#ifndef _HDMI5_CORE_H_ 9#define _HDMI5_CORE_H_ 10 11#include "hdmi.h" 12 13/* HDMI IP Core System */ 14 15/* HDMI Identification */ 16#define HDMI_CORE_DESIGN_ID 0x00000 17#define HDMI_CORE_REVISION_ID 0x00004 18#define HDMI_CORE_PRODUCT_ID0 0x00008 19#define HDMI_CORE_PRODUCT_ID1 0x0000C 20#define HDMI_CORE_CONFIG0_ID 0x00010 21#define HDMI_CORE_CONFIG1_ID 0x00014 22#define HDMI_CORE_CONFIG2_ID 0x00018 23#define HDMI_CORE_CONFIG3_ID 0x0001C 24 25/* HDMI Interrupt */ 26#define HDMI_CORE_IH_FC_STAT0 0x00400 27#define HDMI_CORE_IH_FC_STAT1 0x00404 28#define HDMI_CORE_IH_FC_STAT2 0x00408 29#define HDMI_CORE_IH_AS_STAT0 0x0040C 30#define HDMI_CORE_IH_PHY_STAT0 0x00410 31#define HDMI_CORE_IH_I2CM_STAT0 0x00414 32#define HDMI_CORE_IH_CEC_STAT0 0x00418 33#define HDMI_CORE_IH_VP_STAT0 0x0041C 34#define HDMI_CORE_IH_I2CMPHY_STAT0 0x00420 35#define HDMI_CORE_IH_MUTE 0x007FC 36 37/* HDMI Video Sampler */ 38#define HDMI_CORE_TX_INVID0 0x00800 39#define HDMI_CORE_TX_INSTUFFING 0x00804 40#define HDMI_CORE_TX_RGYDATA0 0x00808 41#define HDMI_CORE_TX_RGYDATA1 0x0080C 42#define HDMI_CORE_TX_RCRDATA0 0x00810 43#define HDMI_CORE_TX_RCRDATA1 0x00814 44#define HDMI_CORE_TX_BCBDATA0 0x00818 45#define HDMI_CORE_TX_BCBDATA1 0x0081C 46 47/* HDMI Video Packetizer */ 48#define HDMI_CORE_VP_STATUS 0x02000 49#define HDMI_CORE_VP_PR_CD 0x02004 50#define HDMI_CORE_VP_STUFF 0x02008 51#define HDMI_CORE_VP_REMAP 0x0200C 52#define HDMI_CORE_VP_CONF 0x02010 53#define HDMI_CORE_VP_STAT 0x02014 54#define HDMI_CORE_VP_INT 0x02018 55#define HDMI_CORE_VP_MASK 0x0201C 56#define HDMI_CORE_VP_POL 0x02020 57 58/* Frame Composer */ 59#define HDMI_CORE_FC_INVIDCONF 0x04000 60#define HDMI_CORE_FC_INHACTIV0 0x04004 61#define HDMI_CORE_FC_INHACTIV1 0x04008 62#define HDMI_CORE_FC_INHBLANK0 0x0400C 63#define HDMI_CORE_FC_INHBLANK1 0x04010 64#define HDMI_CORE_FC_INVACTIV0 0x04014 65#define HDMI_CORE_FC_INVACTIV1 0x04018 66#define HDMI_CORE_FC_INVBLANK 0x0401C 67#define HDMI_CORE_FC_HSYNCINDELAY0 0x04020 68#define HDMI_CORE_FC_HSYNCINDELAY1 0x04024 69#define HDMI_CORE_FC_HSYNCINWIDTH0 0x04028 70#define HDMI_CORE_FC_HSYNCINWIDTH1 0x0402C 71#define HDMI_CORE_FC_VSYNCINDELAY 0x04030 72#define HDMI_CORE_FC_VSYNCINWIDTH 0x04034 73#define HDMI_CORE_FC_INFREQ0 0x04038 74#define HDMI_CORE_FC_INFREQ1 0x0403C 75#define HDMI_CORE_FC_INFREQ2 0x04040 76#define HDMI_CORE_FC_CTRLDUR 0x04044 77#define HDMI_CORE_FC_EXCTRLDUR 0x04048 78#define HDMI_CORE_FC_EXCTRLSPAC 0x0404C 79#define HDMI_CORE_FC_CH0PREAM 0x04050 80#define HDMI_CORE_FC_CH1PREAM 0x04054 81#define HDMI_CORE_FC_CH2PREAM 0x04058 82#define HDMI_CORE_FC_AVICONF3 0x0405C 83#define HDMI_CORE_FC_GCP 0x04060 84#define HDMI_CORE_FC_AVICONF0 0x04064 85#define HDMI_CORE_FC_AVICONF1 0x04068 86#define HDMI_CORE_FC_AVICONF2 0x0406C 87#define HDMI_CORE_FC_AVIVID 0x04070 88#define HDMI_CORE_FC_AVIETB0 0x04074 89#define HDMI_CORE_FC_AVIETB1 0x04078 90#define HDMI_CORE_FC_AVISBB0 0x0407C 91#define HDMI_CORE_FC_AVISBB1 0x04080 92#define HDMI_CORE_FC_AVIELB0 0x04084 93#define HDMI_CORE_FC_AVIELB1 0x04088 94#define HDMI_CORE_FC_AVISRB0 0x0408C 95#define HDMI_CORE_FC_AVISRB1 0x04090 96#define HDMI_CORE_FC_AUDICONF0 0x04094 97#define HDMI_CORE_FC_AUDICONF1 0x04098 98#define HDMI_CORE_FC_AUDICONF2 0x0409C 99#define HDMI_CORE_FC_AUDICONF3 0x040A0 100#define HDMI_CORE_FC_VSDIEEEID0 0x040A4 101#define HDMI_CORE_FC_VSDSIZE 0x040A8 102#define HDMI_CORE_FC_VSDIEEEID1 0x040C0 103#define HDMI_CORE_FC_VSDIEEEID2 0x040C4 104#define HDMI_CORE_FC_VSDPAYLOAD(n) (n * 4 + 0x040C8) 105#define HDMI_CORE_FC_SPDVENDORNAME(n) (n * 4 + 0x04128) 106#define HDMI_CORE_FC_SPDPRODUCTNAME(n) (n * 4 + 0x04148) 107#define HDMI_CORE_FC_SPDDEVICEINF 0x04188 108#define HDMI_CORE_FC_AUDSCONF 0x0418C 109#define HDMI_CORE_FC_AUDSSTAT 0x04190 110#define HDMI_CORE_FC_AUDSV 0x04194 111#define HDMI_CORE_FC_AUDSU 0x04198 112#define HDMI_CORE_FC_AUDSCHNLS(n) (n * 4 + 0x0419C) 113#define HDMI_CORE_FC_CTRLQHIGH 0x041CC 114#define HDMI_CORE_FC_CTRLQLOW 0x041D0 115#define HDMI_CORE_FC_ACP0 0x041D4 116#define HDMI_CORE_FC_ACP(n) ((16-n) * 4 + 0x04208) 117#define HDMI_CORE_FC_ISCR1_0 0x04248 118#define HDMI_CORE_FC_ISCR1(n) ((16-n) * 4 + 0x0424C) 119#define HDMI_CORE_FC_ISCR2(n) ((15-n) * 4 + 0x0428C) 120#define HDMI_CORE_FC_DATAUTO0 0x042CC 121#define HDMI_CORE_FC_DATAUTO1 0x042D0 122#define HDMI_CORE_FC_DATAUTO2 0x042D4 123#define HDMI_CORE_FC_DATMAN 0x042D8 124#define HDMI_CORE_FC_DATAUTO3 0x042DC 125#define HDMI_CORE_FC_RDRB(n) (n * 4 + 0x042E0) 126#define HDMI_CORE_FC_STAT0 0x04340 127#define HDMI_CORE_FC_INT0 0x04344 128#define HDMI_CORE_FC_MASK0 0x04348 129#define HDMI_CORE_FC_POL0 0x0434C 130#define HDMI_CORE_FC_STAT1 0x04350 131#define HDMI_CORE_FC_INT1 0x04354 132#define HDMI_CORE_FC_MASK1 0x04358 133#define HDMI_CORE_FC_POL1 0x0435C 134#define HDMI_CORE_FC_STAT2 0x04360 135#define HDMI_CORE_FC_INT2 0x04364 136#define HDMI_CORE_FC_MASK2 0x04368 137#define HDMI_CORE_FC_POL2 0x0436C 138#define HDMI_CORE_FC_PRCONF 0x04380 139#define HDMI_CORE_FC_GMD_STAT 0x04400 140#define HDMI_CORE_FC_GMD_EN 0x04404 141#define HDMI_CORE_FC_GMD_UP 0x04408 142#define HDMI_CORE_FC_GMD_CONF 0x0440C 143#define HDMI_CORE_FC_GMD_HB 0x04410 144#define HDMI_CORE_FC_GMD_PB(n) (n * 4 + 0x04414) 145#define HDMI_CORE_FC_DBGFORCE 0x04800 146#define HDMI_CORE_FC_DBGAUD0CH0 0x04804 147#define HDMI_CORE_FC_DBGAUD1CH0 0x04808 148#define HDMI_CORE_FC_DBGAUD2CH0 0x0480C 149#define HDMI_CORE_FC_DBGAUD0CH1 0x04810 150#define HDMI_CORE_FC_DBGAUD1CH1 0x04814 151#define HDMI_CORE_FC_DBGAUD2CH1 0x04818 152#define HDMI_CORE_FC_DBGAUD0CH2 0x0481C 153#define HDMI_CORE_FC_DBGAUD1CH2 0x04820 154#define HDMI_CORE_FC_DBGAUD2CH2 0x04824 155#define HDMI_CORE_FC_DBGAUD0CH3 0x04828 156#define HDMI_CORE_FC_DBGAUD1CH3 0x0482C 157#define HDMI_CORE_FC_DBGAUD2CH3 0x04830 158#define HDMI_CORE_FC_DBGAUD0CH4 0x04834 159#define HDMI_CORE_FC_DBGAUD1CH4 0x04838 160#define HDMI_CORE_FC_DBGAUD2CH4 0x0483C 161#define HDMI_CORE_FC_DBGAUD0CH5 0x04840 162#define HDMI_CORE_FC_DBGAUD1CH5 0x04844 163#define HDMI_CORE_FC_DBGAUD2CH5 0x04848 164#define HDMI_CORE_FC_DBGAUD0CH6 0x0484C 165#define HDMI_CORE_FC_DBGAUD1CH6 0x04850 166#define HDMI_CORE_FC_DBGAUD2CH6 0x04854 167#define HDMI_CORE_FC_DBGAUD0CH7 0x04858 168#define HDMI_CORE_FC_DBGAUD1CH7 0x0485C 169#define HDMI_CORE_FC_DBGAUD2CH7 0x04860 170#define HDMI_CORE_FC_DBGTMDS0 0x04864 171#define HDMI_CORE_FC_DBGTMDS1 0x04868 172#define HDMI_CORE_FC_DBGTMDS2 0x0486C 173#define HDMI_CORE_PHY_MASK0 0x0C018 174#define HDMI_CORE_PHY_I2CM_INT_ADDR 0x0C09C 175#define HDMI_CORE_PHY_I2CM_CTLINT_ADDR 0x0C0A0 176 177/* HDMI Audio */ 178#define HDMI_CORE_AUD_CONF0 0x0C400 179#define HDMI_CORE_AUD_CONF1 0x0C404 180#define HDMI_CORE_AUD_INT 0x0C408 181#define HDMI_CORE_AUD_N1 0x0C800 182#define HDMI_CORE_AUD_N2 0x0C804 183#define HDMI_CORE_AUD_N3 0x0C808 184#define HDMI_CORE_AUD_CTS1 0x0C80C 185#define HDMI_CORE_AUD_CTS2 0x0C810 186#define HDMI_CORE_AUD_CTS3 0x0C814 187#define HDMI_CORE_AUD_INCLKFS 0x0C818 188#define HDMI_CORE_AUD_CC08 0x0CC08 189#define HDMI_CORE_AUD_GP_CONF0 0x0D400 190#define HDMI_CORE_AUD_GP_CONF1 0x0D404 191#define HDMI_CORE_AUD_GP_CONF2 0x0D408 192#define HDMI_CORE_AUD_D010 0x0D010 193#define HDMI_CORE_AUD_GP_STAT 0x0D40C 194#define HDMI_CORE_AUD_GP_INT 0x0D410 195#define HDMI_CORE_AUD_GP_POL 0x0D414 196#define HDMI_CORE_AUD_GP_MASK 0x0D418 197 198/* HDMI Main Controller */ 199#define HDMI_CORE_MC_CLKDIS 0x10004 200#define HDMI_CORE_MC_SWRSTZREQ 0x10008 201#define HDMI_CORE_MC_FLOWCTRL 0x10010 202#define HDMI_CORE_MC_PHYRSTZ 0x10014 203#define HDMI_CORE_MC_LOCKONCLOCK 0x10018 204 205/* HDMI COLOR SPACE CONVERTER */ 206#define HDMI_CORE_CSC_CFG 0x10400 207#define HDMI_CORE_CSC_SCALE 0x10404 208#define HDMI_CORE_CSC_COEF_A1_MSB 0x10408 209#define HDMI_CORE_CSC_COEF_A1_LSB 0x1040C 210#define HDMI_CORE_CSC_COEF_A2_MSB 0x10410 211#define HDMI_CORE_CSC_COEF_A2_LSB 0x10414 212#define HDMI_CORE_CSC_COEF_A3_MSB 0x10418 213#define HDMI_CORE_CSC_COEF_A3_LSB 0x1041C 214#define HDMI_CORE_CSC_COEF_A4_MSB 0x10420 215#define HDMI_CORE_CSC_COEF_A4_LSB 0x10424 216#define HDMI_CORE_CSC_COEF_B1_MSB 0x10428 217#define HDMI_CORE_CSC_COEF_B1_LSB 0x1042C 218#define HDMI_CORE_CSC_COEF_B2_MSB 0x10430 219#define HDMI_CORE_CSC_COEF_B2_LSB 0x10434 220#define HDMI_CORE_CSC_COEF_B3_MSB 0x10438 221#define HDMI_CORE_CSC_COEF_B3_LSB 0x1043C 222#define HDMI_CORE_CSC_COEF_B4_MSB 0x10440 223#define HDMI_CORE_CSC_COEF_B4_LSB 0x10444 224#define HDMI_CORE_CSC_COEF_C1_MSB 0x10448 225#define HDMI_CORE_CSC_COEF_C1_LSB 0x1044C 226#define HDMI_CORE_CSC_COEF_C2_MSB 0x10450 227#define HDMI_CORE_CSC_COEF_C2_LSB 0x10454 228#define HDMI_CORE_CSC_COEF_C3_MSB 0x10458 229#define HDMI_CORE_CSC_COEF_C3_LSB 0x1045C 230#define HDMI_CORE_CSC_COEF_C4_MSB 0x10460 231#define HDMI_CORE_CSC_COEF_C4_LSB 0x10464 232 233/* HDMI HDCP */ 234#define HDMI_CORE_HDCP_MASK 0x14020 235 236/* HDMI CEC */ 237#define HDMI_CORE_CEC_MASK 0x17408 238 239/* HDMI I2C Master */ 240#define HDMI_CORE_I2CM_SLAVE 0x157C8 241#define HDMI_CORE_I2CM_ADDRESS 0x157CC 242#define HDMI_CORE_I2CM_DATAO 0x157D0 243#define HDMI_CORE_I2CM_DATAI 0X157D4 244#define HDMI_CORE_I2CM_OPERATION 0x157D8 245#define HDMI_CORE_I2CM_INT 0x157DC 246#define HDMI_CORE_I2CM_CTLINT 0x157E0 247#define HDMI_CORE_I2CM_DIV 0x157E4 248#define HDMI_CORE_I2CM_SEGADDR 0x157E8 249#define HDMI_CORE_I2CM_SOFTRSTZ 0x157EC 250#define HDMI_CORE_I2CM_SEGPTR 0x157F0 251#define HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR 0x157F4 252#define HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR 0x157F8 253#define HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR 0x157FC 254#define HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR 0x15800 255#define HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR 0x15804 256#define HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR 0x15808 257#define HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR 0x1580C 258#define HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR 0x15810 259#define HDMI_CORE_I2CM_SDA_HOLD_ADDR 0x15814 260 261enum hdmi_core_packet_mode { 262 HDMI_PACKETMODERESERVEDVALUE = 0, 263 HDMI_PACKETMODE24BITPERPIXEL = 4, 264 HDMI_PACKETMODE30BITPERPIXEL = 5, 265 HDMI_PACKETMODE36BITPERPIXEL = 6, 266 HDMI_PACKETMODE48BITPERPIXEL = 7, 267}; 268 269struct hdmi_core_vid_config { 270 struct hdmi_config v_fc_config; 271 enum hdmi_core_packet_mode packet_mode; 272 int data_enable_pol; 273 int vblank_osc; 274 int hblank; 275 int vblank; 276}; 277 278struct csc_table { 279 u16 a1, a2, a3, a4; 280 u16 b1, b2, b3, b4; 281 u16 c1, c2, c3, c4; 282}; 283 284int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len); 285void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s); 286int hdmi5_core_handle_irqs(struct hdmi_core_data *core); 287void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 288 struct hdmi_config *cfg); 289int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core); 290 291int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 292 struct omap_dss_audio *audio, u32 pclk); 293#endif 294