1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Fujitsu MB862xx Graphics Controller Registers/Bits 4 */ 5 6#ifndef _MB862XX_REG_H 7#define _MB862XX_REG_H 8 9#define MB862XX_MMIO_BASE 0x01fc0000 10#define MB862XX_MMIO_HIGH_BASE 0x03fc0000 11#define MB862XX_I2C_BASE 0x0000c000 12#define MB862XX_DISP_BASE 0x00010000 13#define MB862XX_CAP_BASE 0x00018000 14#define MB862XX_DRAW_BASE 0x00030000 15#define MB862XX_GEO_BASE 0x00038000 16#define MB862XX_PIO_BASE 0x00038000 17#define MB862XX_MMIO_SIZE 0x40000 18 19/* Host interface/pio registers */ 20#define GC_IST 0x00000020 21#define GC_IMASK 0x00000024 22#define GC_SRST 0x0000002c 23#define GC_CCF 0x00000038 24#define GC_RSW 0x0000005c 25#define GC_CID 0x000000f0 26#define GC_REVISION 0x00000084 27 28#define GC_CCF_CGE_100 0x00000000 29#define GC_CCF_CGE_133 0x00040000 30#define GC_CCF_CGE_166 0x00080000 31#define GC_CCF_COT_100 0x00000000 32#define GC_CCF_COT_133 0x00010000 33#define GC_CID_CNAME_MSK 0x0000ff00 34#define GC_CID_VERSION_MSK 0x000000ff 35 36/* define enabled interrupts hereby */ 37#define GC_INT_EN 0x00000000 38 39/* Memory interface mode register */ 40#define GC_MMR 0x0000fffc 41 42/* Display Controller registers */ 43#define GC_DCM0 0x00000000 44#define GC_HTP 0x00000004 45#define GC_HDB_HDP 0x00000008 46#define GC_VSW_HSW_HSP 0x0000000c 47#define GC_VTR 0x00000010 48#define GC_VDP_VSP 0x00000014 49#define GC_WY_WX 0x00000018 50#define GC_WH_WW 0x0000001c 51#define GC_L0M 0x00000020 52#define GC_L0OA0 0x00000024 53#define GC_L0DA0 0x00000028 54#define GC_L0DY_L0DX 0x0000002c 55#define GC_L1M 0x00000030 56#define GC_L1DA 0x00000034 57#define GC_DCM1 0x00000100 58#define GC_L0EM 0x00000110 59#define GC_L0WY_L0WX 0x00000114 60#define GC_L0WH_L0WW 0x00000118 61#define GC_L1EM 0x00000120 62#define GC_L1WY_L1WX 0x00000124 63#define GC_L1WH_L1WW 0x00000128 64#define GC_DLS 0x00000180 65#define GC_DCM2 0x00000104 66#define GC_DCM3 0x00000108 67#define GC_CPM_CUTC 0x000000a0 68#define GC_CUOA0 0x000000a4 69#define GC_CUY0_CUX0 0x000000a8 70#define GC_CUOA1 0x000000ac 71#define GC_CUY1_CUX1 0x000000b0 72#define GC_L0PAL0 0x00000400 73 74#define GC_CPM_CEN0 0x00100000 75#define GC_CPM_CEN1 0x00200000 76#define GC_DCM1_DEN 0x80000000 77#define GC_DCM1_L1E 0x00020000 78#define GC_L1M_16 0x80000000 79#define GC_L1M_YC 0x40000000 80#define GC_L1M_CS 0x20000000 81 82#define GC_DCM01_ESY 0x00000004 83#define GC_DCM01_SC 0x00003f00 84#define GC_DCM01_RESV 0x00004000 85#define GC_DCM01_CKS 0x00008000 86#define GC_DCM01_L0E 0x00010000 87#define GC_DCM01_DEN 0x80000000 88#define GC_L0M_L0C_8 0x00000000 89#define GC_L0M_L0C_16 0x80000000 90#define GC_L0EM_L0EC_24 0x40000000 91#define GC_L0M_L0W_UNIT 64 92#define GC_L1EM_DM 0x02000000 93 94#define GC_DISP_REFCLK_400 400 95 96/* I2C */ 97#define GC_I2C_BSR 0x00000000 /* BSR */ 98#define GC_I2C_BCR 0x00000004 /* BCR */ 99#define GC_I2C_CCR 0x00000008 /* CCR */ 100#define GC_I2C_ADR 0x0000000C /* ADR */ 101#define GC_I2C_DAR 0x00000010 /* DAR */ 102 103#define I2C_DISABLE 0x00000000 104#define I2C_STOP 0x00000000 105#define I2C_START 0x00000010 106#define I2C_REPEATED_START 0x00000030 107#define I2C_CLOCK_AND_ENABLE 0x0000003f 108#define I2C_READY 0x01 109#define I2C_INT 0x01 110#define I2C_INTE 0x02 111#define I2C_ACK 0x08 112#define I2C_BER 0x80 113#define I2C_BEIE 0x40 114#define I2C_TRX 0x80 115#define I2C_LRB 0x10 116 117/* Capture registers and bits */ 118#define GC_CAP_VCM 0x00000000 119#define GC_CAP_CSC 0x00000004 120#define GC_CAP_VCS 0x00000008 121#define GC_CAP_CBM 0x00000010 122#define GC_CAP_CBOA 0x00000014 123#define GC_CAP_CBLA 0x00000018 124#define GC_CAP_IMG_START 0x0000001C 125#define GC_CAP_IMG_END 0x00000020 126#define GC_CAP_CMSS 0x00000048 127#define GC_CAP_CMDS 0x0000004C 128 129#define GC_VCM_VIE 0x80000000 130#define GC_VCM_CM 0x03000000 131#define GC_VCM_VS_PAL 0x00000002 132#define GC_CBM_OO 0x80000000 133#define GC_CBM_HRV 0x00000010 134#define GC_CBM_CBST 0x00000001 135 136/* Carmine specific */ 137#define MB86297_DRAW_BASE 0x00020000 138#define MB86297_DISP0_BASE 0x00100000 139#define MB86297_DISP1_BASE 0x00140000 140#define MB86297_WRBACK_BASE 0x00180000 141#define MB86297_CAP0_BASE 0x00200000 142#define MB86297_CAP1_BASE 0x00280000 143#define MB86297_DRAMCTRL_BASE 0x00300000 144#define MB86297_CTRL_BASE 0x00400000 145#define MB86297_I2C_BASE 0x00500000 146 147#define GC_CTRL_STATUS 0x00000000 148#define GC_CTRL_INT_MASK 0x00000004 149#define GC_CTRL_CLK_ENABLE 0x0000000c 150#define GC_CTRL_SOFT_RST 0x00000010 151 152#define GC_CTRL_CLK_EN_DRAM 0x00000001 153#define GC_CTRL_CLK_EN_2D3D 0x00000002 154#define GC_CTRL_CLK_EN_DISP0 0x00000020 155#define GC_CTRL_CLK_EN_DISP1 0x00000040 156 157#define GC_2D3D_REV 0x000004b4 158#define GC_RE_REVISION 0x24240200 159 160/* define enabled interrupts hereby */ 161#define GC_CARMINE_INT_EN 0x00000004 162 163/* DRAM controller */ 164#define GC_DCTL_MODE_ADD 0x00000000 165#define GC_DCTL_SETTIME1_EMODE 0x00000004 166#define GC_DCTL_REFRESH_SETTIME2 0x00000008 167#define GC_DCTL_RSV0_STATES 0x0000000C 168#define GC_DCTL_RSV2_RSV1 0x00000010 169#define GC_DCTL_DDRIF2_DDRIF1 0x00000014 170#define GC_DCTL_IOCONT1_IOCONT0 0x00000024 171 172#define GC_DCTL_STATES_MSK 0x0000000f 173#define GC_DCTL_INIT_WAIT_CNT 3000 174#define GC_DCTL_INIT_WAIT_INTERVAL 1 175 176/* DRAM ctrl values for Carmine PCI Eval. board */ 177#define GC_EVB_DCTL_MODE_ADD 0x012105c3 178#define GC_EVB_DCTL_MODE_ADD_AFT_RST 0x002105c3 179#define GC_EVB_DCTL_SETTIME1_EMODE 0x47498000 180#define GC_EVB_DCTL_REFRESH_SETTIME2 0x00422a22 181#define GC_EVB_DCTL_RSV0_STATES 0x00200003 182#define GC_EVB_DCTL_RSV0_STATES_AFT_RST 0x00200002 183#define GC_EVB_DCTL_RSV2_RSV1 0x0000000f 184#define GC_EVB_DCTL_DDRIF2_DDRIF1 0x00556646 185#define GC_EVB_DCTL_IOCONT1_IOCONT0 0x05550555 186 187#define GC_DISP_REFCLK_533 533 188 189#endif 190