1/* SPDX-License-Identifier: GPL-2.0 */ 2 3/* hc_capbase bitmasks */ 4/* bits 7:0 - how long is the Capabilities register */ 5#define HC_LENGTH(p) XHCI_HC_LENGTH(p) 6/* bits 31:16 */ 7#define HC_VERSION(p) (((p) >> 16) & 0xffff) 8 9/* HCSPARAMS1 - hcs_params1 - bitmasks */ 10/* bits 0:7, Max Device Slots */ 11#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 12#define HCS_SLOTS_MASK 0xff 13/* bits 8:18, Max Interrupters */ 14#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 15/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 16#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 17 18/* HCSPARAMS2 - hcs_params2 - bitmasks */ 19/* bits 0:3, frames or uframes that SW needs to queue transactions 20 * ahead of the HW to meet periodic deadlines */ 21#define HCS_IST(p) (((p) >> 0) & 0xf) 22/* bits 4:7, max number of Event Ring segments */ 23#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 24/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 25/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 26/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 27#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 28 29/* HCSPARAMS3 - hcs_params3 - bitmasks */ 30/* bits 0:7, Max U1 to U0 latency for the roothub ports */ 31#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 32/* bits 16:31, Max U2 to U0 latency for the roothub ports */ 33#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 34 35/* HCCPARAMS - hcc_params - bitmasks */ 36/* true: HC can use 64-bit address pointers */ 37#define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 38/* true: HC can do bandwidth negotiation */ 39#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 40/* true: HC uses 64-byte Device Context structures 41 * FIXME 64-byte context structures aren't supported yet. 42 */ 43#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 44/* true: HC has port power switches */ 45#define HCC_PPC(p) ((p) & (1 << 3)) 46/* true: HC has port indicators */ 47#define HCS_INDICATOR(p) ((p) & (1 << 4)) 48/* true: HC has Light HC Reset Capability */ 49#define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 50/* true: HC supports latency tolerance messaging */ 51#define HCC_LTC(p) ((p) & (1 << 6)) 52/* true: no secondary Stream ID Support */ 53#define HCC_NSS(p) ((p) & (1 << 7)) 54/* true: HC supports Stopped - Short Packet */ 55#define HCC_SPC(p) ((p) & (1 << 9)) 56/* true: HC has Contiguous Frame ID Capability */ 57#define HCC_CFC(p) ((p) & (1 << 11)) 58/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 59#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 60/* Extended Capabilities pointer from PCI base - section 5.3.6 */ 61#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 62 63#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 64 65/* db_off bitmask - bits 0:1 reserved */ 66#define DBOFF_MASK (~0x3) 67 68/* run_regs_off bitmask - bits 0:4 reserved */ 69#define RTSOFF_MASK (~0x1f) 70 71/* HCCPARAMS2 - hcc_params2 - bitmasks */ 72/* true: HC supports U3 entry Capability */ 73#define HCC2_U3C(p) ((p) & (1 << 0)) 74/* true: HC supports Configure endpoint command Max exit latency too large */ 75#define HCC2_CMC(p) ((p) & (1 << 1)) 76/* true: HC supports Force Save context Capability */ 77#define HCC2_FSC(p) ((p) & (1 << 2)) 78/* true: HC supports Compliance Transition Capability */ 79#define HCC2_CTC(p) ((p) & (1 << 3)) 80/* true: HC support Large ESIT payload Capability > 48k */ 81#define HCC2_LEC(p) ((p) & (1 << 4)) 82/* true: HC support Configuration Information Capability */ 83#define HCC2_CIC(p) ((p) & (1 << 5)) 84/* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ 85#define HCC2_ETC(p) ((p) & (1 << 6)) 86