1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 4 */ 5#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 6#include <linux/kernel.h> 7#include <linux/module.h> 8#include <linux/pci.h> 9#include <linux/delay.h> 10#include <linux/errno.h> 11#include <linux/gpio/consumer.h> 12#include <linux/gpio/machine.h> 13#include <linux/list.h> 14#include <linux/interrupt.h> 15#include <linux/usb/ch9.h> 16#include <linux/usb/gadget.h> 17#include <linux/irq.h> 18 19#define PCH_VBUS_PERIOD 3000 /* VBUS polling period (msec) */ 20#define PCH_VBUS_INTERVAL 10 /* VBUS polling interval (msec) */ 21 22/* Address offset of Registers */ 23#define UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */ 24 25#define UDC_EPCTL_ADDR 0x00 /* Endpoint control */ 26#define UDC_EPSTS_ADDR 0x04 /* Endpoint status */ 27#define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */ 28#define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */ 29#define UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */ 30#define UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */ 31#define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */ 32 33#define UDC_DEVCFG_ADDR 0x400 /* Device configuration */ 34#define UDC_DEVCTL_ADDR 0x404 /* Device control */ 35#define UDC_DEVSTS_ADDR 0x408 /* Device status */ 36#define UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */ 37#define UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */ 38#define UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */ 39#define UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */ 40#define UDC_DEVLPM_ADDR 0x41C /* LPM control / status */ 41#define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */ 42#define UDC_SRST_ADDR 0x4fc /* SOFT RESET register */ 43#define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */ 44 45/* Endpoint control register */ 46/* Bit position */ 47#define UDC_EPCTL_MRXFLUSH (1 << 12) 48#define UDC_EPCTL_RRDY (1 << 9) 49#define UDC_EPCTL_CNAK (1 << 8) 50#define UDC_EPCTL_SNAK (1 << 7) 51#define UDC_EPCTL_NAK (1 << 6) 52#define UDC_EPCTL_P (1 << 3) 53#define UDC_EPCTL_F (1 << 1) 54#define UDC_EPCTL_S (1 << 0) 55#define UDC_EPCTL_ET_SHIFT 4 56/* Mask patern */ 57#define UDC_EPCTL_ET_MASK 0x00000030 58/* Value for ET field */ 59#define UDC_EPCTL_ET_CONTROL 0 60#define UDC_EPCTL_ET_ISO 1 61#define UDC_EPCTL_ET_BULK 2 62#define UDC_EPCTL_ET_INTERRUPT 3 63 64/* Endpoint status register */ 65/* Bit position */ 66#define UDC_EPSTS_XFERDONE (1 << 27) 67#define UDC_EPSTS_RSS (1 << 26) 68#define UDC_EPSTS_RCS (1 << 25) 69#define UDC_EPSTS_TXEMPTY (1 << 24) 70#define UDC_EPSTS_TDC (1 << 10) 71#define UDC_EPSTS_HE (1 << 9) 72#define UDC_EPSTS_MRXFIFO_EMP (1 << 8) 73#define UDC_EPSTS_BNA (1 << 7) 74#define UDC_EPSTS_IN (1 << 6) 75#define UDC_EPSTS_OUT_SHIFT 4 76/* Mask patern */ 77#define UDC_EPSTS_OUT_MASK 0x00000030 78#define UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0 79/* Value for OUT field */ 80#define UDC_EPSTS_OUT_SETUP 2 81#define UDC_EPSTS_OUT_DATA 1 82 83/* Device configuration register */ 84/* Bit position */ 85#define UDC_DEVCFG_CSR_PRG (1 << 17) 86#define UDC_DEVCFG_SP (1 << 3) 87/* SPD Valee */ 88#define UDC_DEVCFG_SPD_HS 0x0 89#define UDC_DEVCFG_SPD_FS 0x1 90#define UDC_DEVCFG_SPD_LS 0x2 91 92/* Device control register */ 93/* Bit position */ 94#define UDC_DEVCTL_THLEN_SHIFT 24 95#define UDC_DEVCTL_BRLEN_SHIFT 16 96#define UDC_DEVCTL_CSR_DONE (1 << 13) 97#define UDC_DEVCTL_SD (1 << 10) 98#define UDC_DEVCTL_MODE (1 << 9) 99#define UDC_DEVCTL_BREN (1 << 8) 100#define UDC_DEVCTL_THE (1 << 7) 101#define UDC_DEVCTL_DU (1 << 4) 102#define UDC_DEVCTL_TDE (1 << 3) 103#define UDC_DEVCTL_RDE (1 << 2) 104#define UDC_DEVCTL_RES (1 << 0) 105 106/* Device status register */ 107/* Bit position */ 108#define UDC_DEVSTS_TS_SHIFT 18 109#define UDC_DEVSTS_ENUM_SPEED_SHIFT 13 110#define UDC_DEVSTS_ALT_SHIFT 8 111#define UDC_DEVSTS_INTF_SHIFT 4 112#define UDC_DEVSTS_CFG_SHIFT 0 113/* Mask patern */ 114#define UDC_DEVSTS_TS_MASK 0xfffc0000 115#define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000 116#define UDC_DEVSTS_ALT_MASK 0x00000f00 117#define UDC_DEVSTS_INTF_MASK 0x000000f0 118#define UDC_DEVSTS_CFG_MASK 0x0000000f 119/* value for maximum speed for SPEED field */ 120#define UDC_DEVSTS_ENUM_SPEED_FULL 1 121#define UDC_DEVSTS_ENUM_SPEED_HIGH 0 122#define UDC_DEVSTS_ENUM_SPEED_LOW 2 123#define UDC_DEVSTS_ENUM_SPEED_FULLX 3 124 125/* Device irq register */ 126/* Bit position */ 127#define UDC_DEVINT_RWKP (1 << 7) 128#define UDC_DEVINT_ENUM (1 << 6) 129#define UDC_DEVINT_SOF (1 << 5) 130#define UDC_DEVINT_US (1 << 4) 131#define UDC_DEVINT_UR (1 << 3) 132#define UDC_DEVINT_ES (1 << 2) 133#define UDC_DEVINT_SI (1 << 1) 134#define UDC_DEVINT_SC (1 << 0) 135/* Mask patern */ 136#define UDC_DEVINT_MSK 0x7f 137 138/* Endpoint irq register */ 139/* Bit position */ 140#define UDC_EPINT_IN_SHIFT 0 141#define UDC_EPINT_OUT_SHIFT 16 142#define UDC_EPINT_IN_EP0 (1 << 0) 143#define UDC_EPINT_OUT_EP0 (1 << 16) 144/* Mask patern */ 145#define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff 146 147/* UDC_CSR_BUSY Status register */ 148/* Bit position */ 149#define UDC_CSR_BUSY (1 << 0) 150 151/* SOFT RESET register */ 152/* Bit position */ 153#define UDC_PSRST (1 << 1) 154#define UDC_SRST (1 << 0) 155 156/* USB_DEVICE endpoint register */ 157/* Bit position */ 158#define UDC_CSR_NE_NUM_SHIFT 0 159#define UDC_CSR_NE_DIR_SHIFT 4 160#define UDC_CSR_NE_TYPE_SHIFT 5 161#define UDC_CSR_NE_CFG_SHIFT 7 162#define UDC_CSR_NE_INTF_SHIFT 11 163#define UDC_CSR_NE_ALT_SHIFT 15 164#define UDC_CSR_NE_MAX_PKT_SHIFT 19 165/* Mask patern */ 166#define UDC_CSR_NE_NUM_MASK 0x0000000f 167#define UDC_CSR_NE_DIR_MASK 0x00000010 168#define UDC_CSR_NE_TYPE_MASK 0x00000060 169#define UDC_CSR_NE_CFG_MASK 0x00000780 170#define UDC_CSR_NE_INTF_MASK 0x00007800 171#define UDC_CSR_NE_ALT_MASK 0x00078000 172#define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000 173 174#define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4) 175#define PCH_UDC_EPINT(in, num)\ 176 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT))) 177 178/* Index of endpoint */ 179#define UDC_EP0IN_IDX 0 180#define UDC_EP0OUT_IDX 1 181#define UDC_EPIN_IDX(ep) (ep * 2) 182#define UDC_EPOUT_IDX(ep) (ep * 2 + 1) 183#define PCH_UDC_EP0 0 184#define PCH_UDC_EP1 1 185#define PCH_UDC_EP2 2 186#define PCH_UDC_EP3 3 187 188/* Number of endpoint */ 189#define PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */ 190#define PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */ 191/* Length Value */ 192#define PCH_UDC_BRLEN 0x0F /* Burst length */ 193#define PCH_UDC_THLEN 0x1F /* Threshold length */ 194/* Value of EP Buffer Size */ 195#define UDC_EP0IN_BUFF_SIZE 16 196#define UDC_EPIN_BUFF_SIZE 256 197#define UDC_EP0OUT_BUFF_SIZE 16 198#define UDC_EPOUT_BUFF_SIZE 256 199/* Value of EP maximum packet size */ 200#define UDC_EP0IN_MAX_PKT_SIZE 64 201#define UDC_EP0OUT_MAX_PKT_SIZE 64 202#define UDC_BULK_MAX_PKT_SIZE 512 203 204/* DMA */ 205#define DMA_DIR_RX 1 /* DMA for data receive */ 206#define DMA_DIR_TX 2 /* DMA for data transmit */ 207#define DMA_ADDR_INVALID (~(dma_addr_t)0) 208#define UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */ 209 210/** 211 * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information 212 * for data 213 * @status: Status quadlet 214 * @reserved: Reserved 215 * @dataptr: Buffer descriptor 216 * @next: Next descriptor 217 */ 218struct pch_udc_data_dma_desc { 219 u32 status; 220 u32 reserved; 221 u32 dataptr; 222 u32 next; 223}; 224 225/** 226 * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information 227 * for control data 228 * @status: Status 229 * @reserved: Reserved 230 * @request: Control Request 231 */ 232struct pch_udc_stp_dma_desc { 233 u32 status; 234 u32 reserved; 235 struct usb_ctrlrequest request; 236} __attribute((packed)); 237 238/* DMA status definitions */ 239/* Buffer status */ 240#define PCH_UDC_BUFF_STS 0xC0000000 241#define PCH_UDC_BS_HST_RDY 0x00000000 242#define PCH_UDC_BS_DMA_BSY 0x40000000 243#define PCH_UDC_BS_DMA_DONE 0x80000000 244#define PCH_UDC_BS_HST_BSY 0xC0000000 245/* Rx/Tx Status */ 246#define PCH_UDC_RXTX_STS 0x30000000 247#define PCH_UDC_RTS_SUCC 0x00000000 248#define PCH_UDC_RTS_DESERR 0x10000000 249#define PCH_UDC_RTS_BUFERR 0x30000000 250/* Last Descriptor Indication */ 251#define PCH_UDC_DMA_LAST 0x08000000 252/* Number of Rx/Tx Bytes Mask */ 253#define PCH_UDC_RXTX_BYTES 0x0000ffff 254 255/** 256 * struct pch_udc_cfg_data - Structure to hold current configuration 257 * and interface information 258 * @cur_cfg: current configuration in use 259 * @cur_intf: current interface in use 260 * @cur_alt: current alt interface in use 261 */ 262struct pch_udc_cfg_data { 263 u16 cur_cfg; 264 u16 cur_intf; 265 u16 cur_alt; 266}; 267 268/** 269 * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information 270 * @ep: embedded ep request 271 * @td_stp_phys: for setup request 272 * @td_data_phys: for data request 273 * @td_stp: for setup request 274 * @td_data: for data request 275 * @dev: reference to device struct 276 * @offset_addr: offset address of ep register 277 * @queue: queue for requests 278 * @num: endpoint number 279 * @in: endpoint is IN 280 * @halted: endpoint halted? 281 * @epsts: Endpoint status 282 */ 283struct pch_udc_ep { 284 struct usb_ep ep; 285 dma_addr_t td_stp_phys; 286 dma_addr_t td_data_phys; 287 struct pch_udc_stp_dma_desc *td_stp; 288 struct pch_udc_data_dma_desc *td_data; 289 struct pch_udc_dev *dev; 290 unsigned long offset_addr; 291 struct list_head queue; 292 unsigned num:5, 293 in:1, 294 halted:1; 295 unsigned long epsts; 296}; 297 298/** 299 * struct pch_vbus_gpio_data - Structure holding GPIO informaton 300 * for detecting VBUS 301 * @port: gpio descriptor for the VBUS GPIO 302 * @intr: gpio interrupt number 303 * @irq_work_fall: Structure for WorkQueue 304 * @irq_work_rise: Structure for WorkQueue 305 */ 306struct pch_vbus_gpio_data { 307 struct gpio_desc *port; 308 int intr; 309 struct work_struct irq_work_fall; 310 struct work_struct irq_work_rise; 311}; 312 313/** 314 * struct pch_udc_dev - Structure holding complete information 315 * of the PCH USB device 316 * @gadget: gadget driver data 317 * @driver: reference to gadget driver bound 318 * @pdev: reference to the PCI device 319 * @ep: array of endpoints 320 * @lock: protects all state 321 * @stall: stall requested 322 * @prot_stall: protcol stall requested 323 * @registered: driver registered with system 324 * @suspended: driver in suspended state 325 * @connected: gadget driver associated 326 * @vbus_session: required vbus_session state 327 * @set_cfg_not_acked: pending acknowledgement 4 setup 328 * @waiting_zlp_ack: pending acknowledgement 4 ZLP 329 * @data_requests: DMA pool for data requests 330 * @stp_requests: DMA pool for setup requests 331 * @dma_addr: DMA pool for received 332 * @setup_data: Received setup data 333 * @base_addr: for mapped device memory 334 * @bar: PCI BAR used for mapped device memory 335 * @cfg_data: current cfg, intf, and alt in use 336 * @vbus_gpio: GPIO informaton for detecting VBUS 337 */ 338struct pch_udc_dev { 339 struct usb_gadget gadget; 340 struct usb_gadget_driver *driver; 341 struct pci_dev *pdev; 342 struct pch_udc_ep ep[PCH_UDC_EP_NUM]; 343 spinlock_t lock; /* protects all state */ 344 unsigned 345 stall:1, 346 prot_stall:1, 347 suspended:1, 348 connected:1, 349 vbus_session:1, 350 set_cfg_not_acked:1, 351 waiting_zlp_ack:1; 352 struct dma_pool *data_requests; 353 struct dma_pool *stp_requests; 354 dma_addr_t dma_addr; 355 struct usb_ctrlrequest setup_data; 356 void __iomem *base_addr; 357 unsigned short bar; 358 struct pch_udc_cfg_data cfg_data; 359 struct pch_vbus_gpio_data vbus_gpio; 360}; 361#define to_pch_udc(g) (container_of((g), struct pch_udc_dev, gadget)) 362 363#define PCH_UDC_PCI_BAR_QUARK_X1000 0 364#define PCH_UDC_PCI_BAR 1 365 366#define PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC 0x0939 367#define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808 368 369#define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D 370#define PCI_DEVICE_ID_ML7831_IOH_UDC 0x8808 371 372static const char ep0_string[] = "ep0in"; 373static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */ 374static bool speed_fs; 375module_param_named(speed_fs, speed_fs, bool, S_IRUGO); 376MODULE_PARM_DESC(speed_fs, "true for Full speed operation"); 377 378/** 379 * struct pch_udc_request - Structure holding a PCH USB device request packet 380 * @req: embedded ep request 381 * @td_data_phys: phys. address 382 * @td_data: first dma desc. of chain 383 * @td_data_last: last dma desc. of chain 384 * @queue: associated queue 385 * @dma_going: DMA in progress for request 386 * @dma_done: DMA completed for request 387 * @chain_len: chain length 388 */ 389struct pch_udc_request { 390 struct usb_request req; 391 dma_addr_t td_data_phys; 392 struct pch_udc_data_dma_desc *td_data; 393 struct pch_udc_data_dma_desc *td_data_last; 394 struct list_head queue; 395 unsigned dma_going:1, 396 dma_done:1; 397 unsigned chain_len; 398}; 399 400static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg) 401{ 402 return ioread32(dev->base_addr + reg); 403} 404 405static inline void pch_udc_writel(struct pch_udc_dev *dev, 406 unsigned long val, unsigned long reg) 407{ 408 iowrite32(val, dev->base_addr + reg); 409} 410 411static inline void pch_udc_bit_set(struct pch_udc_dev *dev, 412 unsigned long reg, 413 unsigned long bitmask) 414{ 415 pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg); 416} 417 418static inline void pch_udc_bit_clr(struct pch_udc_dev *dev, 419 unsigned long reg, 420 unsigned long bitmask) 421{ 422 pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg); 423} 424 425static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg) 426{ 427 return ioread32(ep->dev->base_addr + ep->offset_addr + reg); 428} 429 430static inline void pch_udc_ep_writel(struct pch_udc_ep *ep, 431 unsigned long val, unsigned long reg) 432{ 433 iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg); 434} 435 436static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep, 437 unsigned long reg, 438 unsigned long bitmask) 439{ 440 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg); 441} 442 443static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep, 444 unsigned long reg, 445 unsigned long bitmask) 446{ 447 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg); 448} 449 450/** 451 * pch_udc_csr_busy() - Wait till idle. 452 * @dev: Reference to pch_udc_dev structure 453 */ 454static void pch_udc_csr_busy(struct pch_udc_dev *dev) 455{ 456 unsigned int count = 200; 457 458 /* Wait till idle */ 459 while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY) 460 && --count) 461 cpu_relax(); 462 if (!count) 463 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__); 464} 465 466/** 467 * pch_udc_write_csr() - Write the command and status registers. 468 * @dev: Reference to pch_udc_dev structure 469 * @val: value to be written to CSR register 470 * @ep: end-point number 471 */ 472static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val, 473 unsigned int ep) 474{ 475 unsigned long reg = PCH_UDC_CSR(ep); 476 477 pch_udc_csr_busy(dev); /* Wait till idle */ 478 pch_udc_writel(dev, val, reg); 479 pch_udc_csr_busy(dev); /* Wait till idle */ 480} 481 482/** 483 * pch_udc_read_csr() - Read the command and status registers. 484 * @dev: Reference to pch_udc_dev structure 485 * @ep: end-point number 486 * 487 * Return codes: content of CSR register 488 */ 489static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep) 490{ 491 unsigned long reg = PCH_UDC_CSR(ep); 492 493 pch_udc_csr_busy(dev); /* Wait till idle */ 494 pch_udc_readl(dev, reg); /* Dummy read */ 495 pch_udc_csr_busy(dev); /* Wait till idle */ 496 return pch_udc_readl(dev, reg); 497} 498 499/** 500 * pch_udc_rmt_wakeup() - Initiate for remote wakeup 501 * @dev: Reference to pch_udc_dev structure 502 */ 503static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev) 504{ 505 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES); 506 mdelay(1); 507 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES); 508} 509 510/** 511 * pch_udc_get_frame() - Get the current frame from device status register 512 * @dev: Reference to pch_udc_dev structure 513 * Retern current frame 514 */ 515static inline int pch_udc_get_frame(struct pch_udc_dev *dev) 516{ 517 u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR); 518 return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT; 519} 520 521/** 522 * pch_udc_clear_selfpowered() - Clear the self power control 523 * @dev: Reference to pch_udc_regs structure 524 */ 525static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev) 526{ 527 pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP); 528} 529 530/** 531 * pch_udc_set_selfpowered() - Set the self power control 532 * @dev: Reference to pch_udc_regs structure 533 */ 534static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev) 535{ 536 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP); 537} 538 539/** 540 * pch_udc_set_disconnect() - Set the disconnect status. 541 * @dev: Reference to pch_udc_regs structure 542 */ 543static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev) 544{ 545 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD); 546} 547 548/** 549 * pch_udc_clear_disconnect() - Clear the disconnect status. 550 * @dev: Reference to pch_udc_regs structure 551 */ 552static void pch_udc_clear_disconnect(struct pch_udc_dev *dev) 553{ 554 /* Clear the disconnect */ 555 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES); 556 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD); 557 mdelay(1); 558 /* Resume USB signalling */ 559 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES); 560} 561 562static void pch_udc_init(struct pch_udc_dev *dev); 563 564/** 565 * pch_udc_reconnect() - This API initializes usb device controller, 566 * and clear the disconnect status. 567 * @dev: Reference to pch_udc_regs structure 568 */ 569static void pch_udc_reconnect(struct pch_udc_dev *dev) 570{ 571 pch_udc_init(dev); 572 573 /* enable device interrupts */ 574 /* pch_udc_enable_interrupts() */ 575 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, 576 UDC_DEVINT_UR | UDC_DEVINT_ENUM); 577 578 /* Clear the disconnect */ 579 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES); 580 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD); 581 mdelay(1); 582 /* Resume USB signalling */ 583 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES); 584} 585 586/** 587 * pch_udc_vbus_session() - set or clearr the disconnect status. 588 * @dev: Reference to pch_udc_regs structure 589 * @is_active: Parameter specifying the action 590 * 0: indicating VBUS power is ending 591 * !0: indicating VBUS power is starting 592 */ 593static inline void pch_udc_vbus_session(struct pch_udc_dev *dev, 594 int is_active) 595{ 596 unsigned long iflags; 597 598 spin_lock_irqsave(&dev->lock, iflags); 599 if (is_active) { 600 pch_udc_reconnect(dev); 601 dev->vbus_session = 1; 602 } else { 603 if (dev->driver && dev->driver->disconnect) { 604 spin_unlock_irqrestore(&dev->lock, iflags); 605 dev->driver->disconnect(&dev->gadget); 606 spin_lock_irqsave(&dev->lock, iflags); 607 } 608 pch_udc_set_disconnect(dev); 609 dev->vbus_session = 0; 610 } 611 spin_unlock_irqrestore(&dev->lock, iflags); 612} 613 614/** 615 * pch_udc_ep_set_stall() - Set the stall of endpoint 616 * @ep: Reference to structure of type pch_udc_ep_regs 617 */ 618static void pch_udc_ep_set_stall(struct pch_udc_ep *ep) 619{ 620 if (ep->in) { 621 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F); 622 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S); 623 } else { 624 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S); 625 } 626} 627 628/** 629 * pch_udc_ep_clear_stall() - Clear the stall of endpoint 630 * @ep: Reference to structure of type pch_udc_ep_regs 631 */ 632static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep) 633{ 634 /* Clear the stall */ 635 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S); 636 /* Clear NAK by writing CNAK */ 637 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK); 638} 639 640/** 641 * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint 642 * @ep: Reference to structure of type pch_udc_ep_regs 643 * @type: Type of endpoint 644 */ 645static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep, 646 u8 type) 647{ 648 pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) & 649 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR); 650} 651 652/** 653 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint 654 * @ep: Reference to structure of type pch_udc_ep_regs 655 * @buf_size: The buffer word size 656 * @ep_in: EP is IN 657 */ 658static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep, 659 u32 buf_size, u32 ep_in) 660{ 661 u32 data; 662 if (ep_in) { 663 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR); 664 data = (data & 0xffff0000) | (buf_size & 0xffff); 665 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR); 666 } else { 667 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR); 668 data = (buf_size << 16) | (data & 0xffff); 669 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR); 670 } 671} 672 673/** 674 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint 675 * @ep: Reference to structure of type pch_udc_ep_regs 676 * @pkt_size: The packet byte size 677 */ 678static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size) 679{ 680 u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR); 681 data = (data & 0xffff0000) | (pkt_size & 0xffff); 682 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR); 683} 684 685/** 686 * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint 687 * @ep: Reference to structure of type pch_udc_ep_regs 688 * @addr: Address of the register 689 */ 690static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr) 691{ 692 pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR); 693} 694 695/** 696 * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint 697 * @ep: Reference to structure of type pch_udc_ep_regs 698 * @addr: Address of the register 699 */ 700static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr) 701{ 702 pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR); 703} 704 705/** 706 * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint 707 * @ep: Reference to structure of type pch_udc_ep_regs 708 */ 709static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep) 710{ 711 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P); 712} 713 714/** 715 * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint 716 * @ep: Reference to structure of type pch_udc_ep_regs 717 */ 718static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep) 719{ 720 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY); 721} 722 723/** 724 * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint 725 * @ep: Reference to structure of type pch_udc_ep_regs 726 */ 727static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep) 728{ 729 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY); 730} 731 732/** 733 * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control 734 * register depending on the direction specified 735 * @dev: Reference to structure of type pch_udc_regs 736 * @dir: whether Tx or Rx 737 * DMA_DIR_RX: Receive 738 * DMA_DIR_TX: Transmit 739 */ 740static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir) 741{ 742 if (dir == DMA_DIR_RX) 743 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE); 744 else if (dir == DMA_DIR_TX) 745 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE); 746} 747 748/** 749 * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control 750 * register depending on the direction specified 751 * @dev: Reference to structure of type pch_udc_regs 752 * @dir: Whether Tx or Rx 753 * DMA_DIR_RX: Receive 754 * DMA_DIR_TX: Transmit 755 */ 756static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir) 757{ 758 if (dir == DMA_DIR_RX) 759 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE); 760 else if (dir == DMA_DIR_TX) 761 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE); 762} 763 764/** 765 * pch_udc_set_csr_done() - Set the device control register 766 * CSR done field (bit 13) 767 * @dev: reference to structure of type pch_udc_regs 768 */ 769static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev) 770{ 771 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE); 772} 773 774/** 775 * pch_udc_disable_interrupts() - Disables the specified interrupts 776 * @dev: Reference to structure of type pch_udc_regs 777 * @mask: Mask to disable interrupts 778 */ 779static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev, 780 u32 mask) 781{ 782 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask); 783} 784 785/** 786 * pch_udc_enable_interrupts() - Enable the specified interrupts 787 * @dev: Reference to structure of type pch_udc_regs 788 * @mask: Mask to enable interrupts 789 */ 790static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev, 791 u32 mask) 792{ 793 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask); 794} 795 796/** 797 * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts 798 * @dev: Reference to structure of type pch_udc_regs 799 * @mask: Mask to disable interrupts 800 */ 801static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev, 802 u32 mask) 803{ 804 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask); 805} 806 807/** 808 * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts 809 * @dev: Reference to structure of type pch_udc_regs 810 * @mask: Mask to enable interrupts 811 */ 812static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev, 813 u32 mask) 814{ 815 pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask); 816} 817 818/** 819 * pch_udc_read_device_interrupts() - Read the device interrupts 820 * @dev: Reference to structure of type pch_udc_regs 821 * Retern The device interrupts 822 */ 823static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev) 824{ 825 return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR); 826} 827 828/** 829 * pch_udc_write_device_interrupts() - Write device interrupts 830 * @dev: Reference to structure of type pch_udc_regs 831 * @val: The value to be written to interrupt register 832 */ 833static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev, 834 u32 val) 835{ 836 pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR); 837} 838 839/** 840 * pch_udc_read_ep_interrupts() - Read the endpoint interrupts 841 * @dev: Reference to structure of type pch_udc_regs 842 * Retern The endpoint interrupt 843 */ 844static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev) 845{ 846 return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR); 847} 848 849/** 850 * pch_udc_write_ep_interrupts() - Clear endpoint interupts 851 * @dev: Reference to structure of type pch_udc_regs 852 * @val: The value to be written to interrupt register 853 */ 854static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev, 855 u32 val) 856{ 857 pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR); 858} 859 860/** 861 * pch_udc_read_device_status() - Read the device status 862 * @dev: Reference to structure of type pch_udc_regs 863 * Retern The device status 864 */ 865static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev) 866{ 867 return pch_udc_readl(dev, UDC_DEVSTS_ADDR); 868} 869 870/** 871 * pch_udc_read_ep_control() - Read the endpoint control 872 * @ep: Reference to structure of type pch_udc_ep_regs 873 * Retern The endpoint control register value 874 */ 875static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep) 876{ 877 return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR); 878} 879 880/** 881 * pch_udc_clear_ep_control() - Clear the endpoint control register 882 * @ep: Reference to structure of type pch_udc_ep_regs 883 * Retern The endpoint control register value 884 */ 885static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep) 886{ 887 return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR); 888} 889 890/** 891 * pch_udc_read_ep_status() - Read the endpoint status 892 * @ep: Reference to structure of type pch_udc_ep_regs 893 * Retern The endpoint status 894 */ 895static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep) 896{ 897 return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR); 898} 899 900/** 901 * pch_udc_clear_ep_status() - Clear the endpoint status 902 * @ep: Reference to structure of type pch_udc_ep_regs 903 * @stat: Endpoint status 904 */ 905static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep, 906 u32 stat) 907{ 908 return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR); 909} 910 911/** 912 * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field) 913 * of the endpoint control register 914 * @ep: Reference to structure of type pch_udc_ep_regs 915 */ 916static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep) 917{ 918 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK); 919} 920 921/** 922 * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field) 923 * of the endpoint control register 924 * @ep: reference to structure of type pch_udc_ep_regs 925 */ 926static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep) 927{ 928 unsigned int loopcnt = 0; 929 struct pch_udc_dev *dev = ep->dev; 930 931 if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK)) 932 return; 933 if (!ep->in) { 934 loopcnt = 10000; 935 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) && 936 --loopcnt) 937 udelay(5); 938 if (!loopcnt) 939 dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n", 940 __func__); 941 } 942 loopcnt = 10000; 943 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) { 944 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK); 945 udelay(5); 946 } 947 if (!loopcnt) 948 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n", 949 __func__, ep->num, (ep->in ? "in" : "out")); 950} 951 952/** 953 * pch_udc_ep_fifo_flush() - Flush the endpoint fifo 954 * @ep: reference to structure of type pch_udc_ep_regs 955 * @dir: direction of endpoint 956 * 0: endpoint is OUT 957 * !0: endpoint is IN 958 */ 959static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir) 960{ 961 if (dir) { /* IN ep */ 962 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F); 963 return; 964 } 965} 966 967/** 968 * pch_udc_ep_enable() - This api enables endpoint 969 * @ep: reference to structure of type pch_udc_ep_regs 970 * @cfg: current configuration information 971 * @desc: endpoint descriptor 972 */ 973static void pch_udc_ep_enable(struct pch_udc_ep *ep, 974 struct pch_udc_cfg_data *cfg, 975 const struct usb_endpoint_descriptor *desc) 976{ 977 u32 val = 0; 978 u32 buff_size = 0; 979 980 pch_udc_ep_set_trfr_type(ep, desc->bmAttributes); 981 if (ep->in) 982 buff_size = UDC_EPIN_BUFF_SIZE; 983 else 984 buff_size = UDC_EPOUT_BUFF_SIZE; 985 pch_udc_ep_set_bufsz(ep, buff_size, ep->in); 986 pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc)); 987 pch_udc_ep_set_nak(ep); 988 pch_udc_ep_fifo_flush(ep, ep->in); 989 /* Configure the endpoint */ 990 val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT | 991 ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) << 992 UDC_CSR_NE_TYPE_SHIFT) | 993 (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) | 994 (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) | 995 (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) | 996 usb_endpoint_maxp(desc) << UDC_CSR_NE_MAX_PKT_SHIFT; 997 998 if (ep->in) 999 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num)); 1000 else 1001 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num)); 1002} 1003 1004/** 1005 * pch_udc_ep_disable() - This api disables endpoint 1006 * @ep: reference to structure of type pch_udc_ep_regs 1007 */ 1008static void pch_udc_ep_disable(struct pch_udc_ep *ep) 1009{ 1010 if (ep->in) { 1011 /* flush the fifo */ 1012 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR); 1013 /* set NAK */ 1014 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR); 1015 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN); 1016 } else { 1017 /* set NAK */ 1018 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR); 1019 } 1020 /* reset desc pointer */ 1021 pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR); 1022} 1023 1024/** 1025 * pch_udc_wait_ep_stall() - Wait EP stall. 1026 * @ep: reference to structure of type pch_udc_ep_regs 1027 */ 1028static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep) 1029{ 1030 unsigned int count = 10000; 1031 1032 /* Wait till idle */ 1033 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count) 1034 udelay(5); 1035 if (!count) 1036 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__); 1037} 1038 1039/** 1040 * pch_udc_init() - This API initializes usb device controller 1041 * @dev: Rreference to pch_udc_regs structure 1042 */ 1043static void pch_udc_init(struct pch_udc_dev *dev) 1044{ 1045 if (NULL == dev) { 1046 pr_err("%s: Invalid address\n", __func__); 1047 return; 1048 } 1049 /* Soft Reset and Reset PHY */ 1050 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR); 1051 pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR); 1052 mdelay(1); 1053 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR); 1054 pch_udc_writel(dev, 0x00, UDC_SRST_ADDR); 1055 mdelay(1); 1056 /* mask and clear all device interrupts */ 1057 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK); 1058 pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK); 1059 1060 /* mask and clear all ep interrupts */ 1061 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL); 1062 pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL); 1063 1064 /* enable dynamic CSR programmingi, self powered and device speed */ 1065 if (speed_fs) 1066 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG | 1067 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS); 1068 else /* defaul high speed */ 1069 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG | 1070 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS); 1071 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, 1072 (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) | 1073 (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) | 1074 UDC_DEVCTL_MODE | UDC_DEVCTL_BREN | 1075 UDC_DEVCTL_THE); 1076} 1077 1078/** 1079 * pch_udc_exit() - This API exit usb device controller 1080 * @dev: Reference to pch_udc_regs structure 1081 */ 1082static void pch_udc_exit(struct pch_udc_dev *dev) 1083{ 1084 /* mask all device interrupts */ 1085 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK); 1086 /* mask all ep interrupts */ 1087 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL); 1088 /* put device in disconnected state */ 1089 pch_udc_set_disconnect(dev); 1090} 1091 1092/** 1093 * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number 1094 * @gadget: Reference to the gadget driver 1095 * 1096 * Return codes: 1097 * 0: Success 1098 * -EINVAL: If the gadget passed is NULL 1099 */ 1100static int pch_udc_pcd_get_frame(struct usb_gadget *gadget) 1101{ 1102 struct pch_udc_dev *dev; 1103 1104 if (!gadget) 1105 return -EINVAL; 1106 dev = container_of(gadget, struct pch_udc_dev, gadget); 1107 return pch_udc_get_frame(dev); 1108} 1109 1110/** 1111 * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup 1112 * @gadget: Reference to the gadget driver 1113 * 1114 * Return codes: 1115 * 0: Success 1116 * -EINVAL: If the gadget passed is NULL 1117 */ 1118static int pch_udc_pcd_wakeup(struct usb_gadget *gadget) 1119{ 1120 struct pch_udc_dev *dev; 1121 unsigned long flags; 1122 1123 if (!gadget) 1124 return -EINVAL; 1125 dev = container_of(gadget, struct pch_udc_dev, gadget); 1126 spin_lock_irqsave(&dev->lock, flags); 1127 pch_udc_rmt_wakeup(dev); 1128 spin_unlock_irqrestore(&dev->lock, flags); 1129 return 0; 1130} 1131 1132/** 1133 * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device 1134 * is self powered or not 1135 * @gadget: Reference to the gadget driver 1136 * @value: Specifies self powered or not 1137 * 1138 * Return codes: 1139 * 0: Success 1140 * -EINVAL: If the gadget passed is NULL 1141 */ 1142static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value) 1143{ 1144 struct pch_udc_dev *dev; 1145 1146 if (!gadget) 1147 return -EINVAL; 1148 gadget->is_selfpowered = (value != 0); 1149 dev = container_of(gadget, struct pch_udc_dev, gadget); 1150 if (value) 1151 pch_udc_set_selfpowered(dev); 1152 else 1153 pch_udc_clear_selfpowered(dev); 1154 return 0; 1155} 1156 1157/** 1158 * pch_udc_pcd_pullup() - This API is invoked to make the device 1159 * visible/invisible to the host 1160 * @gadget: Reference to the gadget driver 1161 * @is_on: Specifies whether the pull up is made active or inactive 1162 * 1163 * Return codes: 1164 * 0: Success 1165 * -EINVAL: If the gadget passed is NULL 1166 */ 1167static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on) 1168{ 1169 struct pch_udc_dev *dev; 1170 unsigned long iflags; 1171 1172 if (!gadget) 1173 return -EINVAL; 1174 1175 dev = container_of(gadget, struct pch_udc_dev, gadget); 1176 1177 spin_lock_irqsave(&dev->lock, iflags); 1178 if (is_on) { 1179 pch_udc_reconnect(dev); 1180 } else { 1181 if (dev->driver && dev->driver->disconnect) { 1182 spin_unlock_irqrestore(&dev->lock, iflags); 1183 dev->driver->disconnect(&dev->gadget); 1184 spin_lock_irqsave(&dev->lock, iflags); 1185 } 1186 pch_udc_set_disconnect(dev); 1187 } 1188 spin_unlock_irqrestore(&dev->lock, iflags); 1189 1190 return 0; 1191} 1192 1193/** 1194 * pch_udc_pcd_vbus_session() - This API is used by a driver for an external 1195 * transceiver (or GPIO) that 1196 * detects a VBUS power session starting/ending 1197 * @gadget: Reference to the gadget driver 1198 * @is_active: specifies whether the session is starting or ending 1199 * 1200 * Return codes: 1201 * 0: Success 1202 * -EINVAL: If the gadget passed is NULL 1203 */ 1204static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active) 1205{ 1206 struct pch_udc_dev *dev; 1207 1208 if (!gadget) 1209 return -EINVAL; 1210 dev = container_of(gadget, struct pch_udc_dev, gadget); 1211 pch_udc_vbus_session(dev, is_active); 1212 return 0; 1213} 1214 1215/** 1216 * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during 1217 * SET_CONFIGURATION calls to 1218 * specify how much power the device can consume 1219 * @gadget: Reference to the gadget driver 1220 * @mA: specifies the current limit in 2mA unit 1221 * 1222 * Return codes: 1223 * -EINVAL: If the gadget passed is NULL 1224 * -EOPNOTSUPP: 1225 */ 1226static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA) 1227{ 1228 return -EOPNOTSUPP; 1229} 1230 1231static int pch_udc_start(struct usb_gadget *g, 1232 struct usb_gadget_driver *driver); 1233static int pch_udc_stop(struct usb_gadget *g); 1234 1235static const struct usb_gadget_ops pch_udc_ops = { 1236 .get_frame = pch_udc_pcd_get_frame, 1237 .wakeup = pch_udc_pcd_wakeup, 1238 .set_selfpowered = pch_udc_pcd_selfpowered, 1239 .pullup = pch_udc_pcd_pullup, 1240 .vbus_session = pch_udc_pcd_vbus_session, 1241 .vbus_draw = pch_udc_pcd_vbus_draw, 1242 .udc_start = pch_udc_start, 1243 .udc_stop = pch_udc_stop, 1244}; 1245 1246/** 1247 * pch_vbus_gpio_get_value() - This API gets value of GPIO port as VBUS status. 1248 * @dev: Reference to the driver structure 1249 * 1250 * Return value: 1251 * 1: VBUS is high 1252 * 0: VBUS is low 1253 * -1: It is not enable to detect VBUS using GPIO 1254 */ 1255static int pch_vbus_gpio_get_value(struct pch_udc_dev *dev) 1256{ 1257 int vbus = 0; 1258 1259 if (dev->vbus_gpio.port) 1260 vbus = gpiod_get_value(dev->vbus_gpio.port) ? 1 : 0; 1261 else 1262 vbus = -1; 1263 1264 return vbus; 1265} 1266 1267/** 1268 * pch_vbus_gpio_work_fall() - This API keeps watch on VBUS becoming Low. 1269 * If VBUS is Low, disconnect is processed 1270 * @irq_work: Structure for WorkQueue 1271 * 1272 */ 1273static void pch_vbus_gpio_work_fall(struct work_struct *irq_work) 1274{ 1275 struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work, 1276 struct pch_vbus_gpio_data, irq_work_fall); 1277 struct pch_udc_dev *dev = 1278 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio); 1279 int vbus_saved = -1; 1280 int vbus; 1281 int count; 1282 1283 if (!dev->vbus_gpio.port) 1284 return; 1285 1286 for (count = 0; count < (PCH_VBUS_PERIOD / PCH_VBUS_INTERVAL); 1287 count++) { 1288 vbus = pch_vbus_gpio_get_value(dev); 1289 1290 if ((vbus_saved == vbus) && (vbus == 0)) { 1291 dev_dbg(&dev->pdev->dev, "VBUS fell"); 1292 if (dev->driver 1293 && dev->driver->disconnect) { 1294 dev->driver->disconnect( 1295 &dev->gadget); 1296 } 1297 if (dev->vbus_gpio.intr) 1298 pch_udc_init(dev); 1299 else 1300 pch_udc_reconnect(dev); 1301 return; 1302 } 1303 vbus_saved = vbus; 1304 mdelay(PCH_VBUS_INTERVAL); 1305 } 1306} 1307 1308/** 1309 * pch_vbus_gpio_work_rise() - This API checks VBUS is High. 1310 * If VBUS is High, connect is processed 1311 * @irq_work: Structure for WorkQueue 1312 * 1313 */ 1314static void pch_vbus_gpio_work_rise(struct work_struct *irq_work) 1315{ 1316 struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work, 1317 struct pch_vbus_gpio_data, irq_work_rise); 1318 struct pch_udc_dev *dev = 1319 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio); 1320 int vbus; 1321 1322 if (!dev->vbus_gpio.port) 1323 return; 1324 1325 mdelay(PCH_VBUS_INTERVAL); 1326 vbus = pch_vbus_gpio_get_value(dev); 1327 1328 if (vbus == 1) { 1329 dev_dbg(&dev->pdev->dev, "VBUS rose"); 1330 pch_udc_reconnect(dev); 1331 return; 1332 } 1333} 1334 1335/** 1336 * pch_vbus_gpio_irq() - IRQ handler for GPIO interrupt for changing VBUS 1337 * @irq: Interrupt request number 1338 * @data: Reference to the device structure 1339 * 1340 * Return codes: 1341 * 0: Success 1342 * -EINVAL: GPIO port is invalid or can't be initialized. 1343 */ 1344static irqreturn_t pch_vbus_gpio_irq(int irq, void *data) 1345{ 1346 struct pch_udc_dev *dev = (struct pch_udc_dev *)data; 1347 1348 if (!dev->vbus_gpio.port || !dev->vbus_gpio.intr) 1349 return IRQ_NONE; 1350 1351 if (pch_vbus_gpio_get_value(dev)) 1352 schedule_work(&dev->vbus_gpio.irq_work_rise); 1353 else 1354 schedule_work(&dev->vbus_gpio.irq_work_fall); 1355 1356 return IRQ_HANDLED; 1357} 1358 1359/** 1360 * pch_vbus_gpio_init() - This API initializes GPIO port detecting VBUS. 1361 * @dev: Reference to the driver structure 1362 * 1363 * Return codes: 1364 * 0: Success 1365 * -EINVAL: GPIO port is invalid or can't be initialized. 1366 */ 1367static int pch_vbus_gpio_init(struct pch_udc_dev *dev) 1368{ 1369 struct device *d = &dev->pdev->dev; 1370 int err; 1371 int irq_num = 0; 1372 struct gpio_desc *gpiod; 1373 1374 dev->vbus_gpio.port = NULL; 1375 dev->vbus_gpio.intr = 0; 1376 1377 /* Retrieve the GPIO line from the USB gadget device */ 1378 gpiod = devm_gpiod_get_optional(d, NULL, GPIOD_IN); 1379 if (IS_ERR(gpiod)) 1380 return PTR_ERR(gpiod); 1381 gpiod_set_consumer_name(gpiod, "pch_vbus"); 1382 1383 dev->vbus_gpio.port = gpiod; 1384 INIT_WORK(&dev->vbus_gpio.irq_work_fall, pch_vbus_gpio_work_fall); 1385 1386 irq_num = gpiod_to_irq(gpiod); 1387 if (irq_num > 0) { 1388 irq_set_irq_type(irq_num, IRQ_TYPE_EDGE_BOTH); 1389 err = request_irq(irq_num, pch_vbus_gpio_irq, 0, 1390 "vbus_detect", dev); 1391 if (!err) { 1392 dev->vbus_gpio.intr = irq_num; 1393 INIT_WORK(&dev->vbus_gpio.irq_work_rise, 1394 pch_vbus_gpio_work_rise); 1395 } else { 1396 pr_err("%s: can't request irq %d, err: %d\n", 1397 __func__, irq_num, err); 1398 } 1399 } 1400 1401 return 0; 1402} 1403 1404/** 1405 * pch_vbus_gpio_free() - This API frees resources of GPIO port 1406 * @dev: Reference to the driver structure 1407 */ 1408static void pch_vbus_gpio_free(struct pch_udc_dev *dev) 1409{ 1410 if (dev->vbus_gpio.intr) 1411 free_irq(dev->vbus_gpio.intr, dev); 1412} 1413 1414/** 1415 * complete_req() - This API is invoked from the driver when processing 1416 * of a request is complete 1417 * @ep: Reference to the endpoint structure 1418 * @req: Reference to the request structure 1419 * @status: Indicates the success/failure of completion 1420 */ 1421static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req, 1422 int status) 1423 __releases(&dev->lock) 1424 __acquires(&dev->lock) 1425{ 1426 struct pch_udc_dev *dev; 1427 unsigned halted = ep->halted; 1428 1429 list_del_init(&req->queue); 1430 1431 /* set new status if pending */ 1432 if (req->req.status == -EINPROGRESS) 1433 req->req.status = status; 1434 else 1435 status = req->req.status; 1436 1437 dev = ep->dev; 1438 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in); 1439 ep->halted = 1; 1440 spin_unlock(&dev->lock); 1441 if (!ep->in) 1442 pch_udc_ep_clear_rrdy(ep); 1443 usb_gadget_giveback_request(&ep->ep, &req->req); 1444 spin_lock(&dev->lock); 1445 ep->halted = halted; 1446} 1447 1448/** 1449 * empty_req_queue() - This API empties the request queue of an endpoint 1450 * @ep: Reference to the endpoint structure 1451 */ 1452static void empty_req_queue(struct pch_udc_ep *ep) 1453{ 1454 struct pch_udc_request *req; 1455 1456 ep->halted = 1; 1457 while (!list_empty(&ep->queue)) { 1458 req = list_entry(ep->queue.next, struct pch_udc_request, queue); 1459 complete_req(ep, req, -ESHUTDOWN); /* Remove from list */ 1460 } 1461} 1462 1463/** 1464 * pch_udc_free_dma_chain() - This function frees the DMA chain created 1465 * for the request 1466 * @dev: Reference to the driver structure 1467 * @req: Reference to the request to be freed 1468 * 1469 * Return codes: 1470 * 0: Success 1471 */ 1472static void pch_udc_free_dma_chain(struct pch_udc_dev *dev, 1473 struct pch_udc_request *req) 1474{ 1475 struct pch_udc_data_dma_desc *td = req->td_data; 1476 unsigned i = req->chain_len; 1477 1478 dma_addr_t addr2; 1479 dma_addr_t addr = (dma_addr_t)td->next; 1480 td->next = 0x00; 1481 for (; i > 1; --i) { 1482 /* do not free first desc., will be done by free for request */ 1483 td = phys_to_virt(addr); 1484 addr2 = (dma_addr_t)td->next; 1485 dma_pool_free(dev->data_requests, td, addr); 1486 addr = addr2; 1487 } 1488 req->chain_len = 1; 1489} 1490 1491/** 1492 * pch_udc_create_dma_chain() - This function creates or reinitializes 1493 * a DMA chain 1494 * @ep: Reference to the endpoint structure 1495 * @req: Reference to the request 1496 * @buf_len: The buffer length 1497 * @gfp_flags: Flags to be used while mapping the data buffer 1498 * 1499 * Return codes: 1500 * 0: success, 1501 * -ENOMEM: dma_pool_alloc invocation fails 1502 */ 1503static int pch_udc_create_dma_chain(struct pch_udc_ep *ep, 1504 struct pch_udc_request *req, 1505 unsigned long buf_len, 1506 gfp_t gfp_flags) 1507{ 1508 struct pch_udc_data_dma_desc *td = req->td_data, *last; 1509 unsigned long bytes = req->req.length, i = 0; 1510 dma_addr_t dma_addr; 1511 unsigned len = 1; 1512 1513 if (req->chain_len > 1) 1514 pch_udc_free_dma_chain(ep->dev, req); 1515 1516 td->dataptr = req->req.dma; 1517 td->status = PCH_UDC_BS_HST_BSY; 1518 1519 for (; ; bytes -= buf_len, ++len) { 1520 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes); 1521 if (bytes <= buf_len) 1522 break; 1523 last = td; 1524 td = dma_pool_alloc(ep->dev->data_requests, gfp_flags, 1525 &dma_addr); 1526 if (!td) 1527 goto nomem; 1528 i += buf_len; 1529 td->dataptr = req->td_data->dataptr + i; 1530 last->next = dma_addr; 1531 } 1532 1533 req->td_data_last = td; 1534 td->status |= PCH_UDC_DMA_LAST; 1535 td->next = req->td_data_phys; 1536 req->chain_len = len; 1537 return 0; 1538 1539nomem: 1540 if (len > 1) { 1541 req->chain_len = len; 1542 pch_udc_free_dma_chain(ep->dev, req); 1543 } 1544 req->chain_len = 1; 1545 return -ENOMEM; 1546} 1547 1548/** 1549 * prepare_dma() - This function creates and initializes the DMA chain 1550 * for the request 1551 * @ep: Reference to the endpoint structure 1552 * @req: Reference to the request 1553 * @gfp: Flag to be used while mapping the data buffer 1554 * 1555 * Return codes: 1556 * 0: Success 1557 * Other 0: linux error number on failure 1558 */ 1559static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req, 1560 gfp_t gfp) 1561{ 1562 int retval; 1563 1564 /* Allocate and create a DMA chain */ 1565 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp); 1566 if (retval) { 1567 pr_err("%s: could not create DMA chain:%d\n", __func__, retval); 1568 return retval; 1569 } 1570 if (ep->in) 1571 req->td_data->status = (req->td_data->status & 1572 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY; 1573 return 0; 1574} 1575 1576/** 1577 * process_zlp() - This function process zero length packets 1578 * from the gadget driver 1579 * @ep: Reference to the endpoint structure 1580 * @req: Reference to the request 1581 */ 1582static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req) 1583{ 1584 struct pch_udc_dev *dev = ep->dev; 1585 1586 /* IN zlp's are handled by hardware */ 1587 complete_req(ep, req, 0); 1588 1589 /* if set_config or set_intf is waiting for ack by zlp 1590 * then set CSR_DONE 1591 */ 1592 if (dev->set_cfg_not_acked) { 1593 pch_udc_set_csr_done(dev); 1594 dev->set_cfg_not_acked = 0; 1595 } 1596 /* setup command is ACK'ed now by zlp */ 1597 if (!dev->stall && dev->waiting_zlp_ack) { 1598 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX])); 1599 dev->waiting_zlp_ack = 0; 1600 } 1601} 1602 1603/** 1604 * pch_udc_start_rxrequest() - This function starts the receive requirement. 1605 * @ep: Reference to the endpoint structure 1606 * @req: Reference to the request structure 1607 */ 1608static void pch_udc_start_rxrequest(struct pch_udc_ep *ep, 1609 struct pch_udc_request *req) 1610{ 1611 struct pch_udc_data_dma_desc *td_data; 1612 1613 pch_udc_clear_dma(ep->dev, DMA_DIR_RX); 1614 td_data = req->td_data; 1615 /* Set the status bits for all descriptors */ 1616 while (1) { 1617 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) | 1618 PCH_UDC_BS_HST_RDY; 1619 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST) 1620 break; 1621 td_data = phys_to_virt(td_data->next); 1622 } 1623 /* Write the descriptor pointer */ 1624 pch_udc_ep_set_ddptr(ep, req->td_data_phys); 1625 req->dma_going = 1; 1626 pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num); 1627 pch_udc_set_dma(ep->dev, DMA_DIR_RX); 1628 pch_udc_ep_clear_nak(ep); 1629 pch_udc_ep_set_rrdy(ep); 1630} 1631 1632/** 1633 * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called 1634 * from gadget driver 1635 * @usbep: Reference to the USB endpoint structure 1636 * @desc: Reference to the USB endpoint descriptor structure 1637 * 1638 * Return codes: 1639 * 0: Success 1640 * -EINVAL: 1641 * -ESHUTDOWN: 1642 */ 1643static int pch_udc_pcd_ep_enable(struct usb_ep *usbep, 1644 const struct usb_endpoint_descriptor *desc) 1645{ 1646 struct pch_udc_ep *ep; 1647 struct pch_udc_dev *dev; 1648 unsigned long iflags; 1649 1650 if (!usbep || (usbep->name == ep0_string) || !desc || 1651 (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize) 1652 return -EINVAL; 1653 1654 ep = container_of(usbep, struct pch_udc_ep, ep); 1655 dev = ep->dev; 1656 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN)) 1657 return -ESHUTDOWN; 1658 spin_lock_irqsave(&dev->lock, iflags); 1659 ep->ep.desc = desc; 1660 ep->halted = 0; 1661 pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc); 1662 ep->ep.maxpacket = usb_endpoint_maxp(desc); 1663 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num)); 1664 spin_unlock_irqrestore(&dev->lock, iflags); 1665 return 0; 1666} 1667 1668/** 1669 * pch_udc_pcd_ep_disable() - This API disables endpoint and is called 1670 * from gadget driver 1671 * @usbep: Reference to the USB endpoint structure 1672 * 1673 * Return codes: 1674 * 0: Success 1675 * -EINVAL: 1676 */ 1677static int pch_udc_pcd_ep_disable(struct usb_ep *usbep) 1678{ 1679 struct pch_udc_ep *ep; 1680 unsigned long iflags; 1681 1682 if (!usbep) 1683 return -EINVAL; 1684 1685 ep = container_of(usbep, struct pch_udc_ep, ep); 1686 if ((usbep->name == ep0_string) || !ep->ep.desc) 1687 return -EINVAL; 1688 1689 spin_lock_irqsave(&ep->dev->lock, iflags); 1690 empty_req_queue(ep); 1691 ep->halted = 1; 1692 pch_udc_ep_disable(ep); 1693 pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num)); 1694 ep->ep.desc = NULL; 1695 INIT_LIST_HEAD(&ep->queue); 1696 spin_unlock_irqrestore(&ep->dev->lock, iflags); 1697 return 0; 1698} 1699 1700/** 1701 * pch_udc_alloc_request() - This function allocates request structure. 1702 * It is called by gadget driver 1703 * @usbep: Reference to the USB endpoint structure 1704 * @gfp: Flag to be used while allocating memory 1705 * 1706 * Return codes: 1707 * NULL: Failure 1708 * Allocated address: Success 1709 */ 1710static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep, 1711 gfp_t gfp) 1712{ 1713 struct pch_udc_request *req; 1714 struct pch_udc_ep *ep; 1715 struct pch_udc_data_dma_desc *dma_desc; 1716 1717 if (!usbep) 1718 return NULL; 1719 ep = container_of(usbep, struct pch_udc_ep, ep); 1720 req = kzalloc(sizeof *req, gfp); 1721 if (!req) 1722 return NULL; 1723 req->req.dma = DMA_ADDR_INVALID; 1724 INIT_LIST_HEAD(&req->queue); 1725 if (!ep->dev->dma_addr) 1726 return &req->req; 1727 /* ep0 in requests are allocated from data pool here */ 1728 dma_desc = dma_pool_alloc(ep->dev->data_requests, gfp, 1729 &req->td_data_phys); 1730 if (NULL == dma_desc) { 1731 kfree(req); 1732 return NULL; 1733 } 1734 /* prevent from using desc. - set HOST BUSY */ 1735 dma_desc->status |= PCH_UDC_BS_HST_BSY; 1736 dma_desc->dataptr = lower_32_bits(DMA_ADDR_INVALID); 1737 req->td_data = dma_desc; 1738 req->td_data_last = dma_desc; 1739 req->chain_len = 1; 1740 return &req->req; 1741} 1742 1743/** 1744 * pch_udc_free_request() - This function frees request structure. 1745 * It is called by gadget driver 1746 * @usbep: Reference to the USB endpoint structure 1747 * @usbreq: Reference to the USB request 1748 */ 1749static void pch_udc_free_request(struct usb_ep *usbep, 1750 struct usb_request *usbreq) 1751{ 1752 struct pch_udc_ep *ep; 1753 struct pch_udc_request *req; 1754 struct pch_udc_dev *dev; 1755 1756 if (!usbep || !usbreq) 1757 return; 1758 ep = container_of(usbep, struct pch_udc_ep, ep); 1759 req = container_of(usbreq, struct pch_udc_request, req); 1760 dev = ep->dev; 1761 if (!list_empty(&req->queue)) 1762 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n", 1763 __func__, usbep->name, req); 1764 if (req->td_data != NULL) { 1765 if (req->chain_len > 1) 1766 pch_udc_free_dma_chain(ep->dev, req); 1767 dma_pool_free(ep->dev->data_requests, req->td_data, 1768 req->td_data_phys); 1769 } 1770 kfree(req); 1771} 1772 1773/** 1774 * pch_udc_pcd_queue() - This function queues a request packet. It is called 1775 * by gadget driver 1776 * @usbep: Reference to the USB endpoint structure 1777 * @usbreq: Reference to the USB request 1778 * @gfp: Flag to be used while mapping the data buffer 1779 * 1780 * Return codes: 1781 * 0: Success 1782 * linux error number: Failure 1783 */ 1784static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq, 1785 gfp_t gfp) 1786{ 1787 int retval = 0; 1788 struct pch_udc_ep *ep; 1789 struct pch_udc_dev *dev; 1790 struct pch_udc_request *req; 1791 unsigned long iflags; 1792 1793 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf) 1794 return -EINVAL; 1795 ep = container_of(usbep, struct pch_udc_ep, ep); 1796 dev = ep->dev; 1797 if (!ep->ep.desc && ep->num) 1798 return -EINVAL; 1799 req = container_of(usbreq, struct pch_udc_request, req); 1800 if (!list_empty(&req->queue)) 1801 return -EINVAL; 1802 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN)) 1803 return -ESHUTDOWN; 1804 spin_lock_irqsave(&dev->lock, iflags); 1805 /* map the buffer for dma */ 1806 retval = usb_gadget_map_request(&dev->gadget, usbreq, ep->in); 1807 if (retval) 1808 goto probe_end; 1809 if (usbreq->length > 0) { 1810 retval = prepare_dma(ep, req, GFP_ATOMIC); 1811 if (retval) 1812 goto probe_end; 1813 } 1814 usbreq->actual = 0; 1815 usbreq->status = -EINPROGRESS; 1816 req->dma_done = 0; 1817 if (list_empty(&ep->queue) && !ep->halted) { 1818 /* no pending transfer, so start this req */ 1819 if (!usbreq->length) { 1820 process_zlp(ep, req); 1821 retval = 0; 1822 goto probe_end; 1823 } 1824 if (!ep->in) { 1825 pch_udc_start_rxrequest(ep, req); 1826 } else { 1827 /* 1828 * For IN trfr the descriptors will be programmed and 1829 * P bit will be set when 1830 * we get an IN token 1831 */ 1832 pch_udc_wait_ep_stall(ep); 1833 pch_udc_ep_clear_nak(ep); 1834 pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num)); 1835 } 1836 } 1837 /* Now add this request to the ep's pending requests */ 1838 if (req != NULL) 1839 list_add_tail(&req->queue, &ep->queue); 1840 1841probe_end: 1842 spin_unlock_irqrestore(&dev->lock, iflags); 1843 return retval; 1844} 1845 1846/** 1847 * pch_udc_pcd_dequeue() - This function de-queues a request packet. 1848 * It is called by gadget driver 1849 * @usbep: Reference to the USB endpoint structure 1850 * @usbreq: Reference to the USB request 1851 * 1852 * Return codes: 1853 * 0: Success 1854 * linux error number: Failure 1855 */ 1856static int pch_udc_pcd_dequeue(struct usb_ep *usbep, 1857 struct usb_request *usbreq) 1858{ 1859 struct pch_udc_ep *ep; 1860 struct pch_udc_request *req; 1861 unsigned long flags; 1862 int ret = -EINVAL; 1863 1864 ep = container_of(usbep, struct pch_udc_ep, ep); 1865 if (!usbep || !usbreq || (!ep->ep.desc && ep->num)) 1866 return ret; 1867 req = container_of(usbreq, struct pch_udc_request, req); 1868 spin_lock_irqsave(&ep->dev->lock, flags); 1869 /* make sure it's still queued on this endpoint */ 1870 list_for_each_entry(req, &ep->queue, queue) { 1871 if (&req->req == usbreq) { 1872 pch_udc_ep_set_nak(ep); 1873 if (!list_empty(&req->queue)) 1874 complete_req(ep, req, -ECONNRESET); 1875 ret = 0; 1876 break; 1877 } 1878 } 1879 spin_unlock_irqrestore(&ep->dev->lock, flags); 1880 return ret; 1881} 1882 1883/** 1884 * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt 1885 * feature 1886 * @usbep: Reference to the USB endpoint structure 1887 * @halt: Specifies whether to set or clear the feature 1888 * 1889 * Return codes: 1890 * 0: Success 1891 * linux error number: Failure 1892 */ 1893static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt) 1894{ 1895 struct pch_udc_ep *ep; 1896 unsigned long iflags; 1897 int ret; 1898 1899 if (!usbep) 1900 return -EINVAL; 1901 ep = container_of(usbep, struct pch_udc_ep, ep); 1902 if (!ep->ep.desc && !ep->num) 1903 return -EINVAL; 1904 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN)) 1905 return -ESHUTDOWN; 1906 spin_lock_irqsave(&udc_stall_spinlock, iflags); 1907 if (list_empty(&ep->queue)) { 1908 if (halt) { 1909 if (ep->num == PCH_UDC_EP0) 1910 ep->dev->stall = 1; 1911 pch_udc_ep_set_stall(ep); 1912 pch_udc_enable_ep_interrupts( 1913 ep->dev, PCH_UDC_EPINT(ep->in, ep->num)); 1914 } else { 1915 pch_udc_ep_clear_stall(ep); 1916 } 1917 ret = 0; 1918 } else { 1919 ret = -EAGAIN; 1920 } 1921 spin_unlock_irqrestore(&udc_stall_spinlock, iflags); 1922 return ret; 1923} 1924 1925/** 1926 * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint 1927 * halt feature 1928 * @usbep: Reference to the USB endpoint structure 1929 * 1930 * Return codes: 1931 * 0: Success 1932 * linux error number: Failure 1933 */ 1934static int pch_udc_pcd_set_wedge(struct usb_ep *usbep) 1935{ 1936 struct pch_udc_ep *ep; 1937 unsigned long iflags; 1938 int ret; 1939 1940 if (!usbep) 1941 return -EINVAL; 1942 ep = container_of(usbep, struct pch_udc_ep, ep); 1943 if (!ep->ep.desc && !ep->num) 1944 return -EINVAL; 1945 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN)) 1946 return -ESHUTDOWN; 1947 spin_lock_irqsave(&udc_stall_spinlock, iflags); 1948 if (!list_empty(&ep->queue)) { 1949 ret = -EAGAIN; 1950 } else { 1951 if (ep->num == PCH_UDC_EP0) 1952 ep->dev->stall = 1; 1953 pch_udc_ep_set_stall(ep); 1954 pch_udc_enable_ep_interrupts(ep->dev, 1955 PCH_UDC_EPINT(ep->in, ep->num)); 1956 ep->dev->prot_stall = 1; 1957 ret = 0; 1958 } 1959 spin_unlock_irqrestore(&udc_stall_spinlock, iflags); 1960 return ret; 1961} 1962 1963/** 1964 * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint 1965 * @usbep: Reference to the USB endpoint structure 1966 */ 1967static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep) 1968{ 1969 struct pch_udc_ep *ep; 1970 1971 if (!usbep) 1972 return; 1973 1974 ep = container_of(usbep, struct pch_udc_ep, ep); 1975 if (ep->ep.desc || !ep->num) 1976 pch_udc_ep_fifo_flush(ep, ep->in); 1977} 1978 1979static const struct usb_ep_ops pch_udc_ep_ops = { 1980 .enable = pch_udc_pcd_ep_enable, 1981 .disable = pch_udc_pcd_ep_disable, 1982 .alloc_request = pch_udc_alloc_request, 1983 .free_request = pch_udc_free_request, 1984 .queue = pch_udc_pcd_queue, 1985 .dequeue = pch_udc_pcd_dequeue, 1986 .set_halt = pch_udc_pcd_set_halt, 1987 .set_wedge = pch_udc_pcd_set_wedge, 1988 .fifo_status = NULL, 1989 .fifo_flush = pch_udc_pcd_fifo_flush, 1990}; 1991 1992/** 1993 * pch_udc_init_setup_buff() - This function initializes the SETUP buffer 1994 * @td_stp: Reference to the SETP buffer structure 1995 */ 1996static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp) 1997{ 1998 static u32 pky_marker; 1999 2000 if (!td_stp) 2001 return; 2002 td_stp->reserved = ++pky_marker; 2003 memset(&td_stp->request, 0xFF, sizeof td_stp->request); 2004 td_stp->status = PCH_UDC_BS_HST_RDY; 2005} 2006 2007/** 2008 * pch_udc_start_next_txrequest() - This function starts 2009 * the next transmission requirement 2010 * @ep: Reference to the endpoint structure 2011 */ 2012static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep) 2013{ 2014 struct pch_udc_request *req; 2015 struct pch_udc_data_dma_desc *td_data; 2016 2017 if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P) 2018 return; 2019 2020 if (list_empty(&ep->queue)) 2021 return; 2022 2023 /* next request */ 2024 req = list_entry(ep->queue.next, struct pch_udc_request, queue); 2025 if (req->dma_going) 2026 return; 2027 if (!req->td_data) 2028 return; 2029 pch_udc_wait_ep_stall(ep); 2030 req->dma_going = 1; 2031 pch_udc_ep_set_ddptr(ep, 0); 2032 td_data = req->td_data; 2033 while (1) { 2034 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) | 2035 PCH_UDC_BS_HST_RDY; 2036 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST) 2037 break; 2038 td_data = phys_to_virt(td_data->next); 2039 } 2040 pch_udc_ep_set_ddptr(ep, req->td_data_phys); 2041 pch_udc_set_dma(ep->dev, DMA_DIR_TX); 2042 pch_udc_ep_set_pd(ep); 2043 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num)); 2044 pch_udc_ep_clear_nak(ep); 2045} 2046 2047/** 2048 * pch_udc_complete_transfer() - This function completes a transfer 2049 * @ep: Reference to the endpoint structure 2050 */ 2051static void pch_udc_complete_transfer(struct pch_udc_ep *ep) 2052{ 2053 struct pch_udc_request *req; 2054 struct pch_udc_dev *dev = ep->dev; 2055 2056 if (list_empty(&ep->queue)) 2057 return; 2058 req = list_entry(ep->queue.next, struct pch_udc_request, queue); 2059 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) != 2060 PCH_UDC_BS_DMA_DONE) 2061 return; 2062 if ((req->td_data_last->status & PCH_UDC_RXTX_STS) != 2063 PCH_UDC_RTS_SUCC) { 2064 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) " 2065 "epstatus=0x%08x\n", 2066 (req->td_data_last->status & PCH_UDC_RXTX_STS), 2067 (int)(ep->epsts)); 2068 return; 2069 } 2070 2071 req->req.actual = req->req.length; 2072 req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST; 2073 req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST; 2074 complete_req(ep, req, 0); 2075 req->dma_going = 0; 2076 if (!list_empty(&ep->queue)) { 2077 pch_udc_wait_ep_stall(ep); 2078 pch_udc_ep_clear_nak(ep); 2079 pch_udc_enable_ep_interrupts(ep->dev, 2080 PCH_UDC_EPINT(ep->in, ep->num)); 2081 } else { 2082 pch_udc_disable_ep_interrupts(ep->dev, 2083 PCH_UDC_EPINT(ep->in, ep->num)); 2084 } 2085} 2086 2087/** 2088 * pch_udc_complete_receiver() - This function completes a receiver 2089 * @ep: Reference to the endpoint structure 2090 */ 2091static void pch_udc_complete_receiver(struct pch_udc_ep *ep) 2092{ 2093 struct pch_udc_request *req; 2094 struct pch_udc_dev *dev = ep->dev; 2095 unsigned int count; 2096 struct pch_udc_data_dma_desc *td; 2097 dma_addr_t addr; 2098 2099 if (list_empty(&ep->queue)) 2100 return; 2101 /* next request */ 2102 req = list_entry(ep->queue.next, struct pch_udc_request, queue); 2103 pch_udc_clear_dma(ep->dev, DMA_DIR_RX); 2104 pch_udc_ep_set_ddptr(ep, 0); 2105 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) == 2106 PCH_UDC_BS_DMA_DONE) 2107 td = req->td_data_last; 2108 else 2109 td = req->td_data; 2110 2111 while (1) { 2112 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) { 2113 dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x " 2114 "epstatus=0x%08x\n", 2115 (req->td_data->status & PCH_UDC_RXTX_STS), 2116 (int)(ep->epsts)); 2117 return; 2118 } 2119 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE) 2120 if (td->status & PCH_UDC_DMA_LAST) { 2121 count = td->status & PCH_UDC_RXTX_BYTES; 2122 break; 2123 } 2124 if (td == req->td_data_last) { 2125 dev_err(&dev->pdev->dev, "Not complete RX descriptor"); 2126 return; 2127 } 2128 addr = (dma_addr_t)td->next; 2129 td = phys_to_virt(addr); 2130 } 2131 /* on 64k packets the RXBYTES field is zero */ 2132 if (!count && (req->req.length == UDC_DMA_MAXPACKET)) 2133 count = UDC_DMA_MAXPACKET; 2134 req->td_data->status |= PCH_UDC_DMA_LAST; 2135 td->status |= PCH_UDC_BS_HST_BSY; 2136 2137 req->dma_going = 0; 2138 req->req.actual = count; 2139 complete_req(ep, req, 0); 2140 /* If there is a new/failed requests try that now */ 2141 if (!list_empty(&ep->queue)) { 2142 req = list_entry(ep->queue.next, struct pch_udc_request, queue); 2143 pch_udc_start_rxrequest(ep, req); 2144 } 2145} 2146 2147/** 2148 * pch_udc_svc_data_in() - This function process endpoint interrupts 2149 * for IN endpoints 2150 * @dev: Reference to the device structure 2151 * @ep_num: Endpoint that generated the interrupt 2152 */ 2153static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num) 2154{ 2155 u32 epsts; 2156 struct pch_udc_ep *ep; 2157 2158 ep = &dev->ep[UDC_EPIN_IDX(ep_num)]; 2159 epsts = ep->epsts; 2160 ep->epsts = 0; 2161 2162 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE | 2163 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY | 2164 UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE))) 2165 return; 2166 if ((epsts & UDC_EPSTS_BNA)) 2167 return; 2168 if (epsts & UDC_EPSTS_HE) 2169 return; 2170 if (epsts & UDC_EPSTS_RSS) { 2171 pch_udc_ep_set_stall(ep); 2172 pch_udc_enable_ep_interrupts(ep->dev, 2173 PCH_UDC_EPINT(ep->in, ep->num)); 2174 } 2175 if (epsts & UDC_EPSTS_RCS) { 2176 if (!dev->prot_stall) { 2177 pch_udc_ep_clear_stall(ep); 2178 } else { 2179 pch_udc_ep_set_stall(ep); 2180 pch_udc_enable_ep_interrupts(ep->dev, 2181 PCH_UDC_EPINT(ep->in, ep->num)); 2182 } 2183 } 2184 if (epsts & UDC_EPSTS_TDC) 2185 pch_udc_complete_transfer(ep); 2186 /* On IN interrupt, provide data if we have any */ 2187 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) && 2188 !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY)) 2189 pch_udc_start_next_txrequest(ep); 2190} 2191 2192/** 2193 * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint 2194 * @dev: Reference to the device structure 2195 * @ep_num: Endpoint that generated the interrupt 2196 */ 2197static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num) 2198{ 2199 u32 epsts; 2200 struct pch_udc_ep *ep; 2201 struct pch_udc_request *req = NULL; 2202 2203 ep = &dev->ep[UDC_EPOUT_IDX(ep_num)]; 2204 epsts = ep->epsts; 2205 ep->epsts = 0; 2206 2207 if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) { 2208 /* next request */ 2209 req = list_entry(ep->queue.next, struct pch_udc_request, 2210 queue); 2211 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) != 2212 PCH_UDC_BS_DMA_DONE) { 2213 if (!req->dma_going) 2214 pch_udc_start_rxrequest(ep, req); 2215 return; 2216 } 2217 } 2218 if (epsts & UDC_EPSTS_HE) 2219 return; 2220 if (epsts & UDC_EPSTS_RSS) { 2221 pch_udc_ep_set_stall(ep); 2222 pch_udc_enable_ep_interrupts(ep->dev, 2223 PCH_UDC_EPINT(ep->in, ep->num)); 2224 } 2225 if (epsts & UDC_EPSTS_RCS) { 2226 if (!dev->prot_stall) { 2227 pch_udc_ep_clear_stall(ep); 2228 } else { 2229 pch_udc_ep_set_stall(ep); 2230 pch_udc_enable_ep_interrupts(ep->dev, 2231 PCH_UDC_EPINT(ep->in, ep->num)); 2232 } 2233 } 2234 if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) == 2235 UDC_EPSTS_OUT_DATA) { 2236 if (ep->dev->prot_stall == 1) { 2237 pch_udc_ep_set_stall(ep); 2238 pch_udc_enable_ep_interrupts(ep->dev, 2239 PCH_UDC_EPINT(ep->in, ep->num)); 2240 } else { 2241 pch_udc_complete_receiver(ep); 2242 } 2243 } 2244 if (list_empty(&ep->queue)) 2245 pch_udc_set_dma(dev, DMA_DIR_RX); 2246} 2247 2248static int pch_udc_gadget_setup(struct pch_udc_dev *dev) 2249 __must_hold(&dev->lock) 2250{ 2251 int rc; 2252 2253 /* In some cases we can get an interrupt before driver gets setup */ 2254 if (!dev->driver) 2255 return -ESHUTDOWN; 2256 2257 spin_unlock(&dev->lock); 2258 rc = dev->driver->setup(&dev->gadget, &dev->setup_data); 2259 spin_lock(&dev->lock); 2260 return rc; 2261} 2262 2263/** 2264 * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts 2265 * @dev: Reference to the device structure 2266 */ 2267static void pch_udc_svc_control_in(struct pch_udc_dev *dev) 2268{ 2269 u32 epsts; 2270 struct pch_udc_ep *ep; 2271 struct pch_udc_ep *ep_out; 2272 2273 ep = &dev->ep[UDC_EP0IN_IDX]; 2274 ep_out = &dev->ep[UDC_EP0OUT_IDX]; 2275 epsts = ep->epsts; 2276 ep->epsts = 0; 2277 2278 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE | 2279 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY | 2280 UDC_EPSTS_XFERDONE))) 2281 return; 2282 if ((epsts & UDC_EPSTS_BNA)) 2283 return; 2284 if (epsts & UDC_EPSTS_HE) 2285 return; 2286 if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) { 2287 pch_udc_complete_transfer(ep); 2288 pch_udc_clear_dma(dev, DMA_DIR_RX); 2289 ep_out->td_data->status = (ep_out->td_data->status & 2290 ~PCH_UDC_BUFF_STS) | 2291 PCH_UDC_BS_HST_RDY; 2292 pch_udc_ep_clear_nak(ep_out); 2293 pch_udc_set_dma(dev, DMA_DIR_RX); 2294 pch_udc_ep_set_rrdy(ep_out); 2295 } 2296 /* On IN interrupt, provide data if we have any */ 2297 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) && 2298 !(epsts & UDC_EPSTS_TXEMPTY)) 2299 pch_udc_start_next_txrequest(ep); 2300} 2301 2302/** 2303 * pch_udc_svc_control_out() - Routine that handle Control 2304 * OUT endpoint interrupts 2305 * @dev: Reference to the device structure 2306 */ 2307static void pch_udc_svc_control_out(struct pch_udc_dev *dev) 2308 __releases(&dev->lock) 2309 __acquires(&dev->lock) 2310{ 2311 u32 stat; 2312 int setup_supported; 2313 struct pch_udc_ep *ep; 2314 2315 ep = &dev->ep[UDC_EP0OUT_IDX]; 2316 stat = ep->epsts; 2317 ep->epsts = 0; 2318 2319 /* If setup data */ 2320 if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) == 2321 UDC_EPSTS_OUT_SETUP) { 2322 dev->stall = 0; 2323 dev->ep[UDC_EP0IN_IDX].halted = 0; 2324 dev->ep[UDC_EP0OUT_IDX].halted = 0; 2325 dev->setup_data = ep->td_stp->request; 2326 pch_udc_init_setup_buff(ep->td_stp); 2327 pch_udc_clear_dma(dev, DMA_DIR_RX); 2328 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]), 2329 dev->ep[UDC_EP0IN_IDX].in); 2330 if ((dev->setup_data.bRequestType & USB_DIR_IN)) 2331 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep; 2332 else /* OUT */ 2333 dev->gadget.ep0 = &ep->ep; 2334 /* If Mass storage Reset */ 2335 if ((dev->setup_data.bRequestType == 0x21) && 2336 (dev->setup_data.bRequest == 0xFF)) 2337 dev->prot_stall = 0; 2338 /* call gadget with setup data received */ 2339 setup_supported = pch_udc_gadget_setup(dev); 2340 2341 if (dev->setup_data.bRequestType & USB_DIR_IN) { 2342 ep->td_data->status = (ep->td_data->status & 2343 ~PCH_UDC_BUFF_STS) | 2344 PCH_UDC_BS_HST_RDY; 2345 pch_udc_ep_set_ddptr(ep, ep->td_data_phys); 2346 } 2347 /* ep0 in returns data on IN phase */ 2348 if (setup_supported >= 0 && setup_supported < 2349 UDC_EP0IN_MAX_PKT_SIZE) { 2350 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX])); 2351 /* Gadget would have queued a request when 2352 * we called the setup */ 2353 if (!(dev->setup_data.bRequestType & USB_DIR_IN)) { 2354 pch_udc_set_dma(dev, DMA_DIR_RX); 2355 pch_udc_ep_clear_nak(ep); 2356 } 2357 } else if (setup_supported < 0) { 2358 /* if unsupported request, then stall */ 2359 pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX])); 2360 pch_udc_enable_ep_interrupts(ep->dev, 2361 PCH_UDC_EPINT(ep->in, ep->num)); 2362 dev->stall = 0; 2363 pch_udc_set_dma(dev, DMA_DIR_RX); 2364 } else { 2365 dev->waiting_zlp_ack = 1; 2366 } 2367 } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) == 2368 UDC_EPSTS_OUT_DATA) && !dev->stall) { 2369 pch_udc_clear_dma(dev, DMA_DIR_RX); 2370 pch_udc_ep_set_ddptr(ep, 0); 2371 if (!list_empty(&ep->queue)) { 2372 ep->epsts = stat; 2373 pch_udc_svc_data_out(dev, PCH_UDC_EP0); 2374 } 2375 pch_udc_set_dma(dev, DMA_DIR_RX); 2376 } 2377 pch_udc_ep_set_rrdy(ep); 2378} 2379 2380 2381/** 2382 * pch_udc_postsvc_epinters() - This function enables end point interrupts 2383 * and clears NAK status 2384 * @dev: Reference to the device structure 2385 * @ep_num: End point number 2386 */ 2387static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num) 2388{ 2389 struct pch_udc_ep *ep = &dev->ep[UDC_EPIN_IDX(ep_num)]; 2390 if (list_empty(&ep->queue)) 2391 return; 2392 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num)); 2393 pch_udc_ep_clear_nak(ep); 2394} 2395 2396/** 2397 * pch_udc_read_all_epstatus() - This function read all endpoint status 2398 * @dev: Reference to the device structure 2399 * @ep_intr: Status of endpoint interrupt 2400 */ 2401static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr) 2402{ 2403 int i; 2404 struct pch_udc_ep *ep; 2405 2406 for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) { 2407 /* IN */ 2408 if (ep_intr & (0x1 << i)) { 2409 ep = &dev->ep[UDC_EPIN_IDX(i)]; 2410 ep->epsts = pch_udc_read_ep_status(ep); 2411 pch_udc_clear_ep_status(ep, ep->epsts); 2412 } 2413 /* OUT */ 2414 if (ep_intr & (0x10000 << i)) { 2415 ep = &dev->ep[UDC_EPOUT_IDX(i)]; 2416 ep->epsts = pch_udc_read_ep_status(ep); 2417 pch_udc_clear_ep_status(ep, ep->epsts); 2418 } 2419 } 2420} 2421 2422/** 2423 * pch_udc_activate_control_ep() - This function enables the control endpoints 2424 * for traffic after a reset 2425 * @dev: Reference to the device structure 2426 */ 2427static void pch_udc_activate_control_ep(struct pch_udc_dev *dev) 2428{ 2429 struct pch_udc_ep *ep; 2430 u32 val; 2431 2432 /* Setup the IN endpoint */ 2433 ep = &dev->ep[UDC_EP0IN_IDX]; 2434 pch_udc_clear_ep_control(ep); 2435 pch_udc_ep_fifo_flush(ep, ep->in); 2436 pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in); 2437 pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE); 2438 /* Initialize the IN EP Descriptor */ 2439 ep->td_data = NULL; 2440 ep->td_stp = NULL; 2441 ep->td_data_phys = 0; 2442 ep->td_stp_phys = 0; 2443 2444 /* Setup the OUT endpoint */ 2445 ep = &dev->ep[UDC_EP0OUT_IDX]; 2446 pch_udc_clear_ep_control(ep); 2447 pch_udc_ep_fifo_flush(ep, ep->in); 2448 pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in); 2449 pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE); 2450 val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT; 2451 pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX); 2452 2453 /* Initialize the SETUP buffer */ 2454 pch_udc_init_setup_buff(ep->td_stp); 2455 /* Write the pointer address of dma descriptor */ 2456 pch_udc_ep_set_subptr(ep, ep->td_stp_phys); 2457 /* Write the pointer address of Setup descriptor */ 2458 pch_udc_ep_set_ddptr(ep, ep->td_data_phys); 2459 2460 /* Initialize the dma descriptor */ 2461 ep->td_data->status = PCH_UDC_DMA_LAST; 2462 ep->td_data->dataptr = dev->dma_addr; 2463 ep->td_data->next = ep->td_data_phys; 2464 2465 pch_udc_ep_clear_nak(ep); 2466} 2467 2468 2469/** 2470 * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt 2471 * @dev: Reference to driver structure 2472 */ 2473static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev) 2474{ 2475 struct pch_udc_ep *ep; 2476 int i; 2477 2478 pch_udc_clear_dma(dev, DMA_DIR_TX); 2479 pch_udc_clear_dma(dev, DMA_DIR_RX); 2480 /* Mask all endpoint interrupts */ 2481 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL); 2482 /* clear all endpoint interrupts */ 2483 pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL); 2484 2485 for (i = 0; i < PCH_UDC_EP_NUM; i++) { 2486 ep = &dev->ep[i]; 2487 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK); 2488 pch_udc_clear_ep_control(ep); 2489 pch_udc_ep_set_ddptr(ep, 0); 2490 pch_udc_write_csr(ep->dev, 0x00, i); 2491 } 2492 dev->stall = 0; 2493 dev->prot_stall = 0; 2494 dev->waiting_zlp_ack = 0; 2495 dev->set_cfg_not_acked = 0; 2496 2497 /* disable ep to empty req queue. Skip the control EP's */ 2498 for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) { 2499 ep = &dev->ep[i]; 2500 pch_udc_ep_set_nak(ep); 2501 pch_udc_ep_fifo_flush(ep, ep->in); 2502 /* Complete request queue */ 2503 empty_req_queue(ep); 2504 } 2505 if (dev->driver) { 2506 spin_unlock(&dev->lock); 2507 usb_gadget_udc_reset(&dev->gadget, dev->driver); 2508 spin_lock(&dev->lock); 2509 } 2510} 2511 2512/** 2513 * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration 2514 * done interrupt 2515 * @dev: Reference to driver structure 2516 */ 2517static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev) 2518{ 2519 u32 dev_stat, dev_speed; 2520 u32 speed = USB_SPEED_FULL; 2521 2522 dev_stat = pch_udc_read_device_status(dev); 2523 dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >> 2524 UDC_DEVSTS_ENUM_SPEED_SHIFT; 2525 switch (dev_speed) { 2526 case UDC_DEVSTS_ENUM_SPEED_HIGH: 2527 speed = USB_SPEED_HIGH; 2528 break; 2529 case UDC_DEVSTS_ENUM_SPEED_FULL: 2530 speed = USB_SPEED_FULL; 2531 break; 2532 case UDC_DEVSTS_ENUM_SPEED_LOW: 2533 speed = USB_SPEED_LOW; 2534 break; 2535 default: 2536 BUG(); 2537 } 2538 dev->gadget.speed = speed; 2539 pch_udc_activate_control_ep(dev); 2540 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0); 2541 pch_udc_set_dma(dev, DMA_DIR_TX); 2542 pch_udc_set_dma(dev, DMA_DIR_RX); 2543 pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX])); 2544 2545 /* enable device interrupts */ 2546 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US | 2547 UDC_DEVINT_ES | UDC_DEVINT_ENUM | 2548 UDC_DEVINT_SI | UDC_DEVINT_SC); 2549} 2550 2551/** 2552 * pch_udc_svc_intf_interrupt() - This function handles a set interface 2553 * interrupt 2554 * @dev: Reference to driver structure 2555 */ 2556static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev) 2557{ 2558 u32 reg, dev_stat = 0; 2559 int i; 2560 2561 dev_stat = pch_udc_read_device_status(dev); 2562 dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >> 2563 UDC_DEVSTS_INTF_SHIFT; 2564 dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >> 2565 UDC_DEVSTS_ALT_SHIFT; 2566 dev->set_cfg_not_acked = 1; 2567 /* Construct the usb request for gadget driver and inform it */ 2568 memset(&dev->setup_data, 0 , sizeof dev->setup_data); 2569 dev->setup_data.bRequest = USB_REQ_SET_INTERFACE; 2570 dev->setup_data.bRequestType = USB_RECIP_INTERFACE; 2571 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt); 2572 dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf); 2573 /* programm the Endpoint Cfg registers */ 2574 /* Only one end point cfg register */ 2575 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX); 2576 reg = (reg & ~UDC_CSR_NE_INTF_MASK) | 2577 (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT); 2578 reg = (reg & ~UDC_CSR_NE_ALT_MASK) | 2579 (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT); 2580 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX); 2581 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) { 2582 /* clear stall bits */ 2583 pch_udc_ep_clear_stall(&(dev->ep[i])); 2584 dev->ep[i].halted = 0; 2585 } 2586 dev->stall = 0; 2587 pch_udc_gadget_setup(dev); 2588} 2589 2590/** 2591 * pch_udc_svc_cfg_interrupt() - This function handles a set configuration 2592 * interrupt 2593 * @dev: Reference to driver structure 2594 */ 2595static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev) 2596{ 2597 int i; 2598 u32 reg, dev_stat = 0; 2599 2600 dev_stat = pch_udc_read_device_status(dev); 2601 dev->set_cfg_not_acked = 1; 2602 dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >> 2603 UDC_DEVSTS_CFG_SHIFT; 2604 /* make usb request for gadget driver */ 2605 memset(&dev->setup_data, 0 , sizeof dev->setup_data); 2606 dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION; 2607 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg); 2608 /* program the NE registers */ 2609 /* Only one end point cfg register */ 2610 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX); 2611 reg = (reg & ~UDC_CSR_NE_CFG_MASK) | 2612 (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT); 2613 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX); 2614 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) { 2615 /* clear stall bits */ 2616 pch_udc_ep_clear_stall(&(dev->ep[i])); 2617 dev->ep[i].halted = 0; 2618 } 2619 dev->stall = 0; 2620 2621 /* call gadget zero with setup data received */ 2622 pch_udc_gadget_setup(dev); 2623} 2624 2625/** 2626 * pch_udc_dev_isr() - This function services device interrupts 2627 * by invoking appropriate routines. 2628 * @dev: Reference to the device structure 2629 * @dev_intr: The Device interrupt status. 2630 */ 2631static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr) 2632{ 2633 int vbus; 2634 2635 /* USB Reset Interrupt */ 2636 if (dev_intr & UDC_DEVINT_UR) { 2637 pch_udc_svc_ur_interrupt(dev); 2638 dev_dbg(&dev->pdev->dev, "USB_RESET\n"); 2639 } 2640 /* Enumeration Done Interrupt */ 2641 if (dev_intr & UDC_DEVINT_ENUM) { 2642 pch_udc_svc_enum_interrupt(dev); 2643 dev_dbg(&dev->pdev->dev, "USB_ENUM\n"); 2644 } 2645 /* Set Interface Interrupt */ 2646 if (dev_intr & UDC_DEVINT_SI) 2647 pch_udc_svc_intf_interrupt(dev); 2648 /* Set Config Interrupt */ 2649 if (dev_intr & UDC_DEVINT_SC) 2650 pch_udc_svc_cfg_interrupt(dev); 2651 /* USB Suspend interrupt */ 2652 if (dev_intr & UDC_DEVINT_US) { 2653 if (dev->driver 2654 && dev->driver->suspend) { 2655 spin_unlock(&dev->lock); 2656 dev->driver->suspend(&dev->gadget); 2657 spin_lock(&dev->lock); 2658 } 2659 2660 vbus = pch_vbus_gpio_get_value(dev); 2661 if ((dev->vbus_session == 0) 2662 && (vbus != 1)) { 2663 if (dev->driver && dev->driver->disconnect) { 2664 spin_unlock(&dev->lock); 2665 dev->driver->disconnect(&dev->gadget); 2666 spin_lock(&dev->lock); 2667 } 2668 pch_udc_reconnect(dev); 2669 } else if ((dev->vbus_session == 0) 2670 && (vbus == 1) 2671 && !dev->vbus_gpio.intr) 2672 schedule_work(&dev->vbus_gpio.irq_work_fall); 2673 2674 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n"); 2675 } 2676 /* Clear the SOF interrupt, if enabled */ 2677 if (dev_intr & UDC_DEVINT_SOF) 2678 dev_dbg(&dev->pdev->dev, "SOF\n"); 2679 /* ES interrupt, IDLE > 3ms on the USB */ 2680 if (dev_intr & UDC_DEVINT_ES) 2681 dev_dbg(&dev->pdev->dev, "ES\n"); 2682 /* RWKP interrupt */ 2683 if (dev_intr & UDC_DEVINT_RWKP) 2684 dev_dbg(&dev->pdev->dev, "RWKP\n"); 2685} 2686 2687/** 2688 * pch_udc_isr() - This function handles interrupts from the PCH USB Device 2689 * @irq: Interrupt request number 2690 * @pdev: Reference to the device structure 2691 */ 2692static irqreturn_t pch_udc_isr(int irq, void *pdev) 2693{ 2694 struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev; 2695 u32 dev_intr, ep_intr; 2696 int i; 2697 2698 dev_intr = pch_udc_read_device_interrupts(dev); 2699 ep_intr = pch_udc_read_ep_interrupts(dev); 2700 2701 /* For a hot plug, this find that the controller is hung up. */ 2702 if (dev_intr == ep_intr) 2703 if (dev_intr == pch_udc_readl(dev, UDC_DEVCFG_ADDR)) { 2704 dev_dbg(&dev->pdev->dev, "UDC: Hung up\n"); 2705 /* The controller is reset */ 2706 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR); 2707 return IRQ_HANDLED; 2708 } 2709 if (dev_intr) 2710 /* Clear device interrupts */ 2711 pch_udc_write_device_interrupts(dev, dev_intr); 2712 if (ep_intr) 2713 /* Clear ep interrupts */ 2714 pch_udc_write_ep_interrupts(dev, ep_intr); 2715 if (!dev_intr && !ep_intr) 2716 return IRQ_NONE; 2717 spin_lock(&dev->lock); 2718 if (dev_intr) 2719 pch_udc_dev_isr(dev, dev_intr); 2720 if (ep_intr) { 2721 pch_udc_read_all_epstatus(dev, ep_intr); 2722 /* Process Control In interrupts, if present */ 2723 if (ep_intr & UDC_EPINT_IN_EP0) { 2724 pch_udc_svc_control_in(dev); 2725 pch_udc_postsvc_epinters(dev, 0); 2726 } 2727 /* Process Control Out interrupts, if present */ 2728 if (ep_intr & UDC_EPINT_OUT_EP0) 2729 pch_udc_svc_control_out(dev); 2730 /* Process data in end point interrupts */ 2731 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) { 2732 if (ep_intr & (1 << i)) { 2733 pch_udc_svc_data_in(dev, i); 2734 pch_udc_postsvc_epinters(dev, i); 2735 } 2736 } 2737 /* Process data out end point interrupts */ 2738 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT + 2739 PCH_UDC_USED_EP_NUM); i++) 2740 if (ep_intr & (1 << i)) 2741 pch_udc_svc_data_out(dev, i - 2742 UDC_EPINT_OUT_SHIFT); 2743 } 2744 spin_unlock(&dev->lock); 2745 return IRQ_HANDLED; 2746} 2747 2748/** 2749 * pch_udc_setup_ep0() - This function enables control endpoint for traffic 2750 * @dev: Reference to the device structure 2751 */ 2752static void pch_udc_setup_ep0(struct pch_udc_dev *dev) 2753{ 2754 /* enable ep0 interrupts */ 2755 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | 2756 UDC_EPINT_OUT_EP0); 2757 /* enable device interrupts */ 2758 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US | 2759 UDC_DEVINT_ES | UDC_DEVINT_ENUM | 2760 UDC_DEVINT_SI | UDC_DEVINT_SC); 2761} 2762 2763/** 2764 * pch_udc_pcd_reinit() - This API initializes the endpoint structures 2765 * @dev: Reference to the driver structure 2766 */ 2767static void pch_udc_pcd_reinit(struct pch_udc_dev *dev) 2768{ 2769 const char *const ep_string[] = { 2770 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out", 2771 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out", 2772 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out", 2773 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out", 2774 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out", 2775 "ep15in", "ep15out", 2776 }; 2777 int i; 2778 2779 dev->gadget.speed = USB_SPEED_UNKNOWN; 2780 INIT_LIST_HEAD(&dev->gadget.ep_list); 2781 2782 /* Initialize the endpoints structures */ 2783 memset(dev->ep, 0, sizeof dev->ep); 2784 for (i = 0; i < PCH_UDC_EP_NUM; i++) { 2785 struct pch_udc_ep *ep = &dev->ep[i]; 2786 ep->dev = dev; 2787 ep->halted = 1; 2788 ep->num = i / 2; 2789 ep->in = ~i & 1; 2790 ep->ep.name = ep_string[i]; 2791 ep->ep.ops = &pch_udc_ep_ops; 2792 if (ep->in) { 2793 ep->offset_addr = ep->num * UDC_EP_REG_SHIFT; 2794 ep->ep.caps.dir_in = true; 2795 } else { 2796 ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) * 2797 UDC_EP_REG_SHIFT; 2798 ep->ep.caps.dir_out = true; 2799 } 2800 if (i == UDC_EP0IN_IDX || i == UDC_EP0OUT_IDX) { 2801 ep->ep.caps.type_control = true; 2802 } else { 2803 ep->ep.caps.type_iso = true; 2804 ep->ep.caps.type_bulk = true; 2805 ep->ep.caps.type_int = true; 2806 } 2807 /* need to set ep->ep.maxpacket and set Default Configuration?*/ 2808 usb_ep_set_maxpacket_limit(&ep->ep, UDC_BULK_MAX_PKT_SIZE); 2809 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); 2810 INIT_LIST_HEAD(&ep->queue); 2811 } 2812 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IDX].ep, UDC_EP0IN_MAX_PKT_SIZE); 2813 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IDX].ep, UDC_EP0OUT_MAX_PKT_SIZE); 2814 2815 /* remove ep0 in and out from the list. They have own pointer */ 2816 list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list); 2817 list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list); 2818 2819 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep; 2820 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); 2821} 2822 2823/** 2824 * pch_udc_pcd_init() - This API initializes the driver structure 2825 * @dev: Reference to the driver structure 2826 * 2827 * Return codes: 2828 * 0: Success 2829 * -ERRNO: All kind of errors when retrieving VBUS GPIO 2830 */ 2831static int pch_udc_pcd_init(struct pch_udc_dev *dev) 2832{ 2833 int ret; 2834 2835 pch_udc_init(dev); 2836 pch_udc_pcd_reinit(dev); 2837 2838 ret = pch_vbus_gpio_init(dev); 2839 if (ret) 2840 pch_udc_exit(dev); 2841 return ret; 2842} 2843 2844/** 2845 * init_dma_pools() - create dma pools during initialization 2846 * @dev: reference to struct pci_dev 2847 */ 2848static int init_dma_pools(struct pch_udc_dev *dev) 2849{ 2850 struct pch_udc_stp_dma_desc *td_stp; 2851 struct pch_udc_data_dma_desc *td_data; 2852 void *ep0out_buf; 2853 2854 /* DMA setup */ 2855 dev->data_requests = dma_pool_create("data_requests", &dev->pdev->dev, 2856 sizeof(struct pch_udc_data_dma_desc), 0, 0); 2857 if (!dev->data_requests) { 2858 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n", 2859 __func__); 2860 return -ENOMEM; 2861 } 2862 2863 /* dma desc for setup data */ 2864 dev->stp_requests = dma_pool_create("setup requests", &dev->pdev->dev, 2865 sizeof(struct pch_udc_stp_dma_desc), 0, 0); 2866 if (!dev->stp_requests) { 2867 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n", 2868 __func__); 2869 return -ENOMEM; 2870 } 2871 /* setup */ 2872 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL, 2873 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys); 2874 if (!td_stp) { 2875 dev_err(&dev->pdev->dev, 2876 "%s: can't allocate setup dma descriptor\n", __func__); 2877 return -ENOMEM; 2878 } 2879 dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp; 2880 2881 /* data: 0 packets !? */ 2882 td_data = dma_pool_alloc(dev->data_requests, GFP_KERNEL, 2883 &dev->ep[UDC_EP0OUT_IDX].td_data_phys); 2884 if (!td_data) { 2885 dev_err(&dev->pdev->dev, 2886 "%s: can't allocate data dma descriptor\n", __func__); 2887 return -ENOMEM; 2888 } 2889 dev->ep[UDC_EP0OUT_IDX].td_data = td_data; 2890 dev->ep[UDC_EP0IN_IDX].td_stp = NULL; 2891 dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0; 2892 dev->ep[UDC_EP0IN_IDX].td_data = NULL; 2893 dev->ep[UDC_EP0IN_IDX].td_data_phys = 0; 2894 2895 ep0out_buf = devm_kzalloc(&dev->pdev->dev, UDC_EP0OUT_BUFF_SIZE * 4, 2896 GFP_KERNEL); 2897 if (!ep0out_buf) 2898 return -ENOMEM; 2899 dev->dma_addr = dma_map_single(&dev->pdev->dev, ep0out_buf, 2900 UDC_EP0OUT_BUFF_SIZE * 4, 2901 DMA_FROM_DEVICE); 2902 return dma_mapping_error(&dev->pdev->dev, dev->dma_addr); 2903} 2904 2905static int pch_udc_start(struct usb_gadget *g, 2906 struct usb_gadget_driver *driver) 2907{ 2908 struct pch_udc_dev *dev = to_pch_udc(g); 2909 2910 dev->driver = driver; 2911 2912 /* get ready for ep0 traffic */ 2913 pch_udc_setup_ep0(dev); 2914 2915 /* clear SD */ 2916 if ((pch_vbus_gpio_get_value(dev) != 0) || !dev->vbus_gpio.intr) 2917 pch_udc_clear_disconnect(dev); 2918 2919 dev->connected = 1; 2920 return 0; 2921} 2922 2923static int pch_udc_stop(struct usb_gadget *g) 2924{ 2925 struct pch_udc_dev *dev = to_pch_udc(g); 2926 2927 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK); 2928 2929 /* Assures that there are no pending requests with this driver */ 2930 dev->driver = NULL; 2931 dev->connected = 0; 2932 2933 /* set SD */ 2934 pch_udc_set_disconnect(dev); 2935 2936 return 0; 2937} 2938 2939static void pch_vbus_gpio_remove_table(void *table) 2940{ 2941 gpiod_remove_lookup_table(table); 2942} 2943 2944static int pch_vbus_gpio_add_table(struct device *d, void *table) 2945{ 2946 gpiod_add_lookup_table(table); 2947 return devm_add_action_or_reset(d, pch_vbus_gpio_remove_table, table); 2948} 2949 2950static struct gpiod_lookup_table pch_udc_minnow_vbus_gpio_table = { 2951 .dev_id = "0000:02:02.4", 2952 .table = { 2953 GPIO_LOOKUP("sch_gpio.33158", 12, NULL, GPIO_ACTIVE_HIGH), 2954 {} 2955 }, 2956}; 2957 2958static int pch_udc_minnow_platform_init(struct device *d) 2959{ 2960 return pch_vbus_gpio_add_table(d, &pch_udc_minnow_vbus_gpio_table); 2961} 2962 2963static int pch_udc_quark_platform_init(struct device *d) 2964{ 2965 struct pch_udc_dev *dev = dev_get_drvdata(d); 2966 2967 dev->bar = PCH_UDC_PCI_BAR_QUARK_X1000; 2968 return 0; 2969} 2970 2971static void pch_udc_shutdown(struct pci_dev *pdev) 2972{ 2973 struct pch_udc_dev *dev = pci_get_drvdata(pdev); 2974 2975 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK); 2976 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL); 2977 2978 /* disable the pullup so the host will think we're gone */ 2979 pch_udc_set_disconnect(dev); 2980} 2981 2982static void pch_udc_remove(struct pci_dev *pdev) 2983{ 2984 struct pch_udc_dev *dev = pci_get_drvdata(pdev); 2985 2986 usb_del_gadget_udc(&dev->gadget); 2987 2988 /* gadget driver must not be registered */ 2989 if (dev->driver) 2990 dev_err(&pdev->dev, 2991 "%s: gadget driver still bound!!!\n", __func__); 2992 /* dma pool cleanup */ 2993 dma_pool_destroy(dev->data_requests); 2994 2995 if (dev->stp_requests) { 2996 /* cleanup DMA desc's for ep0in */ 2997 if (dev->ep[UDC_EP0OUT_IDX].td_stp) { 2998 dma_pool_free(dev->stp_requests, 2999 dev->ep[UDC_EP0OUT_IDX].td_stp, 3000 dev->ep[UDC_EP0OUT_IDX].td_stp_phys); 3001 } 3002 if (dev->ep[UDC_EP0OUT_IDX].td_data) { 3003 dma_pool_free(dev->stp_requests, 3004 dev->ep[UDC_EP0OUT_IDX].td_data, 3005 dev->ep[UDC_EP0OUT_IDX].td_data_phys); 3006 } 3007 dma_pool_destroy(dev->stp_requests); 3008 } 3009 3010 if (dev->dma_addr) 3011 dma_unmap_single(&dev->pdev->dev, dev->dma_addr, 3012 UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE); 3013 3014 pch_vbus_gpio_free(dev); 3015 3016 pch_udc_exit(dev); 3017} 3018 3019static int __maybe_unused pch_udc_suspend(struct device *d) 3020{ 3021 struct pch_udc_dev *dev = dev_get_drvdata(d); 3022 3023 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK); 3024 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL); 3025 3026 return 0; 3027} 3028 3029static int __maybe_unused pch_udc_resume(struct device *d) 3030{ 3031 return 0; 3032} 3033 3034static SIMPLE_DEV_PM_OPS(pch_udc_pm, pch_udc_suspend, pch_udc_resume); 3035 3036typedef int (*platform_init_fn)(struct device *); 3037 3038static int pch_udc_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3039{ 3040 platform_init_fn platform_init = (platform_init_fn)id->driver_data; 3041 int retval; 3042 struct pch_udc_dev *dev; 3043 3044 /* init */ 3045 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 3046 if (!dev) 3047 return -ENOMEM; 3048 3049 /* pci setup */ 3050 retval = pcim_enable_device(pdev); 3051 if (retval) 3052 return retval; 3053 3054 dev->bar = PCH_UDC_PCI_BAR; 3055 dev->pdev = pdev; 3056 pci_set_drvdata(pdev, dev); 3057 3058 /* Platform specific hook */ 3059 if (platform_init) { 3060 retval = platform_init(&pdev->dev); 3061 if (retval) 3062 return retval; 3063 } 3064 3065 /* PCI resource allocation */ 3066 retval = pcim_iomap_regions(pdev, BIT(dev->bar), pci_name(pdev)); 3067 if (retval) 3068 return retval; 3069 3070 dev->base_addr = pcim_iomap_table(pdev)[dev->bar]; 3071 3072 /* initialize the hardware */ 3073 retval = pch_udc_pcd_init(dev); 3074 if (retval) 3075 return retval; 3076 3077 pci_enable_msi(pdev); 3078 3079 retval = devm_request_irq(&pdev->dev, pdev->irq, pch_udc_isr, 3080 IRQF_SHARED, KBUILD_MODNAME, dev); 3081 if (retval) { 3082 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__, 3083 pdev->irq); 3084 goto finished; 3085 } 3086 3087 pci_set_master(pdev); 3088 pci_try_set_mwi(pdev); 3089 3090 /* device struct setup */ 3091 spin_lock_init(&dev->lock); 3092 dev->gadget.ops = &pch_udc_ops; 3093 3094 retval = init_dma_pools(dev); 3095 if (retval) 3096 goto finished; 3097 3098 dev->gadget.name = KBUILD_MODNAME; 3099 dev->gadget.max_speed = USB_SPEED_HIGH; 3100 3101 /* Put the device in disconnected state till a driver is bound */ 3102 pch_udc_set_disconnect(dev); 3103 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget); 3104 if (retval) 3105 goto finished; 3106 return 0; 3107 3108finished: 3109 pch_udc_remove(pdev); 3110 return retval; 3111} 3112 3113static const struct pci_device_id pch_udc_pcidev_id[] = { 3114 { 3115 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC), 3116 .class = PCI_CLASS_SERIAL_USB_DEVICE, 3117 .class_mask = 0xffffffff, 3118 .driver_data = (kernel_ulong_t)&pch_udc_quark_platform_init, 3119 }, 3120 { 3121 PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC, 3122 PCI_VENDOR_ID_CIRCUITCO, PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD), 3123 .class = PCI_CLASS_SERIAL_USB_DEVICE, 3124 .class_mask = 0xffffffff, 3125 .driver_data = (kernel_ulong_t)&pch_udc_minnow_platform_init, 3126 }, 3127 { 3128 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC), 3129 .class = PCI_CLASS_SERIAL_USB_DEVICE, 3130 .class_mask = 0xffffffff, 3131 }, 3132 { 3133 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC), 3134 .class = PCI_CLASS_SERIAL_USB_DEVICE, 3135 .class_mask = 0xffffffff, 3136 }, 3137 { 3138 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7831_IOH_UDC), 3139 .class = PCI_CLASS_SERIAL_USB_DEVICE, 3140 .class_mask = 0xffffffff, 3141 }, 3142 { 0 }, 3143}; 3144 3145MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id); 3146 3147static struct pci_driver pch_udc_driver = { 3148 .name = KBUILD_MODNAME, 3149 .id_table = pch_udc_pcidev_id, 3150 .probe = pch_udc_probe, 3151 .remove = pch_udc_remove, 3152 .shutdown = pch_udc_shutdown, 3153 .driver = { 3154 .pm = &pch_udc_pm, 3155 }, 3156}; 3157 3158module_pci_driver(pch_udc_driver); 3159 3160MODULE_DESCRIPTION("Intel EG20T USB Device Controller"); 3161MODULE_AUTHOR("LAPIS Semiconductor, <tomoya-linux@dsn.lapis-semi.com>"); 3162MODULE_LICENSE("GPL"); 3163