1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Toshiba TC86C001 ("Goku-S") USB Device Controller driver
4 *
5 * Copyright (C) 2000-2002 Lineo
6 *      by Stuart Lynne, Tom Rushworth, and Bruce Balden
7 * Copyright (C) 2002 Toshiba Corporation
8 * Copyright (C) 2003 MontaVista Software (source@mvista.com)
9 */
10
11/*
12 * PCI BAR 0 points to these registers.
13 */
14struct goku_udc_regs {
15	/* irq management */
16	u32	int_status;		/* 0x000 */
17	u32	int_enable;
18#define INT_SUSPEND		0x00001		/* or resume */
19#define INT_USBRESET		0x00002
20#define INT_ENDPOINT0		0x00004
21#define INT_SETUP		0x00008
22#define INT_STATUS		0x00010
23#define INT_STATUSNAK		0x00020
24#define INT_EPxDATASET(n)	(0x00020 << (n))	/* 0 < n < 4 */
25#	define INT_EP1DATASET		0x00040
26#	define INT_EP2DATASET		0x00080
27#	define INT_EP3DATASET		0x00100
28#define INT_EPnNAK(n)		(0x00100 << (n))	/* 0 < n < 4 */
29#	define INT_EP1NAK		0x00200
30#	define INT_EP2NAK		0x00400
31#	define INT_EP3NAK		0x00800
32#define INT_SOF			0x01000
33#define INT_ERR			0x02000
34#define INT_MSTWRSET		0x04000
35#define INT_MSTWREND		0x08000
36#define INT_MSTWRTMOUT		0x10000
37#define INT_MSTRDEND		0x20000
38#define INT_SYSERROR		0x40000
39#define INT_PWRDETECT		0x80000
40
41#define	INT_DEVWIDE \
42	(INT_PWRDETECT|INT_SYSERROR/*|INT_ERR*/|INT_USBRESET|INT_SUSPEND)
43#define	INT_EP0 \
44	(INT_SETUP|INT_ENDPOINT0/*|INT_STATUS*/|INT_STATUSNAK)
45
46	u32	dma_master;
47#define MST_EOPB_DIS		0x0800
48#define MST_EOPB_ENA		0x0400
49#define MST_TIMEOUT_DIS		0x0200
50#define MST_TIMEOUT_ENA		0x0100
51#define MST_RD_EOPB		0x0080		/* write-only */
52#define MST_RD_RESET		0x0040
53#define MST_WR_RESET		0x0020
54#define MST_RD_ENA		0x0004		/* 1:start, 0:ignore */
55#define MST_WR_ENA		0x0002		/* 1:start, 0:ignore */
56#define MST_CONNECTION		0x0001		/* 0 for ep1out/ep2in */
57
58#define MST_R_BITS		(MST_EOPB_DIS|MST_EOPB_ENA \
59					|MST_RD_ENA|MST_RD_RESET)
60#define MST_W_BITS		(MST_TIMEOUT_DIS|MST_TIMEOUT_ENA \
61					|MST_WR_ENA|MST_WR_RESET)
62#define MST_RW_BITS		(MST_R_BITS|MST_W_BITS \
63					|MST_CONNECTION)
64
65/* these values assume (dma_master & MST_CONNECTION) == 0 */
66#define UDC_MSTWR_ENDPOINT        1
67#define UDC_MSTRD_ENDPOINT        2
68
69	/* dma master write */
70	u32	out_dma_start;
71	u32	out_dma_end;
72	u32	out_dma_current;
73
74	/* dma master read */
75	u32	in_dma_start;
76	u32	in_dma_end;
77	u32	in_dma_current;
78
79	u32	power_detect;
80#define PW_DETECT		0x04
81#define PW_RESETB		0x02
82#define PW_PULLUP		0x01
83
84	u8	_reserved0 [0x1d8];
85
86	/* endpoint registers */
87	u32	ep_fifo [4];		/* 0x200 */
88	u8	_reserved1 [0x10];
89	u32	ep_mode [4];		/* only 1-3 valid */
90	u8	_reserved2 [0x10];
91
92	u32	ep_status [4];
93#define EPxSTATUS_TOGGLE	0x40
94#define EPxSTATUS_SUSPEND	0x20
95#define EPxSTATUS_EP_MASK	(0x07<<2)
96#	define EPxSTATUS_EP_READY	(0<<2)
97#	define EPxSTATUS_EP_DATAIN	(1<<2)
98#	define EPxSTATUS_EP_FULL	(2<<2)
99#	define EPxSTATUS_EP_TX_ERR	(3<<2)
100#	define EPxSTATUS_EP_RX_ERR	(4<<2)
101#	define EPxSTATUS_EP_BUSY	(5<<2)
102#	define EPxSTATUS_EP_STALL	(6<<2)
103#	define EPxSTATUS_EP_INVALID	(7<<2)
104#define EPxSTATUS_FIFO_DISABLE	0x02
105#define EPxSTATUS_STAGE_ERROR	0x01
106
107	u8	_reserved3 [0x10];
108	u32	EPxSizeLA[4];
109#define PACKET_ACTIVE		(1<<7)
110#define DATASIZE		0x7f
111	u8	_reserved3a [0x10];
112	u32	EPxSizeLB[4];		/* only 1,2 valid */
113	u8	_reserved3b [0x10];
114	u32	EPxSizeHA[4];		/* only 1-3 valid */
115	u8	_reserved3c [0x10];
116	u32	EPxSizeHB[4];		/* only 1,2 valid */
117	u8	_reserved4[0x30];
118
119	/* SETUP packet contents */
120	u32	bRequestType;		/* 0x300 */
121	u32	bRequest;
122	u32	wValueL;
123	u32	wValueH;
124	u32	wIndexL;
125	u32	wIndexH;
126	u32	wLengthL;
127	u32	wLengthH;
128
129	/* command interaction/handshaking */
130	u32	SetupRecv;		/* 0x320 */
131	u32	CurrConfig;
132	u32	StdRequest;
133	u32	Request;
134	u32	DataSet;
135#define DATASET_A(epnum)	(1<<(2*(epnum)))
136#define DATASET_B(epnum)	(2<<(2*(epnum)))
137#define DATASET_AB(epnum)	(3<<(2*(epnum)))
138	u8	_reserved5[4];
139
140	u32	UsbState;
141#define USBSTATE_CONFIGURED	0x04
142#define USBSTATE_ADDRESSED	0x02
143#define USBSTATE_DEFAULT	0x01
144
145	u32	EOP;
146
147	u32	Command;		/* 0x340 */
148#define COMMAND_SETDATA0	2
149#define COMMAND_RESET		3
150#define COMMAND_STALL		4
151#define COMMAND_INVALID		5
152#define COMMAND_FIFO_DISABLE	7
153#define COMMAND_FIFO_ENABLE	8
154#define COMMAND_INIT_DESCRIPTOR	9
155#define COMMAND_FIFO_CLEAR	10	/* also stall */
156#define COMMAND_STALL_CLEAR	11
157#define COMMAND_EP(n)		((n) << 4)
158
159	u32	EPxSingle;
160	u8	_reserved6[4];
161	u32	EPxBCS;
162	u8	_reserved7[8];
163	u32	IntControl;
164#define ICONTROL_STATUSNAK	1
165	u8	_reserved8[4];
166
167	u32	reqmode;	// 0x360 standard request mode, low 8 bits
168#define G_REQMODE_SET_INTF	(1<<7)
169#define G_REQMODE_GET_INTF	(1<<6)
170#define G_REQMODE_SET_CONF	(1<<5)
171#define G_REQMODE_GET_CONF	(1<<4)
172#define G_REQMODE_GET_DESC	(1<<3)
173#define G_REQMODE_SET_FEAT	(1<<2)
174#define G_REQMODE_CLEAR_FEAT	(1<<1)
175#define G_REQMODE_GET_STATUS	(1<<0)
176
177	u32	ReqMode;
178	u8	_reserved9[0x18];
179	u32	PortStatus;		/* 0x380 */
180	u8	_reserved10[8];
181	u32	address;
182	u32	buff_test;
183	u8	_reserved11[4];
184	u32	UsbReady;
185	u8	_reserved12[4];
186	u32	SetDescStall;		/* 0x3a0 */
187	u8	_reserved13[0x45c];
188
189	/* hardware could handle limited GET_DESCRIPTOR duties */
190#define	DESC_LEN	0x80
191	u32	descriptors[DESC_LEN];	/* 0x800 */
192	u8	_reserved14[0x600];
193
194} __attribute__ ((packed));
195
196#define	MAX_FIFO_SIZE	64
197#define	MAX_EP0_SIZE	8		/* ep0 fifo is bigger, though */
198
199
200/*-------------------------------------------------------------------------*/
201
202/* DRIVER DATA STRUCTURES and UTILITIES */
203
204struct goku_ep {
205	struct usb_ep				ep;
206	struct goku_udc				*dev;
207	unsigned long				irqs;
208
209	unsigned				num:8,
210						dma:1,
211						is_in:1,
212						stopped:1;
213
214	/* analogous to a host-side qh */
215	struct list_head			queue;
216
217	u32 __iomem				*reg_fifo;
218	u32 __iomem				*reg_mode;
219	u32 __iomem				*reg_status;
220};
221
222struct goku_request {
223	struct usb_request		req;
224	struct list_head		queue;
225
226	unsigned			mapped:1;
227};
228
229enum ep0state {
230	EP0_DISCONNECT,		/* no host */
231	EP0_IDLE,		/* between STATUS ack and SETUP report */
232	EP0_IN, EP0_OUT,	/* data stage */
233	EP0_STATUS,		/* status stage */
234	EP0_STALL,		/* data or status stages */
235	EP0_SUSPEND,		/* usb suspend */
236};
237
238struct goku_udc {
239	/* each pci device provides one gadget, several endpoints */
240	struct usb_gadget		gadget;
241	spinlock_t			lock;
242	struct goku_ep			ep[4];
243	struct usb_gadget_driver	*driver;
244
245	enum ep0state			ep0state;
246	unsigned			got_irq:1,
247					got_region:1,
248					req_config:1,
249					configured:1,
250					enabled:1;
251
252	/* pci state used to access those endpoints */
253	struct pci_dev			*pdev;
254	struct goku_udc_regs __iomem	*regs;
255	u32				int_enable;
256
257	/* statistics... */
258	unsigned long			irqs;
259};
260#define to_goku_udc(g)		(container_of((g), struct goku_udc, gadget))
261
262/*-------------------------------------------------------------------------*/
263
264#define xprintk(dev,level,fmt,args...) \
265	printk(level "%s %s: " fmt , driver_name , \
266			pci_name(dev->pdev) , ## args)
267
268#ifdef DEBUG
269#define DBG(dev,fmt,args...) \
270	xprintk(dev , KERN_DEBUG , fmt , ## args)
271#else
272#define DBG(dev,fmt,args...) \
273	do { } while (0)
274#endif /* DEBUG */
275
276#ifdef VERBOSE
277#define VDBG DBG
278#else
279#define VDBG(dev,fmt,args...) \
280	do { } while (0)
281#endif	/* VERBOSE */
282
283#define ERROR(dev,fmt,args...) \
284	xprintk(dev , KERN_ERR , fmt , ## args)
285#define WARNING(dev,fmt,args...) \
286	xprintk(dev , KERN_WARNING , fmt , ## args)
287#define INFO(dev,fmt,args...) \
288	xprintk(dev , KERN_INFO , fmt , ## args)
289
290