1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms
4 *
5 * This is a small driver for the dwc3 to provide the glue logic
6 * to configure the controller. Tested on STi platforms.
7 *
8 * Copyright (C) 2014 Stmicroelectronics
9 *
10 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 * Contributors: Aymen Bouattay <aymen.bouattay@st.com>
12 *               Peter Griffin <peter.griffin@linaro.org>
13 *
14 * Inspired by dwc3-omap.c and dwc3-exynos.c.
15 */
16
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/ioport.h>
21#include <linux/kernel.h>
22#include <linux/mfd/syscon.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/platform_device.h>
27#include <linux/slab.h>
28#include <linux/regmap.h>
29#include <linux/reset.h>
30#include <linux/pinctrl/consumer.h>
31#include <linux/usb/of.h>
32
33#include "core.h"
34#include "io.h"
35
36/* glue registers */
37#define CLKRST_CTRL		0x00
38#define AUX_CLK_EN		BIT(0)
39#define SW_PIPEW_RESET_N	BIT(4)
40#define EXT_CFG_RESET_N		BIT(8)
41/*
42 * 1'b0 : The host controller complies with the xHCI revision 0.96
43 * 1'b1 : The host controller complies with the xHCI revision 1.0
44 */
45#define XHCI_REVISION		BIT(12)
46
47#define USB2_VBUS_MNGMNT_SEL1	0x2C
48/*
49 * For all fields in USB2_VBUS_MNGMNT_SEL1
50 * 2���b00 : Override value from Reg 0x30 is selected
51 * 2���b01 : utmiotg_<signal_name> from usb3_top is selected
52 * 2���b10 : pipew_<signal_name> from PIPEW instance is selected
53 * 2���b11 : value is 1'b0
54 */
55#define USB2_VBUS_REG30		0x0
56#define USB2_VBUS_UTMIOTG	0x1
57#define USB2_VBUS_PIPEW		0x2
58#define USB2_VBUS_ZERO		0x3
59
60#define SEL_OVERRIDE_VBUSVALID(n)	(n << 0)
61#define SEL_OVERRIDE_POWERPRESENT(n)	(n << 4)
62#define SEL_OVERRIDE_BVALID(n)		(n << 8)
63
64/* Static DRD configuration */
65#define USB3_CONTROL_MASK		0xf77
66
67#define USB3_DEVICE_NOT_HOST		BIT(0)
68#define USB3_FORCE_VBUSVALID		BIT(1)
69#define USB3_DELAY_VBUSVALID		BIT(2)
70#define USB3_SEL_FORCE_OPMODE		BIT(4)
71#define USB3_FORCE_OPMODE(n)		(n << 5)
72#define USB3_SEL_FORCE_DPPULLDOWN2	BIT(8)
73#define USB3_FORCE_DPPULLDOWN2		BIT(9)
74#define USB3_SEL_FORCE_DMPULLDOWN2	BIT(10)
75#define USB3_FORCE_DMPULLDOWN2		BIT(11)
76
77/**
78 * struct st_dwc3 - dwc3-st driver private structure
79 * @dev:		device pointer
80 * @glue_base:		ioaddr for the glue registers
81 * @regmap:		regmap pointer for getting syscfg
82 * @syscfg_reg_off:	usb syscfg control offset
83 * @dr_mode:		drd static host/device config
84 * @rstc_pwrdn:		rest controller for powerdown signal
85 * @rstc_rst:		reset controller for softreset signal
86 */
87
88struct st_dwc3 {
89	struct device *dev;
90	void __iomem *glue_base;
91	struct regmap *regmap;
92	int syscfg_reg_off;
93	enum usb_dr_mode dr_mode;
94	struct reset_control *rstc_pwrdn;
95	struct reset_control *rstc_rst;
96};
97
98static inline u32 st_dwc3_readl(void __iomem *base, u32 offset)
99{
100	return readl_relaxed(base + offset);
101}
102
103static inline void st_dwc3_writel(void __iomem *base, u32 offset, u32 value)
104{
105	writel_relaxed(value, base + offset);
106}
107
108/**
109 * st_dwc3_drd_init: program the port
110 * @dwc3_data: driver private structure
111 * Description: this function is to program the port as either host or device
112 * according to the static configuration passed from devicetree.
113 * OTG and dual role are not yet supported!
114 */
115static int st_dwc3_drd_init(struct st_dwc3 *dwc3_data)
116{
117	u32 val;
118	int err;
119
120	err = regmap_read(dwc3_data->regmap, dwc3_data->syscfg_reg_off, &val);
121	if (err)
122		return err;
123
124	val &= USB3_CONTROL_MASK;
125
126	switch (dwc3_data->dr_mode) {
127	case USB_DR_MODE_PERIPHERAL:
128
129		val &= ~(USB3_DELAY_VBUSVALID
130			| USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
131			| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
132			| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
133
134		/*
135		 * USB3_PORT2_FORCE_VBUSVALID When '1' and when
136		 * USB3_PORT2_DEVICE_NOT_HOST = 1, forces VBUSVLDEXT2 input
137		 * of the pico PHY to 1.
138		 */
139
140		val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID;
141		break;
142
143	case USB_DR_MODE_HOST:
144
145		val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID
146			| USB3_SEL_FORCE_OPMODE	| USB3_FORCE_OPMODE(0x3)
147			| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
148			| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
149
150		/*
151		 * USB3_DELAY_VBUSVALID is ANDed with USB_C_VBUSVALID. Thus,
152		 * when set to ���0���, it can delay the arrival of VBUSVALID
153		 * information to VBUSVLDEXT2 input of the pico PHY.
154		 * We don't want to do that so we set the bit to '1'.
155		 */
156
157		val |= USB3_DELAY_VBUSVALID;
158		break;
159
160	default:
161		dev_err(dwc3_data->dev, "Unsupported mode of operation %d\n",
162			dwc3_data->dr_mode);
163		return -EINVAL;
164	}
165
166	return regmap_write(dwc3_data->regmap, dwc3_data->syscfg_reg_off, val);
167}
168
169/**
170 * st_dwc3_init: init the controller via glue logic
171 * @dwc3_data: driver private structure
172 */
173static void st_dwc3_init(struct st_dwc3 *dwc3_data)
174{
175	u32 reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL);
176
177	reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;
178	reg &= ~SW_PIPEW_RESET_N;
179	st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg);
180
181	/* configure mux for vbus, powerpresent and bvalid signals */
182	reg = st_dwc3_readl(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1);
183
184	reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
185		SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
186		SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG);
187
188	st_dwc3_writel(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1, reg);
189
190	reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL);
191	reg |= SW_PIPEW_RESET_N;
192	st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg);
193}
194
195static int st_dwc3_probe(struct platform_device *pdev)
196{
197	struct st_dwc3 *dwc3_data;
198	struct resource *res;
199	struct device *dev = &pdev->dev;
200	struct device_node *node = dev->of_node, *child;
201	struct platform_device *child_pdev;
202	struct regmap *regmap;
203	int ret;
204
205	dwc3_data = devm_kzalloc(dev, sizeof(*dwc3_data), GFP_KERNEL);
206	if (!dwc3_data)
207		return -ENOMEM;
208
209	dwc3_data->glue_base =
210		devm_platform_ioremap_resource_byname(pdev, "reg-glue");
211	if (IS_ERR(dwc3_data->glue_base))
212		return PTR_ERR(dwc3_data->glue_base);
213
214	regmap = syscon_regmap_lookup_by_phandle(node, "st,syscfg");
215	if (IS_ERR(regmap))
216		return PTR_ERR(regmap);
217
218	dwc3_data->dev = dev;
219	dwc3_data->regmap = regmap;
220
221	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "syscfg-reg");
222	if (!res) {
223		ret = -ENXIO;
224		goto undo_platform_dev_alloc;
225	}
226
227	dwc3_data->syscfg_reg_off = res->start;
228
229	dev_vdbg(&pdev->dev, "glue-logic addr 0x%pK, syscfg-reg offset 0x%x\n",
230		 dwc3_data->glue_base, dwc3_data->syscfg_reg_off);
231
232	dwc3_data->rstc_pwrdn =
233		devm_reset_control_get_exclusive(dev, "powerdown");
234	if (IS_ERR(dwc3_data->rstc_pwrdn)) {
235		dev_err(&pdev->dev, "could not get power controller\n");
236		ret = PTR_ERR(dwc3_data->rstc_pwrdn);
237		goto undo_platform_dev_alloc;
238	}
239
240	/* Manage PowerDown */
241	reset_control_deassert(dwc3_data->rstc_pwrdn);
242
243	dwc3_data->rstc_rst =
244		devm_reset_control_get_shared(dev, "softreset");
245	if (IS_ERR(dwc3_data->rstc_rst)) {
246		dev_err(&pdev->dev, "could not get reset controller\n");
247		ret = PTR_ERR(dwc3_data->rstc_rst);
248		goto undo_powerdown;
249	}
250
251	/* Manage SoftReset */
252	reset_control_deassert(dwc3_data->rstc_rst);
253
254	child = of_get_compatible_child(node, "snps,dwc3");
255	if (!child) {
256		dev_err(&pdev->dev, "failed to find dwc3 core node\n");
257		ret = -ENODEV;
258		goto err_node_put;
259	}
260
261	/* Allocate and initialize the core */
262	ret = of_platform_populate(node, NULL, NULL, dev);
263	if (ret) {
264		dev_err(dev, "failed to add dwc3 core\n");
265		goto err_node_put;
266	}
267
268	child_pdev = of_find_device_by_node(child);
269	if (!child_pdev) {
270		dev_err(dev, "failed to find dwc3 core device\n");
271		ret = -ENODEV;
272		goto err_node_put;
273	}
274
275	dwc3_data->dr_mode = usb_get_dr_mode(&child_pdev->dev);
276	of_node_put(child);
277	platform_device_put(child_pdev);
278
279	/*
280	 * Configure the USB port as device or host according to the static
281	 * configuration passed from DT.
282	 * DRD is the only mode currently supported so this will be enhanced
283	 * as soon as OTG is available.
284	 */
285	ret = st_dwc3_drd_init(dwc3_data);
286	if (ret) {
287		dev_err(dev, "drd initialisation failed\n");
288		goto undo_softreset;
289	}
290
291	/* ST glue logic init */
292	st_dwc3_init(dwc3_data);
293
294	platform_set_drvdata(pdev, dwc3_data);
295	return 0;
296
297err_node_put:
298	of_node_put(child);
299undo_softreset:
300	reset_control_assert(dwc3_data->rstc_rst);
301undo_powerdown:
302	reset_control_assert(dwc3_data->rstc_pwrdn);
303undo_platform_dev_alloc:
304	platform_device_put(pdev);
305	return ret;
306}
307
308static void st_dwc3_remove(struct platform_device *pdev)
309{
310	struct st_dwc3 *dwc3_data = platform_get_drvdata(pdev);
311
312	of_platform_depopulate(&pdev->dev);
313
314	reset_control_assert(dwc3_data->rstc_pwrdn);
315	reset_control_assert(dwc3_data->rstc_rst);
316}
317
318#ifdef CONFIG_PM_SLEEP
319static int st_dwc3_suspend(struct device *dev)
320{
321	struct st_dwc3 *dwc3_data = dev_get_drvdata(dev);
322
323	reset_control_assert(dwc3_data->rstc_pwrdn);
324	reset_control_assert(dwc3_data->rstc_rst);
325
326	pinctrl_pm_select_sleep_state(dev);
327
328	return 0;
329}
330
331static int st_dwc3_resume(struct device *dev)
332{
333	struct st_dwc3 *dwc3_data = dev_get_drvdata(dev);
334	int ret;
335
336	pinctrl_pm_select_default_state(dev);
337
338	reset_control_deassert(dwc3_data->rstc_pwrdn);
339	reset_control_deassert(dwc3_data->rstc_rst);
340
341	ret = st_dwc3_drd_init(dwc3_data);
342	if (ret) {
343		dev_err(dev, "drd initialisation failed\n");
344		return ret;
345	}
346
347	/* ST glue logic init */
348	st_dwc3_init(dwc3_data);
349
350	return 0;
351}
352#endif /* CONFIG_PM_SLEEP */
353
354static SIMPLE_DEV_PM_OPS(st_dwc3_dev_pm_ops, st_dwc3_suspend, st_dwc3_resume);
355
356static const struct of_device_id st_dwc3_match[] = {
357	{ .compatible = "st,stih407-dwc3" },
358	{ /* sentinel */ },
359};
360
361MODULE_DEVICE_TABLE(of, st_dwc3_match);
362
363static struct platform_driver st_dwc3_driver = {
364	.probe = st_dwc3_probe,
365	.remove_new = st_dwc3_remove,
366	.driver = {
367		.name = "usb-st-dwc3",
368		.of_match_table = st_dwc3_match,
369		.pm = &st_dwc3_dev_pm_ops,
370	},
371};
372
373module_platform_driver(st_dwc3_driver);
374
375MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
376MODULE_DESCRIPTION("DesignWare USB3 STi Glue Layer");
377MODULE_LICENSE("GPL v2");
378