1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 */ 5 6#include <linux/kernel.h> 7#include <linux/module.h> 8#include <linux/of.h> 9#include <linux/usb/of.h> 10#include <linux/pci_ids.h> 11#include <linux/pci.h> 12 13#include "core.h" 14 15#define PCI_PRODUCT_ID_HAPS_HSOTG 0xabc0 16#define PCI_DEVICE_ID_LOONGSON_DWC2 0x7a04 17 18static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 19{ 20 struct dwc2_core_params *p = &hsotg->params; 21 22 p->host_rx_fifo_size = 774; 23 p->max_transfer_size = 65535; 24 p->max_packet_count = 511; 25 p->ahbcfg = 0x10; 26} 27 28static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 29{ 30 struct dwc2_core_params *p = &hsotg->params; 31 32 p->otg_caps.hnp_support = false; 33 p->otg_caps.srp_support = false; 34 p->speed = DWC2_SPEED_PARAM_HIGH; 35 p->host_rx_fifo_size = 512; 36 p->host_nperio_tx_fifo_size = 512; 37 p->host_perio_tx_fifo_size = 512; 38 p->max_transfer_size = 65535; 39 p->max_packet_count = 511; 40 p->host_channels = 16; 41 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 42 p->phy_utmi_width = 8; 43 p->i2c_enable = false; 44 p->reload_ctl = false; 45 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 46 GAHBCFG_HBSTLEN_SHIFT; 47 p->change_speed_quirk = true; 48 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 49} 50 51static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg) 52{ 53 struct dwc2_core_params *p = &hsotg->params; 54 55 p->otg_caps.hnp_support = false; 56 p->speed = DWC2_SPEED_PARAM_HIGH; 57 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 58 p->phy_utmi_width = 16; 59 p->activate_ingenic_overcurrent_detection = 60 !device_property_read_bool(hsotg->dev, "disable-over-current"); 61} 62 63static void dwc2_set_loongson_params(struct dwc2_hsotg *hsotg) 64{ 65 struct dwc2_core_params *p = &hsotg->params; 66 67 p->phy_utmi_width = 8; 68 p->power_down = DWC2_POWER_DOWN_PARAM_PARTIAL; 69} 70 71static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg) 72{ 73 struct dwc2_core_params *p = &hsotg->params; 74 75 p->otg_caps.hnp_support = false; 76 p->speed = DWC2_SPEED_PARAM_HIGH; 77 p->host_channels = 16; 78 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 79 p->phy_utmi_width = 16; 80 p->activate_ingenic_overcurrent_detection = 81 !device_property_read_bool(hsotg->dev, "disable-over-current"); 82} 83 84static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg) 85{ 86 struct dwc2_core_params *p = &hsotg->params; 87 88 p->otg_caps.hnp_support = false; 89 p->speed = DWC2_SPEED_PARAM_HIGH; 90 p->host_rx_fifo_size = 1024; 91 p->host_nperio_tx_fifo_size = 1024; 92 p->host_perio_tx_fifo_size = 1024; 93 p->host_channels = 16; 94 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 95 p->phy_utmi_width = 16; 96 p->activate_ingenic_overcurrent_detection = 97 !device_property_read_bool(hsotg->dev, "disable-over-current"); 98} 99 100static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) 101{ 102 struct dwc2_core_params *p = &hsotg->params; 103 104 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 105 p->no_clock_gating = true; 106 p->phy_utmi_width = 8; 107} 108 109static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg) 110{ 111 struct dwc2_core_params *p = &hsotg->params; 112 113 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 114 p->no_clock_gating = true; 115} 116 117static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 118{ 119 struct dwc2_core_params *p = &hsotg->params; 120 121 p->otg_caps.hnp_support = false; 122 p->otg_caps.srp_support = false; 123 p->host_rx_fifo_size = 525; 124 p->host_nperio_tx_fifo_size = 128; 125 p->host_perio_tx_fifo_size = 256; 126 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 127 GAHBCFG_HBSTLEN_SHIFT; 128 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 129 p->lpm = false; 130 p->lpm_clock_gating = false; 131 p->besl = false; 132 p->hird_threshold_en = false; 133 p->no_clock_gating = true; 134} 135 136static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 137{ 138 struct dwc2_core_params *p = &hsotg->params; 139 140 p->otg_caps.hnp_support = false; 141 p->otg_caps.srp_support = false; 142 p->host_rx_fifo_size = 288; 143 p->host_nperio_tx_fifo_size = 128; 144 p->host_perio_tx_fifo_size = 96; 145 p->max_transfer_size = 65535; 146 p->max_packet_count = 511; 147 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 148 GAHBCFG_HBSTLEN_SHIFT; 149} 150 151static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 152{ 153 struct dwc2_core_params *p = &hsotg->params; 154 155 p->otg_caps.hnp_support = false; 156 p->otg_caps.srp_support = false; 157 p->speed = DWC2_SPEED_PARAM_HIGH; 158 p->host_rx_fifo_size = 512; 159 p->host_nperio_tx_fifo_size = 500; 160 p->host_perio_tx_fifo_size = 500; 161 p->host_channels = 16; 162 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 163 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 164 GAHBCFG_HBSTLEN_SHIFT; 165 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 166} 167 168static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) 169{ 170 struct dwc2_core_params *p = &hsotg->params; 171 172 p->lpm = false; 173 p->lpm_clock_gating = false; 174 p->besl = false; 175 p->hird_threshold_en = false; 176} 177 178static void dwc2_set_amlogic_a1_params(struct dwc2_hsotg *hsotg) 179{ 180 struct dwc2_core_params *p = &hsotg->params; 181 182 p->otg_caps.hnp_support = false; 183 p->otg_caps.srp_support = false; 184 p->speed = DWC2_SPEED_PARAM_HIGH; 185 p->host_rx_fifo_size = 192; 186 p->host_nperio_tx_fifo_size = 128; 187 p->host_perio_tx_fifo_size = 128; 188 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 189 p->phy_utmi_width = 8; 190 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT; 191 p->lpm = false; 192 p->lpm_clock_gating = false; 193 p->besl = false; 194 p->hird_threshold_en = false; 195} 196 197static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 198{ 199 struct dwc2_core_params *p = &hsotg->params; 200 201 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 202} 203 204static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 205{ 206 struct dwc2_core_params *p = &hsotg->params; 207 208 p->otg_caps.hnp_support = false; 209 p->otg_caps.srp_support = false; 210 p->speed = DWC2_SPEED_PARAM_FULL; 211 p->host_rx_fifo_size = 128; 212 p->host_nperio_tx_fifo_size = 96; 213 p->host_perio_tx_fifo_size = 96; 214 p->max_packet_count = 256; 215 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 216 p->i2c_enable = false; 217 p->activate_stm_fs_transceiver = true; 218} 219 220static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 221{ 222 struct dwc2_core_params *p = &hsotg->params; 223 224 p->host_rx_fifo_size = 622; 225 p->host_nperio_tx_fifo_size = 128; 226 p->host_perio_tx_fifo_size = 256; 227} 228 229static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg) 230{ 231 struct dwc2_core_params *p = &hsotg->params; 232 233 p->otg_caps.hnp_support = false; 234 p->otg_caps.srp_support = false; 235 p->otg_caps.otg_rev = 0x200; 236 p->speed = DWC2_SPEED_PARAM_FULL; 237 p->host_rx_fifo_size = 128; 238 p->host_nperio_tx_fifo_size = 96; 239 p->host_perio_tx_fifo_size = 96; 240 p->max_packet_count = 256; 241 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 242 p->i2c_enable = false; 243 p->activate_stm_fs_transceiver = true; 244 p->activate_stm_id_vb_detection = true; 245 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 246 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 247 p->host_support_fs_ls_low_power = true; 248 p->host_ls_low_power_phy_clk = true; 249} 250 251static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg) 252{ 253 struct dwc2_core_params *p = &hsotg->params; 254 255 p->otg_caps.hnp_support = false; 256 p->otg_caps.srp_support = false; 257 p->otg_caps.otg_rev = 0x200; 258 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); 259 p->host_rx_fifo_size = 440; 260 p->host_nperio_tx_fifo_size = 256; 261 p->host_perio_tx_fifo_size = 256; 262 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 263 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 264 p->lpm = false; 265 p->lpm_clock_gating = false; 266 p->besl = false; 267 p->hird_threshold_en = false; 268} 269 270const struct of_device_id dwc2_of_match_table[] = { 271 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 272 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 273 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params }, 274 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params }, 275 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params }, 276 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params }, 277 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params }, 278 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params }, 279 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params }, 280 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 281 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 282 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 283 { .compatible = "snps,dwc2" }, 284 { .compatible = "samsung,s3c6400-hsotg", 285 .data = dwc2_set_s3c6400_params }, 286 { .compatible = "amlogic,meson8-usb", 287 .data = dwc2_set_amlogic_params }, 288 { .compatible = "amlogic,meson8b-usb", 289 .data = dwc2_set_amlogic_params }, 290 { .compatible = "amlogic,meson-gxbb-usb", 291 .data = dwc2_set_amlogic_params }, 292 { .compatible = "amlogic,meson-g12a-usb", 293 .data = dwc2_set_amlogic_g12a_params }, 294 { .compatible = "amlogic,meson-a1-usb", 295 .data = dwc2_set_amlogic_a1_params }, 296 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 297 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, 298 { .compatible = "st,stm32f4x9-fsotg", 299 .data = dwc2_set_stm32f4x9_fsotg_params }, 300 { .compatible = "st,stm32f4x9-hsotg" }, 301 { .compatible = "st,stm32f7-hsotg", 302 .data = dwc2_set_stm32f7_hsotg_params }, 303 { .compatible = "st,stm32mp15-fsotg", 304 .data = dwc2_set_stm32mp15_fsotg_params }, 305 { .compatible = "st,stm32mp15-hsotg", 306 .data = dwc2_set_stm32mp15_hsotg_params }, 307 { .compatible = "intel,socfpga-agilex-hsotg", 308 .data = dwc2_set_socfpga_agilex_params }, 309 {}, 310}; 311MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 312 313const struct acpi_device_id dwc2_acpi_match[] = { 314 { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params }, 315 { }, 316}; 317MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match); 318 319const struct pci_device_id dwc2_pci_ids[] = { 320 { 321 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, PCI_PRODUCT_ID_HAPS_HSOTG), 322 }, 323 { 324 PCI_DEVICE(PCI_VENDOR_ID_STMICRO, 325 PCI_DEVICE_ID_STMICRO_USB_OTG), 326 }, 327 { 328 PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DWC2), 329 .driver_data = (unsigned long)dwc2_set_loongson_params, 330 }, 331 { /* end: all zeroes */ } 332}; 333MODULE_DEVICE_TABLE(pci, dwc2_pci_ids); 334EXPORT_SYMBOL_GPL(dwc2_pci_ids); 335 336static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 337{ 338 switch (hsotg->hw_params.op_mode) { 339 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 340 hsotg->params.otg_caps.hnp_support = true; 341 hsotg->params.otg_caps.srp_support = true; 342 break; 343 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 344 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 345 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 346 hsotg->params.otg_caps.hnp_support = false; 347 hsotg->params.otg_caps.srp_support = true; 348 break; 349 default: 350 hsotg->params.otg_caps.hnp_support = false; 351 hsotg->params.otg_caps.srp_support = false; 352 break; 353 } 354} 355 356static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 357{ 358 int val; 359 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 360 361 val = DWC2_PHY_TYPE_PARAM_FS; 362 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 363 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 364 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 365 val = DWC2_PHY_TYPE_PARAM_UTMI; 366 else 367 val = DWC2_PHY_TYPE_PARAM_ULPI; 368 } 369 370 if (dwc2_is_fs_iot(hsotg)) 371 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 372 373 hsotg->params.phy_type = val; 374} 375 376static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 377{ 378 int val; 379 380 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 381 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 382 383 if (dwc2_is_fs_iot(hsotg)) 384 val = DWC2_SPEED_PARAM_FULL; 385 386 if (dwc2_is_hs_iot(hsotg)) 387 val = DWC2_SPEED_PARAM_HIGH; 388 389 hsotg->params.speed = val; 390} 391 392static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 393{ 394 int val; 395 396 val = (hsotg->hw_params.utmi_phy_data_width == 397 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 398 399 if (hsotg->phy) { 400 /* 401 * If using the generic PHY framework, check if the PHY bus 402 * width is 8-bit and set the phyif appropriately. 403 */ 404 if (phy_get_bus_width(hsotg->phy) == 8) 405 val = 8; 406 } 407 408 hsotg->params.phy_utmi_width = val; 409} 410 411static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 412{ 413 struct dwc2_core_params *p = &hsotg->params; 414 int depth_average; 415 int fifo_count; 416 int i; 417 418 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 419 420 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 421 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 422 for (i = 1; i <= fifo_count; i++) 423 p->g_tx_fifo_size[i] = depth_average; 424} 425 426static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 427{ 428 int val; 429 430 if (hsotg->hw_params.hibernation) 431 val = DWC2_POWER_DOWN_PARAM_HIBERNATION; 432 else if (hsotg->hw_params.power_optimized) 433 val = DWC2_POWER_DOWN_PARAM_PARTIAL; 434 else 435 val = DWC2_POWER_DOWN_PARAM_NONE; 436 437 hsotg->params.power_down = val; 438} 439 440static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) 441{ 442 struct dwc2_core_params *p = &hsotg->params; 443 444 p->lpm = hsotg->hw_params.lpm_mode; 445 if (p->lpm) { 446 p->lpm_clock_gating = true; 447 p->besl = true; 448 p->hird_threshold_en = true; 449 p->hird_threshold = 4; 450 } else { 451 p->lpm_clock_gating = false; 452 p->besl = false; 453 p->hird_threshold_en = false; 454 } 455} 456 457/** 458 * dwc2_set_default_params() - Set all core parameters to their 459 * auto-detected default values. 460 * 461 * @hsotg: Programming view of the DWC_otg controller 462 * 463 */ 464static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 465{ 466 struct dwc2_hw_params *hw = &hsotg->hw_params; 467 struct dwc2_core_params *p = &hsotg->params; 468 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 469 470 dwc2_set_param_otg_cap(hsotg); 471 dwc2_set_param_phy_type(hsotg); 472 dwc2_set_param_speed(hsotg); 473 dwc2_set_param_phy_utmi_width(hsotg); 474 dwc2_set_param_power_down(hsotg); 475 dwc2_set_param_lpm(hsotg); 476 p->phy_ulpi_ddr = false; 477 p->phy_ulpi_ext_vbus = false; 478 479 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 480 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 481 p->i2c_enable = hw->i2c_enable; 482 p->acg_enable = hw->acg_enable; 483 p->ulpi_fs_ls = false; 484 p->ts_dline = false; 485 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 486 p->uframe_sched = true; 487 p->external_id_pin_ctl = false; 488 p->ipg_isoc_en = false; 489 p->service_interval = false; 490 p->max_packet_count = hw->max_packet_count; 491 p->max_transfer_size = hw->max_transfer_size; 492 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 493 p->ref_clk_per = 33333; 494 p->sof_cnt_wkup_alert = 100; 495 496 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 497 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 498 p->host_dma = dma_capable; 499 p->dma_desc_enable = false; 500 p->dma_desc_fs_enable = false; 501 p->host_support_fs_ls_low_power = false; 502 p->host_ls_low_power_phy_clk = false; 503 p->host_channels = hw->host_channels; 504 p->host_rx_fifo_size = hw->rx_fifo_size; 505 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 506 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 507 } 508 509 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 510 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 511 p->g_dma = dma_capable; 512 p->g_dma_desc = hw->dma_desc_enable; 513 514 /* 515 * The values for g_rx_fifo_size (2048) and 516 * g_np_tx_fifo_size (1024) come from the legacy s3c 517 * gadget driver. These defaults have been hard-coded 518 * for some time so many platforms depend on these 519 * values. Leave them as defaults for now and only 520 * auto-detect if the hardware does not support the 521 * default. 522 */ 523 p->g_rx_fifo_size = 2048; 524 p->g_np_tx_fifo_size = 1024; 525 dwc2_set_param_tx_fifo_sizes(hsotg); 526 } 527} 528 529/** 530 * dwc2_get_device_properties() - Read in device properties. 531 * 532 * @hsotg: Programming view of the DWC_otg controller 533 * 534 * Read in the device properties and adjust core parameters if needed. 535 */ 536static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 537{ 538 struct dwc2_core_params *p = &hsotg->params; 539 int num; 540 541 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 542 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 543 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 544 &p->g_rx_fifo_size); 545 546 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 547 &p->g_np_tx_fifo_size); 548 549 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); 550 if (num > 0) { 551 num = min(num, 15); 552 memset(p->g_tx_fifo_size, 0, 553 sizeof(p->g_tx_fifo_size)); 554 device_property_read_u32_array(hsotg->dev, 555 "g-tx-fifo-size", 556 &p->g_tx_fifo_size[1], 557 num); 558 } 559 560 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); 561 } 562 563 p->oc_disable = of_property_read_bool(hsotg->dev->of_node, "disable-over-current"); 564} 565 566static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 567{ 568 int valid = 1; 569 570 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { 571 /* check HNP && SRP capable */ 572 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 573 valid = 0; 574 } else if (!hsotg->params.otg_caps.hnp_support) { 575 /* check SRP only capable */ 576 if (hsotg->params.otg_caps.srp_support) { 577 switch (hsotg->hw_params.op_mode) { 578 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 579 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 580 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 581 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 582 break; 583 default: 584 valid = 0; 585 break; 586 } 587 } 588 /* else: NO HNP && NO SRP capable: always valid */ 589 } else { 590 valid = 0; 591 } 592 593 if (!valid) 594 dwc2_set_param_otg_cap(hsotg); 595} 596 597static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 598{ 599 int valid = 0; 600 u32 hs_phy_type; 601 u32 fs_phy_type; 602 603 hs_phy_type = hsotg->hw_params.hs_phy_type; 604 fs_phy_type = hsotg->hw_params.fs_phy_type; 605 606 switch (hsotg->params.phy_type) { 607 case DWC2_PHY_TYPE_PARAM_FS: 608 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 609 valid = 1; 610 break; 611 case DWC2_PHY_TYPE_PARAM_UTMI: 612 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 613 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 614 valid = 1; 615 break; 616 case DWC2_PHY_TYPE_PARAM_ULPI: 617 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 618 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 619 valid = 1; 620 break; 621 default: 622 break; 623 } 624 625 if (!valid) 626 dwc2_set_param_phy_type(hsotg); 627} 628 629static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 630{ 631 int valid = 1; 632 int phy_type = hsotg->params.phy_type; 633 int speed = hsotg->params.speed; 634 635 switch (speed) { 636 case DWC2_SPEED_PARAM_HIGH: 637 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 638 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 639 valid = 0; 640 break; 641 case DWC2_SPEED_PARAM_FULL: 642 case DWC2_SPEED_PARAM_LOW: 643 break; 644 default: 645 valid = 0; 646 break; 647 } 648 649 if (!valid) 650 dwc2_set_param_speed(hsotg); 651} 652 653static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 654{ 655 int valid = 0; 656 int param = hsotg->params.phy_utmi_width; 657 int width = hsotg->hw_params.utmi_phy_data_width; 658 659 switch (width) { 660 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 661 valid = (param == 8); 662 break; 663 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 664 valid = (param == 16); 665 break; 666 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 667 valid = (param == 8 || param == 16); 668 break; 669 } 670 671 if (!valid) 672 dwc2_set_param_phy_utmi_width(hsotg); 673} 674 675static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 676{ 677 int param = hsotg->params.power_down; 678 679 switch (param) { 680 case DWC2_POWER_DOWN_PARAM_NONE: 681 break; 682 case DWC2_POWER_DOWN_PARAM_PARTIAL: 683 if (hsotg->hw_params.power_optimized) 684 break; 685 dev_dbg(hsotg->dev, 686 "Partial power down isn't supported by HW\n"); 687 param = DWC2_POWER_DOWN_PARAM_NONE; 688 break; 689 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 690 if (hsotg->hw_params.hibernation) 691 break; 692 dev_dbg(hsotg->dev, 693 "Hibernation isn't supported by HW\n"); 694 param = DWC2_POWER_DOWN_PARAM_NONE; 695 break; 696 default: 697 dev_err(hsotg->dev, 698 "%s: Invalid parameter power_down=%d\n", 699 __func__, param); 700 param = DWC2_POWER_DOWN_PARAM_NONE; 701 break; 702 } 703 704 hsotg->params.power_down = param; 705} 706 707static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 708{ 709 int fifo_count; 710 int fifo; 711 int min; 712 u32 total = 0; 713 u32 dptxfszn; 714 715 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 716 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 717 718 for (fifo = 1; fifo <= fifo_count; fifo++) 719 total += hsotg->params.g_tx_fifo_size[fifo]; 720 721 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 722 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 723 __func__); 724 dwc2_set_param_tx_fifo_sizes(hsotg); 725 } 726 727 for (fifo = 1; fifo <= fifo_count; fifo++) { 728 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 729 730 if (hsotg->params.g_tx_fifo_size[fifo] < min || 731 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 732 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 733 __func__, fifo, 734 hsotg->params.g_tx_fifo_size[fifo]); 735 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 736 } 737 } 738} 739 740#define CHECK_RANGE(_param, _min, _max, _def) do { \ 741 if ((int)(hsotg->params._param) < (_min) || \ 742 (hsotg->params._param) > (_max)) { \ 743 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 744 __func__, #_param, hsotg->params._param); \ 745 hsotg->params._param = (_def); \ 746 } \ 747 } while (0) 748 749#define CHECK_BOOL(_param, _check) do { \ 750 if (hsotg->params._param && !(_check)) { \ 751 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 752 __func__, #_param, hsotg->params._param); \ 753 hsotg->params._param = false; \ 754 } \ 755 } while (0) 756 757static void dwc2_check_params(struct dwc2_hsotg *hsotg) 758{ 759 struct dwc2_hw_params *hw = &hsotg->hw_params; 760 struct dwc2_core_params *p = &hsotg->params; 761 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 762 763 dwc2_check_param_otg_cap(hsotg); 764 dwc2_check_param_phy_type(hsotg); 765 dwc2_check_param_speed(hsotg); 766 dwc2_check_param_phy_utmi_width(hsotg); 767 dwc2_check_param_power_down(hsotg); 768 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 769 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 770 CHECK_BOOL(i2c_enable, hw->i2c_enable); 771 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 772 CHECK_BOOL(acg_enable, hw->acg_enable); 773 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 774 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 775 CHECK_BOOL(lpm, hw->lpm_mode); 776 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 777 CHECK_BOOL(besl, hsotg->params.lpm); 778 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 779 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 780 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 781 CHECK_BOOL(service_interval, hw->service_interval_mode); 782 CHECK_RANGE(max_packet_count, 783 15, hw->max_packet_count, 784 hw->max_packet_count); 785 CHECK_RANGE(max_transfer_size, 786 2047, hw->max_transfer_size, 787 hw->max_transfer_size); 788 789 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 790 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 791 CHECK_BOOL(host_dma, dma_capable); 792 CHECK_BOOL(dma_desc_enable, p->host_dma); 793 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 794 CHECK_BOOL(host_ls_low_power_phy_clk, 795 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 796 CHECK_RANGE(host_channels, 797 1, hw->host_channels, 798 hw->host_channels); 799 CHECK_RANGE(host_rx_fifo_size, 800 16, hw->rx_fifo_size, 801 hw->rx_fifo_size); 802 CHECK_RANGE(host_nperio_tx_fifo_size, 803 16, hw->host_nperio_tx_fifo_size, 804 hw->host_nperio_tx_fifo_size); 805 CHECK_RANGE(host_perio_tx_fifo_size, 806 16, hw->host_perio_tx_fifo_size, 807 hw->host_perio_tx_fifo_size); 808 } 809 810 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 811 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 812 CHECK_BOOL(g_dma, dma_capable); 813 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 814 CHECK_RANGE(g_rx_fifo_size, 815 16, hw->rx_fifo_size, 816 hw->rx_fifo_size); 817 CHECK_RANGE(g_np_tx_fifo_size, 818 16, hw->dev_nperio_tx_fifo_size, 819 hw->dev_nperio_tx_fifo_size); 820 dwc2_check_param_tx_fifo_sizes(hsotg); 821 } 822} 823 824/* 825 * Gets host hardware parameters. Forces host mode if not currently in 826 * host mode. Should be called immediately after a core soft reset in 827 * order to get the reset values. 828 */ 829static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 830{ 831 struct dwc2_hw_params *hw = &hsotg->hw_params; 832 u32 gnptxfsiz; 833 u32 hptxfsiz; 834 835 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 836 return; 837 838 dwc2_force_mode(hsotg, true); 839 840 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 841 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 842 843 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 844 FIFOSIZE_DEPTH_SHIFT; 845 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 846 FIFOSIZE_DEPTH_SHIFT; 847} 848 849/* 850 * Gets device hardware parameters. Forces device mode if not 851 * currently in device mode. Should be called immediately after a core 852 * soft reset in order to get the reset values. 853 */ 854static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 855{ 856 struct dwc2_hw_params *hw = &hsotg->hw_params; 857 u32 gnptxfsiz; 858 int fifo, fifo_count; 859 860 if (hsotg->dr_mode == USB_DR_MODE_HOST) 861 return; 862 863 dwc2_force_mode(hsotg, false); 864 865 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 866 867 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 868 869 for (fifo = 1; fifo <= fifo_count; fifo++) { 870 hw->g_tx_fifo_size[fifo] = 871 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 872 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 873 } 874 875 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 876 FIFOSIZE_DEPTH_SHIFT; 877} 878 879/** 880 * dwc2_get_hwparams() - During device initialization, read various hardware 881 * configuration registers and interpret the contents. 882 * 883 * @hsotg: Programming view of the DWC_otg controller 884 * 885 */ 886int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 887{ 888 struct dwc2_hw_params *hw = &hsotg->hw_params; 889 unsigned int width; 890 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 891 u32 grxfsiz; 892 893 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 894 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 895 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 896 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 897 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 898 899 /* hwcfg1 */ 900 hw->dev_ep_dirs = hwcfg1; 901 902 /* hwcfg2 */ 903 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 904 GHWCFG2_OP_MODE_SHIFT; 905 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 906 GHWCFG2_ARCHITECTURE_SHIFT; 907 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 908 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 909 GHWCFG2_NUM_HOST_CHAN_SHIFT); 910 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 911 GHWCFG2_HS_PHY_TYPE_SHIFT; 912 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 913 GHWCFG2_FS_PHY_TYPE_SHIFT; 914 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 915 GHWCFG2_NUM_DEV_EP_SHIFT; 916 hw->nperio_tx_q_depth = 917 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 918 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 919 hw->host_perio_tx_q_depth = 920 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 921 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 922 hw->dev_token_q_depth = 923 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 924 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 925 926 /* hwcfg3 */ 927 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 928 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 929 hw->max_transfer_size = (1 << (width + 11)) - 1; 930 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 931 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 932 hw->max_packet_count = (1 << (width + 4)) - 1; 933 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 934 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 935 GHWCFG3_DFIFO_DEPTH_SHIFT; 936 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 937 938 /* hwcfg4 */ 939 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 940 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 941 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 942 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 943 GHWCFG4_NUM_IN_EPS_SHIFT; 944 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 945 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 946 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 947 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 948 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 949 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 950 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 951 hw->service_interval_mode = !!(hwcfg4 & 952 GHWCFG4_SERVICE_INTERVAL_SUPPORTED); 953 954 /* fifo sizes */ 955 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 956 GRXFSIZ_DEPTH_SHIFT; 957 /* 958 * Host specific hardware parameters. Reading these parameters 959 * requires the controller to be in host mode. The mode will 960 * be forced, if necessary, to read these values. 961 */ 962 dwc2_get_host_hwparams(hsotg); 963 dwc2_get_dev_hwparams(hsotg); 964 965 return 0; 966} 967 968typedef void (*set_params_cb)(struct dwc2_hsotg *data); 969 970int dwc2_init_params(struct dwc2_hsotg *hsotg) 971{ 972 set_params_cb set_params; 973 974 dwc2_set_default_params(hsotg); 975 dwc2_get_device_properties(hsotg); 976 977 set_params = device_get_match_data(hsotg->dev); 978 if (set_params) { 979 set_params(hsotg); 980 } else { 981 const struct pci_device_id *pmatch = 982 pci_match_id(dwc2_pci_ids, to_pci_dev(hsotg->dev->parent)); 983 984 if (pmatch && pmatch->driver_data) { 985 set_params = (set_params_cb)pmatch->driver_data; 986 set_params(hsotg); 987 } 988 } 989 990 dwc2_check_params(hsotg); 991 992 return 0; 993} 994