1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18#undef DEBUG 19 20#include <linux/clk.h> 21#include <linux/console.h> 22#include <linux/ctype.h> 23#include <linux/cpufreq.h> 24#include <linux/delay.h> 25#include <linux/dmaengine.h> 26#include <linux/dma-mapping.h> 27#include <linux/err.h> 28#include <linux/errno.h> 29#include <linux/init.h> 30#include <linux/interrupt.h> 31#include <linux/ioport.h> 32#include <linux/ktime.h> 33#include <linux/major.h> 34#include <linux/minmax.h> 35#include <linux/module.h> 36#include <linux/mm.h> 37#include <linux/of.h> 38#include <linux/platform_device.h> 39#include <linux/pm_runtime.h> 40#include <linux/reset.h> 41#include <linux/scatterlist.h> 42#include <linux/serial.h> 43#include <linux/serial_sci.h> 44#include <linux/sh_dma.h> 45#include <linux/slab.h> 46#include <linux/string.h> 47#include <linux/sysrq.h> 48#include <linux/timer.h> 49#include <linux/tty.h> 50#include <linux/tty_flip.h> 51 52#ifdef CONFIG_SUPERH 53#include <asm/sh_bios.h> 54#include <asm/platform_early.h> 55#endif 56 57#include "serial_mctrl_gpio.h" 58#include "sh-sci.h" 59 60/* Offsets into the sci_port->irqs array */ 61enum { 62 SCIx_ERI_IRQ, 63 SCIx_RXI_IRQ, 64 SCIx_TXI_IRQ, 65 SCIx_BRI_IRQ, 66 SCIx_DRI_IRQ, 67 SCIx_TEI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71}; 72 73#define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79enum SCI_CLKS { 80 SCI_FCK, /* Functional Clock */ 81 SCI_SCK, /* Optional External Clock */ 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 84 SCI_NUM_CLKS 85}; 86 87/* Bit x set means sampling rate x + 1 is supported */ 88#define SCI_SR(x) BIT((x) - 1) 89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 90 91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 93 SCI_SR(19) | SCI_SR(27) 94 95#define min_sr(_port) ffs((_port)->sampling_rate_mask) 96#define max_sr(_port) fls((_port)->sampling_rate_mask) 97 98/* Iterate over all supported sampling rates, from high to low */ 99#define for_each_sr(_sr, _port) \ 100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 101 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 102 103struct plat_sci_reg { 104 u8 offset, size; 105}; 106 107struct sci_port_params { 108 const struct plat_sci_reg regs[SCIx_NR_REGS]; 109 unsigned int fifosize; 110 unsigned int overrun_reg; 111 unsigned int overrun_mask; 112 unsigned int sampling_rate_mask; 113 unsigned int error_mask; 114 unsigned int error_clear; 115}; 116 117struct sci_port { 118 struct uart_port port; 119 120 /* Platform configuration */ 121 const struct sci_port_params *params; 122 const struct plat_sci_port *cfg; 123 unsigned int sampling_rate_mask; 124 resource_size_t reg_size; 125 struct mctrl_gpios *gpios; 126 127 /* Clocks */ 128 struct clk *clks[SCI_NUM_CLKS]; 129 unsigned long clk_rates[SCI_NUM_CLKS]; 130 131 int irqs[SCIx_NR_IRQS]; 132 char *irqstr[SCIx_NR_IRQS]; 133 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 137#ifdef CONFIG_SERIAL_SH_SCI_DMA 138 struct dma_chan *chan_tx_saved; 139 struct dma_chan *chan_rx_saved; 140 dma_cookie_t cookie_tx; 141 dma_cookie_t cookie_rx[2]; 142 dma_cookie_t active_rx; 143 dma_addr_t tx_dma_addr; 144 unsigned int tx_dma_len; 145 struct scatterlist sg_rx[2]; 146 void *rx_buf[2]; 147 size_t buf_len_rx; 148 struct work_struct work_tx; 149 struct hrtimer rx_timer; 150 unsigned int rx_timeout; /* microseconds */ 151#endif 152 unsigned int rx_frame; 153 int rx_trigger; 154 struct timer_list rx_fifo_timer; 155 int rx_fifo_timeout; 156 u16 hscif_tot; 157 158 bool has_rtscts; 159 bool autorts; 160}; 161 162#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 163 164static struct sci_port sci_ports[SCI_NPORTS]; 165static unsigned long sci_ports_in_use; 166static struct uart_driver sci_uart_driver; 167 168static inline struct sci_port * 169to_sci_port(struct uart_port *uart) 170{ 171 return container_of(uart, struct sci_port, port); 172} 173 174static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 175 /* 176 * Common SCI definitions, dependent on the port's regshift 177 * value. 178 */ 179 [SCIx_SCI_REGTYPE] = { 180 .regs = { 181 [SCSMR] = { 0x00, 8 }, 182 [SCBRR] = { 0x01, 8 }, 183 [SCSCR] = { 0x02, 8 }, 184 [SCxTDR] = { 0x03, 8 }, 185 [SCxSR] = { 0x04, 8 }, 186 [SCxRDR] = { 0x05, 8 }, 187 }, 188 .fifosize = 1, 189 .overrun_reg = SCxSR, 190 .overrun_mask = SCI_ORER, 191 .sampling_rate_mask = SCI_SR(32), 192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 194 }, 195 196 /* 197 * Common definitions for legacy IrDA ports. 198 */ 199 [SCIx_IRDA_REGTYPE] = { 200 .regs = { 201 [SCSMR] = { 0x00, 8 }, 202 [SCBRR] = { 0x02, 8 }, 203 [SCSCR] = { 0x04, 8 }, 204 [SCxTDR] = { 0x06, 8 }, 205 [SCxSR] = { 0x08, 16 }, 206 [SCxRDR] = { 0x0a, 8 }, 207 [SCFCR] = { 0x0c, 8 }, 208 [SCFDR] = { 0x0e, 16 }, 209 }, 210 .fifosize = 1, 211 .overrun_reg = SCxSR, 212 .overrun_mask = SCI_ORER, 213 .sampling_rate_mask = SCI_SR(32), 214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 216 }, 217 218 /* 219 * Common SCIFA definitions. 220 */ 221 [SCIx_SCIFA_REGTYPE] = { 222 .regs = { 223 [SCSMR] = { 0x00, 16 }, 224 [SCBRR] = { 0x04, 8 }, 225 [SCSCR] = { 0x08, 16 }, 226 [SCxTDR] = { 0x20, 8 }, 227 [SCxSR] = { 0x14, 16 }, 228 [SCxRDR] = { 0x24, 8 }, 229 [SCFCR] = { 0x18, 16 }, 230 [SCFDR] = { 0x1c, 16 }, 231 [SCPCR] = { 0x30, 16 }, 232 [SCPDR] = { 0x34, 16 }, 233 }, 234 .fifosize = 64, 235 .overrun_reg = SCxSR, 236 .overrun_mask = SCIFA_ORER, 237 .sampling_rate_mask = SCI_SR_SCIFAB, 238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 240 }, 241 242 /* 243 * Common SCIFB definitions. 244 */ 245 [SCIx_SCIFB_REGTYPE] = { 246 .regs = { 247 [SCSMR] = { 0x00, 16 }, 248 [SCBRR] = { 0x04, 8 }, 249 [SCSCR] = { 0x08, 16 }, 250 [SCxTDR] = { 0x40, 8 }, 251 [SCxSR] = { 0x14, 16 }, 252 [SCxRDR] = { 0x60, 8 }, 253 [SCFCR] = { 0x18, 16 }, 254 [SCTFDR] = { 0x38, 16 }, 255 [SCRFDR] = { 0x3c, 16 }, 256 [SCPCR] = { 0x30, 16 }, 257 [SCPDR] = { 0x34, 16 }, 258 }, 259 .fifosize = 256, 260 .overrun_reg = SCxSR, 261 .overrun_mask = SCIFA_ORER, 262 .sampling_rate_mask = SCI_SR_SCIFAB, 263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 265 }, 266 267 /* 268 * Common SH-2(A) SCIF definitions for ports with FIFO data 269 * count registers. 270 */ 271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 272 .regs = { 273 [SCSMR] = { 0x00, 16 }, 274 [SCBRR] = { 0x04, 8 }, 275 [SCSCR] = { 0x08, 16 }, 276 [SCxTDR] = { 0x0c, 8 }, 277 [SCxSR] = { 0x10, 16 }, 278 [SCxRDR] = { 0x14, 8 }, 279 [SCFCR] = { 0x18, 16 }, 280 [SCFDR] = { 0x1c, 16 }, 281 [SCSPTR] = { 0x20, 16 }, 282 [SCLSR] = { 0x24, 16 }, 283 }, 284 .fifosize = 16, 285 .overrun_reg = SCLSR, 286 .overrun_mask = SCLSR_ORER, 287 .sampling_rate_mask = SCI_SR(32), 288 .error_mask = SCIF_DEFAULT_ERROR_MASK, 289 .error_clear = SCIF_ERROR_CLEAR, 290 }, 291 292 /* 293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 294 * It looks like a normal SCIF with FIFO data, but with a 295 * compressed address space. Also, the break out of interrupts 296 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 297 */ 298 [SCIx_RZ_SCIFA_REGTYPE] = { 299 .regs = { 300 [SCSMR] = { 0x00, 16 }, 301 [SCBRR] = { 0x02, 8 }, 302 [SCSCR] = { 0x04, 16 }, 303 [SCxTDR] = { 0x06, 8 }, 304 [SCxSR] = { 0x08, 16 }, 305 [SCxRDR] = { 0x0A, 8 }, 306 [SCFCR] = { 0x0C, 16 }, 307 [SCFDR] = { 0x0E, 16 }, 308 [SCSPTR] = { 0x10, 16 }, 309 [SCLSR] = { 0x12, 16 }, 310 [SEMR] = { 0x14, 8 }, 311 }, 312 .fifosize = 16, 313 .overrun_reg = SCLSR, 314 .overrun_mask = SCLSR_ORER, 315 .sampling_rate_mask = SCI_SR(32), 316 .error_mask = SCIF_DEFAULT_ERROR_MASK, 317 .error_clear = SCIF_ERROR_CLEAR, 318 }, 319 320 /* 321 * Common SH-3 SCIF definitions. 322 */ 323 [SCIx_SH3_SCIF_REGTYPE] = { 324 .regs = { 325 [SCSMR] = { 0x00, 8 }, 326 [SCBRR] = { 0x02, 8 }, 327 [SCSCR] = { 0x04, 8 }, 328 [SCxTDR] = { 0x06, 8 }, 329 [SCxSR] = { 0x08, 16 }, 330 [SCxRDR] = { 0x0a, 8 }, 331 [SCFCR] = { 0x0c, 8 }, 332 [SCFDR] = { 0x0e, 16 }, 333 }, 334 .fifosize = 16, 335 .overrun_reg = SCLSR, 336 .overrun_mask = SCLSR_ORER, 337 .sampling_rate_mask = SCI_SR(32), 338 .error_mask = SCIF_DEFAULT_ERROR_MASK, 339 .error_clear = SCIF_ERROR_CLEAR, 340 }, 341 342 /* 343 * Common SH-4(A) SCIF(B) definitions. 344 */ 345 [SCIx_SH4_SCIF_REGTYPE] = { 346 .regs = { 347 [SCSMR] = { 0x00, 16 }, 348 [SCBRR] = { 0x04, 8 }, 349 [SCSCR] = { 0x08, 16 }, 350 [SCxTDR] = { 0x0c, 8 }, 351 [SCxSR] = { 0x10, 16 }, 352 [SCxRDR] = { 0x14, 8 }, 353 [SCFCR] = { 0x18, 16 }, 354 [SCFDR] = { 0x1c, 16 }, 355 [SCSPTR] = { 0x20, 16 }, 356 [SCLSR] = { 0x24, 16 }, 357 }, 358 .fifosize = 16, 359 .overrun_reg = SCLSR, 360 .overrun_mask = SCLSR_ORER, 361 .sampling_rate_mask = SCI_SR(32), 362 .error_mask = SCIF_DEFAULT_ERROR_MASK, 363 .error_clear = SCIF_ERROR_CLEAR, 364 }, 365 366 /* 367 * Common SCIF definitions for ports with a Baud Rate Generator for 368 * External Clock (BRG). 369 */ 370 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 371 .regs = { 372 [SCSMR] = { 0x00, 16 }, 373 [SCBRR] = { 0x04, 8 }, 374 [SCSCR] = { 0x08, 16 }, 375 [SCxTDR] = { 0x0c, 8 }, 376 [SCxSR] = { 0x10, 16 }, 377 [SCxRDR] = { 0x14, 8 }, 378 [SCFCR] = { 0x18, 16 }, 379 [SCFDR] = { 0x1c, 16 }, 380 [SCSPTR] = { 0x20, 16 }, 381 [SCLSR] = { 0x24, 16 }, 382 [SCDL] = { 0x30, 16 }, 383 [SCCKS] = { 0x34, 16 }, 384 }, 385 .fifosize = 16, 386 .overrun_reg = SCLSR, 387 .overrun_mask = SCLSR_ORER, 388 .sampling_rate_mask = SCI_SR(32), 389 .error_mask = SCIF_DEFAULT_ERROR_MASK, 390 .error_clear = SCIF_ERROR_CLEAR, 391 }, 392 393 /* 394 * Common HSCIF definitions. 395 */ 396 [SCIx_HSCIF_REGTYPE] = { 397 .regs = { 398 [SCSMR] = { 0x00, 16 }, 399 [SCBRR] = { 0x04, 8 }, 400 [SCSCR] = { 0x08, 16 }, 401 [SCxTDR] = { 0x0c, 8 }, 402 [SCxSR] = { 0x10, 16 }, 403 [SCxRDR] = { 0x14, 8 }, 404 [SCFCR] = { 0x18, 16 }, 405 [SCFDR] = { 0x1c, 16 }, 406 [SCSPTR] = { 0x20, 16 }, 407 [SCLSR] = { 0x24, 16 }, 408 [HSSRR] = { 0x40, 16 }, 409 [SCDL] = { 0x30, 16 }, 410 [SCCKS] = { 0x34, 16 }, 411 [HSRTRGR] = { 0x54, 16 }, 412 [HSTTRGR] = { 0x58, 16 }, 413 }, 414 .fifosize = 128, 415 .overrun_reg = SCLSR, 416 .overrun_mask = SCLSR_ORER, 417 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 418 .error_mask = SCIF_DEFAULT_ERROR_MASK, 419 .error_clear = SCIF_ERROR_CLEAR, 420 }, 421 422 /* 423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 424 * register. 425 */ 426 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 427 .regs = { 428 [SCSMR] = { 0x00, 16 }, 429 [SCBRR] = { 0x04, 8 }, 430 [SCSCR] = { 0x08, 16 }, 431 [SCxTDR] = { 0x0c, 8 }, 432 [SCxSR] = { 0x10, 16 }, 433 [SCxRDR] = { 0x14, 8 }, 434 [SCFCR] = { 0x18, 16 }, 435 [SCFDR] = { 0x1c, 16 }, 436 [SCLSR] = { 0x24, 16 }, 437 }, 438 .fifosize = 16, 439 .overrun_reg = SCLSR, 440 .overrun_mask = SCLSR_ORER, 441 .sampling_rate_mask = SCI_SR(32), 442 .error_mask = SCIF_DEFAULT_ERROR_MASK, 443 .error_clear = SCIF_ERROR_CLEAR, 444 }, 445 446 /* 447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 448 * count registers. 449 */ 450 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 451 .regs = { 452 [SCSMR] = { 0x00, 16 }, 453 [SCBRR] = { 0x04, 8 }, 454 [SCSCR] = { 0x08, 16 }, 455 [SCxTDR] = { 0x0c, 8 }, 456 [SCxSR] = { 0x10, 16 }, 457 [SCxRDR] = { 0x14, 8 }, 458 [SCFCR] = { 0x18, 16 }, 459 [SCFDR] = { 0x1c, 16 }, 460 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 461 [SCRFDR] = { 0x20, 16 }, 462 [SCSPTR] = { 0x24, 16 }, 463 [SCLSR] = { 0x28, 16 }, 464 }, 465 .fifosize = 16, 466 .overrun_reg = SCLSR, 467 .overrun_mask = SCLSR_ORER, 468 .sampling_rate_mask = SCI_SR(32), 469 .error_mask = SCIF_DEFAULT_ERROR_MASK, 470 .error_clear = SCIF_ERROR_CLEAR, 471 }, 472 473 /* 474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 475 * registers. 476 */ 477 [SCIx_SH7705_SCIF_REGTYPE] = { 478 .regs = { 479 [SCSMR] = { 0x00, 16 }, 480 [SCBRR] = { 0x04, 8 }, 481 [SCSCR] = { 0x08, 16 }, 482 [SCxTDR] = { 0x20, 8 }, 483 [SCxSR] = { 0x14, 16 }, 484 [SCxRDR] = { 0x24, 8 }, 485 [SCFCR] = { 0x18, 16 }, 486 [SCFDR] = { 0x1c, 16 }, 487 }, 488 .fifosize = 64, 489 .overrun_reg = SCxSR, 490 .overrun_mask = SCIFA_ORER, 491 .sampling_rate_mask = SCI_SR(16), 492 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 493 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 494 }, 495}; 496 497#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 498 499/* 500 * The "offset" here is rather misleading, in that it refers to an enum 501 * value relative to the port mapping rather than the fixed offset 502 * itself, which needs to be manually retrieved from the platform's 503 * register map for the given port. 504 */ 505static unsigned int sci_serial_in(struct uart_port *p, int offset) 506{ 507 const struct plat_sci_reg *reg = sci_getreg(p, offset); 508 509 if (reg->size == 8) 510 return ioread8(p->membase + (reg->offset << p->regshift)); 511 else if (reg->size == 16) 512 return ioread16(p->membase + (reg->offset << p->regshift)); 513 else 514 WARN(1, "Invalid register access\n"); 515 516 return 0; 517} 518 519static void sci_serial_out(struct uart_port *p, int offset, int value) 520{ 521 const struct plat_sci_reg *reg = sci_getreg(p, offset); 522 523 if (reg->size == 8) 524 iowrite8(value, p->membase + (reg->offset << p->regshift)); 525 else if (reg->size == 16) 526 iowrite16(value, p->membase + (reg->offset << p->regshift)); 527 else 528 WARN(1, "Invalid register access\n"); 529} 530 531static void sci_port_enable(struct sci_port *sci_port) 532{ 533 unsigned int i; 534 535 if (!sci_port->port.dev) 536 return; 537 538 pm_runtime_get_sync(sci_port->port.dev); 539 540 for (i = 0; i < SCI_NUM_CLKS; i++) { 541 clk_prepare_enable(sci_port->clks[i]); 542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 543 } 544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 545} 546 547static void sci_port_disable(struct sci_port *sci_port) 548{ 549 unsigned int i; 550 551 if (!sci_port->port.dev) 552 return; 553 554 for (i = SCI_NUM_CLKS; i-- > 0; ) 555 clk_disable_unprepare(sci_port->clks[i]); 556 557 pm_runtime_put_sync(sci_port->port.dev); 558} 559 560static inline unsigned long port_rx_irq_mask(struct uart_port *port) 561{ 562 /* 563 * Not all ports (such as SCIFA) will support REIE. Rather than 564 * special-casing the port type, we check the port initialization 565 * IRQ enable mask to see whether the IRQ is desired at all. If 566 * it's unset, it's logically inferred that there's no point in 567 * testing for it. 568 */ 569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 570} 571 572static void sci_start_tx(struct uart_port *port) 573{ 574 struct sci_port *s = to_sci_port(port); 575 unsigned short ctrl; 576 577#ifdef CONFIG_SERIAL_SH_SCI_DMA 578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 579 u16 new, scr = sci_serial_in(port, SCSCR); 580 if (s->chan_tx) 581 new = scr | SCSCR_TDRQE; 582 else 583 new = scr & ~SCSCR_TDRQE; 584 if (new != scr) 585 sci_serial_out(port, SCSCR, new); 586 } 587 588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 589 dma_submit_error(s->cookie_tx)) { 590 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 591 /* Switch irq from SCIF to DMA */ 592 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); 593 594 s->cookie_tx = 0; 595 schedule_work(&s->work_tx); 596 } 597#endif 598 599 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || 600 port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 601 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 602 ctrl = sci_serial_in(port, SCSCR); 603 604 /* 605 * For SCI, TE (transmit enable) must be set after setting TIE 606 * (transmit interrupt enable) or in the same instruction to start 607 * the transmit process. 608 */ 609 if (port->type == PORT_SCI) 610 ctrl |= SCSCR_TE; 611 612 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE); 613 } 614} 615 616static void sci_stop_tx(struct uart_port *port) 617{ 618 unsigned short ctrl; 619 620 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 621 ctrl = sci_serial_in(port, SCSCR); 622 623 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 624 ctrl &= ~SCSCR_TDRQE; 625 626 ctrl &= ~SCSCR_TIE; 627 628 sci_serial_out(port, SCSCR, ctrl); 629 630#ifdef CONFIG_SERIAL_SH_SCI_DMA 631 if (to_sci_port(port)->chan_tx && 632 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 633 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 634 to_sci_port(port)->cookie_tx = -EINVAL; 635 } 636#endif 637} 638 639static void sci_start_rx(struct uart_port *port) 640{ 641 unsigned short ctrl; 642 643 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port); 644 645 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 646 ctrl &= ~SCSCR_RDRQE; 647 648 sci_serial_out(port, SCSCR, ctrl); 649} 650 651static void sci_stop_rx(struct uart_port *port) 652{ 653 unsigned short ctrl; 654 655 ctrl = sci_serial_in(port, SCSCR); 656 657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 658 ctrl &= ~SCSCR_RDRQE; 659 660 ctrl &= ~port_rx_irq_mask(port); 661 662 sci_serial_out(port, SCSCR, ctrl); 663} 664 665static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 666{ 667 if (port->type == PORT_SCI) { 668 /* Just store the mask */ 669 sci_serial_out(port, SCxSR, mask); 670 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 671 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 672 /* Only clear the status bits we want to clear */ 673 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask); 674 } else { 675 /* Store the mask, clear parity/framing errors */ 676 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 677 } 678} 679 680#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 681 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 682 683#ifdef CONFIG_CONSOLE_POLL 684static int sci_poll_get_char(struct uart_port *port) 685{ 686 unsigned short status; 687 int c; 688 689 do { 690 status = sci_serial_in(port, SCxSR); 691 if (status & SCxSR_ERRORS(port)) { 692 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 693 continue; 694 } 695 break; 696 } while (1); 697 698 if (!(status & SCxSR_RDxF(port))) 699 return NO_POLL_CHAR; 700 701 c = sci_serial_in(port, SCxRDR); 702 703 /* Dummy read */ 704 sci_serial_in(port, SCxSR); 705 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 706 707 return c; 708} 709#endif 710 711static void sci_poll_put_char(struct uart_port *port, unsigned char c) 712{ 713 unsigned short status; 714 715 do { 716 status = sci_serial_in(port, SCxSR); 717 } while (!(status & SCxSR_TDxE(port))); 718 719 sci_serial_out(port, SCxTDR, c); 720 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 721} 722#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 723 CONFIG_SERIAL_SH_SCI_EARLYCON */ 724 725static void sci_init_pins(struct uart_port *port, unsigned int cflag) 726{ 727 struct sci_port *s = to_sci_port(port); 728 729 /* 730 * Use port-specific handler if provided. 731 */ 732 if (s->cfg->ops && s->cfg->ops->init_pins) { 733 s->cfg->ops->init_pins(port, cflag); 734 return; 735 } 736 737 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 738 u16 data = sci_serial_in(port, SCPDR); 739 u16 ctrl = sci_serial_in(port, SCPCR); 740 741 /* Enable RXD and TXD pin functions */ 742 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 743 if (to_sci_port(port)->has_rtscts) { 744 /* RTS# is output, active low, unless autorts */ 745 if (!(port->mctrl & TIOCM_RTS)) { 746 ctrl |= SCPCR_RTSC; 747 data |= SCPDR_RTSD; 748 } else if (!s->autorts) { 749 ctrl |= SCPCR_RTSC; 750 data &= ~SCPDR_RTSD; 751 } else { 752 /* Enable RTS# pin function */ 753 ctrl &= ~SCPCR_RTSC; 754 } 755 /* Enable CTS# pin function */ 756 ctrl &= ~SCPCR_CTSC; 757 } 758 sci_serial_out(port, SCPDR, data); 759 sci_serial_out(port, SCPCR, ctrl); 760 } else if (sci_getreg(port, SCSPTR)->size) { 761 u16 status = sci_serial_in(port, SCSPTR); 762 763 /* RTS# is always output; and active low, unless autorts */ 764 status |= SCSPTR_RTSIO; 765 if (!(port->mctrl & TIOCM_RTS)) 766 status |= SCSPTR_RTSDT; 767 else if (!s->autorts) 768 status &= ~SCSPTR_RTSDT; 769 /* CTS# and SCK are inputs */ 770 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 771 sci_serial_out(port, SCSPTR, status); 772 } 773} 774 775static int sci_txfill(struct uart_port *port) 776{ 777 struct sci_port *s = to_sci_port(port); 778 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 779 const struct plat_sci_reg *reg; 780 781 reg = sci_getreg(port, SCTFDR); 782 if (reg->size) 783 return sci_serial_in(port, SCTFDR) & fifo_mask; 784 785 reg = sci_getreg(port, SCFDR); 786 if (reg->size) 787 return sci_serial_in(port, SCFDR) >> 8; 788 789 return !(sci_serial_in(port, SCxSR) & SCI_TDRE); 790} 791 792static int sci_txroom(struct uart_port *port) 793{ 794 return port->fifosize - sci_txfill(port); 795} 796 797static int sci_rxfill(struct uart_port *port) 798{ 799 struct sci_port *s = to_sci_port(port); 800 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 801 const struct plat_sci_reg *reg; 802 803 reg = sci_getreg(port, SCRFDR); 804 if (reg->size) 805 return sci_serial_in(port, SCRFDR) & fifo_mask; 806 807 reg = sci_getreg(port, SCFDR); 808 if (reg->size) 809 return sci_serial_in(port, SCFDR) & fifo_mask; 810 811 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 812} 813 814/* ********************************************************************** * 815 * the interrupt related routines * 816 * ********************************************************************** */ 817 818static void sci_transmit_chars(struct uart_port *port) 819{ 820 struct circ_buf *xmit = &port->state->xmit; 821 unsigned int stopped = uart_tx_stopped(port); 822 unsigned short status; 823 unsigned short ctrl; 824 int count; 825 826 status = sci_serial_in(port, SCxSR); 827 if (!(status & SCxSR_TDxE(port))) { 828 ctrl = sci_serial_in(port, SCSCR); 829 if (uart_circ_empty(xmit)) 830 ctrl &= ~SCSCR_TIE; 831 else 832 ctrl |= SCSCR_TIE; 833 sci_serial_out(port, SCSCR, ctrl); 834 return; 835 } 836 837 count = sci_txroom(port); 838 839 do { 840 unsigned char c; 841 842 if (port->x_char) { 843 c = port->x_char; 844 port->x_char = 0; 845 } else if (!uart_circ_empty(xmit) && !stopped) { 846 c = xmit->buf[xmit->tail]; 847 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 848 } else if (port->type == PORT_SCI && uart_circ_empty(xmit)) { 849 ctrl = sci_serial_in(port, SCSCR); 850 ctrl &= ~SCSCR_TE; 851 sci_serial_out(port, SCSCR, ctrl); 852 return; 853 } else { 854 break; 855 } 856 857 sci_serial_out(port, SCxTDR, c); 858 859 port->icount.tx++; 860 } while (--count > 0); 861 862 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 863 864 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 865 uart_write_wakeup(port); 866 if (uart_circ_empty(xmit)) { 867 if (port->type == PORT_SCI) { 868 ctrl = sci_serial_in(port, SCSCR); 869 ctrl &= ~SCSCR_TIE; 870 ctrl |= SCSCR_TEIE; 871 sci_serial_out(port, SCSCR, ctrl); 872 } 873 874 sci_stop_tx(port); 875 } 876} 877 878static void sci_receive_chars(struct uart_port *port) 879{ 880 struct tty_port *tport = &port->state->port; 881 int i, count, copied = 0; 882 unsigned short status; 883 unsigned char flag; 884 885 status = sci_serial_in(port, SCxSR); 886 if (!(status & SCxSR_RDxF(port))) 887 return; 888 889 while (1) { 890 /* Don't copy more bytes than there is room for in the buffer */ 891 count = tty_buffer_request_room(tport, sci_rxfill(port)); 892 893 /* If for any reason we can't copy more data, we're done! */ 894 if (count == 0) 895 break; 896 897 if (port->type == PORT_SCI) { 898 char c = sci_serial_in(port, SCxRDR); 899 if (uart_handle_sysrq_char(port, c)) 900 count = 0; 901 else 902 tty_insert_flip_char(tport, c, TTY_NORMAL); 903 } else { 904 for (i = 0; i < count; i++) { 905 char c; 906 907 if (port->type == PORT_SCIF || 908 port->type == PORT_HSCIF) { 909 status = sci_serial_in(port, SCxSR); 910 c = sci_serial_in(port, SCxRDR); 911 } else { 912 c = sci_serial_in(port, SCxRDR); 913 status = sci_serial_in(port, SCxSR); 914 } 915 if (uart_handle_sysrq_char(port, c)) { 916 count--; i--; 917 continue; 918 } 919 920 /* Store data and status */ 921 if (status & SCxSR_FER(port)) { 922 flag = TTY_FRAME; 923 port->icount.frame++; 924 } else if (status & SCxSR_PER(port)) { 925 flag = TTY_PARITY; 926 port->icount.parity++; 927 } else 928 flag = TTY_NORMAL; 929 930 tty_insert_flip_char(tport, c, flag); 931 } 932 } 933 934 sci_serial_in(port, SCxSR); /* dummy read */ 935 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 936 937 copied += count; 938 port->icount.rx += count; 939 } 940 941 if (copied) { 942 /* Tell the rest of the system the news. New characters! */ 943 tty_flip_buffer_push(tport); 944 } else { 945 /* TTY buffers full; read from RX reg to prevent lockup */ 946 sci_serial_in(port, SCxRDR); 947 sci_serial_in(port, SCxSR); /* dummy read */ 948 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 949 } 950} 951 952static int sci_handle_errors(struct uart_port *port) 953{ 954 int copied = 0; 955 unsigned short status = sci_serial_in(port, SCxSR); 956 struct tty_port *tport = &port->state->port; 957 struct sci_port *s = to_sci_port(port); 958 959 /* Handle overruns */ 960 if (status & s->params->overrun_mask) { 961 port->icount.overrun++; 962 963 /* overrun error */ 964 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 965 copied++; 966 } 967 968 if (status & SCxSR_FER(port)) { 969 /* frame error */ 970 port->icount.frame++; 971 972 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 973 copied++; 974 } 975 976 if (status & SCxSR_PER(port)) { 977 /* parity error */ 978 port->icount.parity++; 979 980 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 981 copied++; 982 } 983 984 if (copied) 985 tty_flip_buffer_push(tport); 986 987 return copied; 988} 989 990static int sci_handle_fifo_overrun(struct uart_port *port) 991{ 992 struct tty_port *tport = &port->state->port; 993 struct sci_port *s = to_sci_port(port); 994 const struct plat_sci_reg *reg; 995 int copied = 0; 996 u16 status; 997 998 reg = sci_getreg(port, s->params->overrun_reg); 999 if (!reg->size) 1000 return 0; 1001 1002 status = sci_serial_in(port, s->params->overrun_reg); 1003 if (status & s->params->overrun_mask) { 1004 status &= ~s->params->overrun_mask; 1005 sci_serial_out(port, s->params->overrun_reg, status); 1006 1007 port->icount.overrun++; 1008 1009 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1010 tty_flip_buffer_push(tport); 1011 copied++; 1012 } 1013 1014 return copied; 1015} 1016 1017static int sci_handle_breaks(struct uart_port *port) 1018{ 1019 int copied = 0; 1020 unsigned short status = sci_serial_in(port, SCxSR); 1021 struct tty_port *tport = &port->state->port; 1022 1023 if (uart_handle_break(port)) 1024 return 0; 1025 1026 if (status & SCxSR_BRK(port)) { 1027 port->icount.brk++; 1028 1029 /* Notify of BREAK */ 1030 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1031 copied++; 1032 } 1033 1034 if (copied) 1035 tty_flip_buffer_push(tport); 1036 1037 copied += sci_handle_fifo_overrun(port); 1038 1039 return copied; 1040} 1041 1042static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1043{ 1044 unsigned int bits; 1045 1046 if (rx_trig >= port->fifosize) 1047 rx_trig = port->fifosize - 1; 1048 if (rx_trig < 1) 1049 rx_trig = 1; 1050 1051 /* HSCIF can be set to an arbitrary level. */ 1052 if (sci_getreg(port, HSRTRGR)->size) { 1053 sci_serial_out(port, HSRTRGR, rx_trig); 1054 return rx_trig; 1055 } 1056 1057 switch (port->type) { 1058 case PORT_SCIF: 1059 if (rx_trig < 4) { 1060 bits = 0; 1061 rx_trig = 1; 1062 } else if (rx_trig < 8) { 1063 bits = SCFCR_RTRG0; 1064 rx_trig = 4; 1065 } else if (rx_trig < 14) { 1066 bits = SCFCR_RTRG1; 1067 rx_trig = 8; 1068 } else { 1069 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1070 rx_trig = 14; 1071 } 1072 break; 1073 case PORT_SCIFA: 1074 case PORT_SCIFB: 1075 if (rx_trig < 16) { 1076 bits = 0; 1077 rx_trig = 1; 1078 } else if (rx_trig < 32) { 1079 bits = SCFCR_RTRG0; 1080 rx_trig = 16; 1081 } else if (rx_trig < 48) { 1082 bits = SCFCR_RTRG1; 1083 rx_trig = 32; 1084 } else { 1085 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1086 rx_trig = 48; 1087 } 1088 break; 1089 default: 1090 WARN(1, "unknown FIFO configuration"); 1091 return 1; 1092 } 1093 1094 sci_serial_out(port, SCFCR, 1095 (sci_serial_in(port, SCFCR) & 1096 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1097 1098 return rx_trig; 1099} 1100 1101static int scif_rtrg_enabled(struct uart_port *port) 1102{ 1103 if (sci_getreg(port, HSRTRGR)->size) 1104 return sci_serial_in(port, HSRTRGR) != 0; 1105 else 1106 return (sci_serial_in(port, SCFCR) & 1107 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1108} 1109 1110static void rx_fifo_timer_fn(struct timer_list *t) 1111{ 1112 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1113 struct uart_port *port = &s->port; 1114 1115 dev_dbg(port->dev, "Rx timed out\n"); 1116 scif_set_rtrg(port, 1); 1117} 1118 1119static ssize_t rx_fifo_trigger_show(struct device *dev, 1120 struct device_attribute *attr, char *buf) 1121{ 1122 struct uart_port *port = dev_get_drvdata(dev); 1123 struct sci_port *sci = to_sci_port(port); 1124 1125 return sprintf(buf, "%d\n", sci->rx_trigger); 1126} 1127 1128static ssize_t rx_fifo_trigger_store(struct device *dev, 1129 struct device_attribute *attr, 1130 const char *buf, size_t count) 1131{ 1132 struct uart_port *port = dev_get_drvdata(dev); 1133 struct sci_port *sci = to_sci_port(port); 1134 int ret; 1135 long r; 1136 1137 ret = kstrtol(buf, 0, &r); 1138 if (ret) 1139 return ret; 1140 1141 sci->rx_trigger = scif_set_rtrg(port, r); 1142 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1143 scif_set_rtrg(port, 1); 1144 1145 return count; 1146} 1147 1148static DEVICE_ATTR_RW(rx_fifo_trigger); 1149 1150static ssize_t rx_fifo_timeout_show(struct device *dev, 1151 struct device_attribute *attr, 1152 char *buf) 1153{ 1154 struct uart_port *port = dev_get_drvdata(dev); 1155 struct sci_port *sci = to_sci_port(port); 1156 int v; 1157 1158 if (port->type == PORT_HSCIF) 1159 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1160 else 1161 v = sci->rx_fifo_timeout; 1162 1163 return sprintf(buf, "%d\n", v); 1164} 1165 1166static ssize_t rx_fifo_timeout_store(struct device *dev, 1167 struct device_attribute *attr, 1168 const char *buf, 1169 size_t count) 1170{ 1171 struct uart_port *port = dev_get_drvdata(dev); 1172 struct sci_port *sci = to_sci_port(port); 1173 int ret; 1174 long r; 1175 1176 ret = kstrtol(buf, 0, &r); 1177 if (ret) 1178 return ret; 1179 1180 if (port->type == PORT_HSCIF) { 1181 if (r < 0 || r > 3) 1182 return -EINVAL; 1183 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1184 } else { 1185 sci->rx_fifo_timeout = r; 1186 scif_set_rtrg(port, 1); 1187 if (r > 0) 1188 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1189 } 1190 1191 return count; 1192} 1193 1194static DEVICE_ATTR_RW(rx_fifo_timeout); 1195 1196 1197#ifdef CONFIG_SERIAL_SH_SCI_DMA 1198static void sci_dma_tx_complete(void *arg) 1199{ 1200 struct sci_port *s = arg; 1201 struct uart_port *port = &s->port; 1202 struct circ_buf *xmit = &port->state->xmit; 1203 unsigned long flags; 1204 1205 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1206 1207 uart_port_lock_irqsave(port, &flags); 1208 1209 uart_xmit_advance(port, s->tx_dma_len); 1210 1211 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1212 uart_write_wakeup(port); 1213 1214 if (!uart_circ_empty(xmit)) { 1215 s->cookie_tx = 0; 1216 schedule_work(&s->work_tx); 1217 } else { 1218 s->cookie_tx = -EINVAL; 1219 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1220 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1221 u16 ctrl = sci_serial_in(port, SCSCR); 1222 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1223 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1224 /* Switch irq from DMA to SCIF */ 1225 dmaengine_pause(s->chan_tx_saved); 1226 enable_irq(s->irqs[SCIx_TXI_IRQ]); 1227 } 1228 } 1229 } 1230 1231 uart_port_unlock_irqrestore(port, flags); 1232} 1233 1234/* Locking: called with port lock held */ 1235static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1236{ 1237 struct uart_port *port = &s->port; 1238 struct tty_port *tport = &port->state->port; 1239 int copied; 1240 1241 copied = tty_insert_flip_string(tport, buf, count); 1242 if (copied < count) 1243 port->icount.buf_overrun++; 1244 1245 port->icount.rx += copied; 1246 1247 return copied; 1248} 1249 1250static int sci_dma_rx_find_active(struct sci_port *s) 1251{ 1252 unsigned int i; 1253 1254 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1255 if (s->active_rx == s->cookie_rx[i]) 1256 return i; 1257 1258 return -1; 1259} 1260 1261static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1262{ 1263 unsigned int i; 1264 1265 s->chan_rx = NULL; 1266 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1267 s->cookie_rx[i] = -EINVAL; 1268 s->active_rx = 0; 1269} 1270 1271static void sci_dma_rx_release(struct sci_port *s) 1272{ 1273 struct dma_chan *chan = s->chan_rx_saved; 1274 1275 s->chan_rx_saved = NULL; 1276 sci_dma_rx_chan_invalidate(s); 1277 dmaengine_terminate_sync(chan); 1278 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1279 sg_dma_address(&s->sg_rx[0])); 1280 dma_release_channel(chan); 1281} 1282 1283static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1284{ 1285 long sec = usec / 1000000; 1286 long nsec = (usec % 1000000) * 1000; 1287 ktime_t t = ktime_set(sec, nsec); 1288 1289 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1290} 1291 1292static void sci_dma_rx_reenable_irq(struct sci_port *s) 1293{ 1294 struct uart_port *port = &s->port; 1295 u16 scr; 1296 1297 /* Direct new serial port interrupts back to CPU */ 1298 scr = sci_serial_in(port, SCSCR); 1299 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1300 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1301 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1302 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1303 scif_set_rtrg(port, s->rx_trigger); 1304 else 1305 scr &= ~SCSCR_RDRQE; 1306 } 1307 sci_serial_out(port, SCSCR, scr | SCSCR_RIE); 1308} 1309 1310static void sci_dma_rx_complete(void *arg) 1311{ 1312 struct sci_port *s = arg; 1313 struct dma_chan *chan = s->chan_rx; 1314 struct uart_port *port = &s->port; 1315 struct dma_async_tx_descriptor *desc; 1316 unsigned long flags; 1317 int active, count = 0; 1318 1319 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1320 s->active_rx); 1321 1322 uart_port_lock_irqsave(port, &flags); 1323 1324 active = sci_dma_rx_find_active(s); 1325 if (active >= 0) 1326 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1327 1328 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1329 1330 if (count) 1331 tty_flip_buffer_push(&port->state->port); 1332 1333 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1334 DMA_DEV_TO_MEM, 1335 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1336 if (!desc) 1337 goto fail; 1338 1339 desc->callback = sci_dma_rx_complete; 1340 desc->callback_param = s; 1341 s->cookie_rx[active] = dmaengine_submit(desc); 1342 if (dma_submit_error(s->cookie_rx[active])) 1343 goto fail; 1344 1345 s->active_rx = s->cookie_rx[!active]; 1346 1347 dma_async_issue_pending(chan); 1348 1349 uart_port_unlock_irqrestore(port, flags); 1350 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1351 __func__, s->cookie_rx[active], active, s->active_rx); 1352 return; 1353 1354fail: 1355 uart_port_unlock_irqrestore(port, flags); 1356 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1357 /* Switch to PIO */ 1358 uart_port_lock_irqsave(port, &flags); 1359 dmaengine_terminate_async(chan); 1360 sci_dma_rx_chan_invalidate(s); 1361 sci_dma_rx_reenable_irq(s); 1362 uart_port_unlock_irqrestore(port, flags); 1363} 1364 1365static void sci_dma_tx_release(struct sci_port *s) 1366{ 1367 struct dma_chan *chan = s->chan_tx_saved; 1368 1369 cancel_work_sync(&s->work_tx); 1370 s->chan_tx_saved = s->chan_tx = NULL; 1371 s->cookie_tx = -EINVAL; 1372 dmaengine_terminate_sync(chan); 1373 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1374 DMA_TO_DEVICE); 1375 dma_release_channel(chan); 1376} 1377 1378static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1379{ 1380 struct dma_chan *chan = s->chan_rx; 1381 struct uart_port *port = &s->port; 1382 unsigned long flags; 1383 int i; 1384 1385 for (i = 0; i < 2; i++) { 1386 struct scatterlist *sg = &s->sg_rx[i]; 1387 struct dma_async_tx_descriptor *desc; 1388 1389 desc = dmaengine_prep_slave_sg(chan, 1390 sg, 1, DMA_DEV_TO_MEM, 1391 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1392 if (!desc) 1393 goto fail; 1394 1395 desc->callback = sci_dma_rx_complete; 1396 desc->callback_param = s; 1397 s->cookie_rx[i] = dmaengine_submit(desc); 1398 if (dma_submit_error(s->cookie_rx[i])) 1399 goto fail; 1400 1401 } 1402 1403 s->active_rx = s->cookie_rx[0]; 1404 1405 dma_async_issue_pending(chan); 1406 return 0; 1407 1408fail: 1409 /* Switch to PIO */ 1410 if (!port_lock_held) 1411 uart_port_lock_irqsave(port, &flags); 1412 if (i) 1413 dmaengine_terminate_async(chan); 1414 sci_dma_rx_chan_invalidate(s); 1415 sci_start_rx(port); 1416 if (!port_lock_held) 1417 uart_port_unlock_irqrestore(port, flags); 1418 return -EAGAIN; 1419} 1420 1421static void sci_dma_tx_work_fn(struct work_struct *work) 1422{ 1423 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1424 struct dma_async_tx_descriptor *desc; 1425 struct dma_chan *chan = s->chan_tx; 1426 struct uart_port *port = &s->port; 1427 struct circ_buf *xmit = &port->state->xmit; 1428 unsigned long flags; 1429 dma_addr_t buf; 1430 int head, tail; 1431 1432 /* 1433 * DMA is idle now. 1434 * Port xmit buffer is already mapped, and it is one page... Just adjust 1435 * offsets and lengths. Since it is a circular buffer, we have to 1436 * transmit till the end, and then the rest. Take the port lock to get a 1437 * consistent xmit buffer state. 1438 */ 1439 uart_port_lock_irq(port); 1440 head = xmit->head; 1441 tail = xmit->tail; 1442 buf = s->tx_dma_addr + tail; 1443 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE); 1444 if (!s->tx_dma_len) { 1445 /* Transmit buffer has been flushed */ 1446 uart_port_unlock_irq(port); 1447 return; 1448 } 1449 1450 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1451 DMA_MEM_TO_DEV, 1452 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1453 if (!desc) { 1454 uart_port_unlock_irq(port); 1455 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1456 goto switch_to_pio; 1457 } 1458 1459 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1460 DMA_TO_DEVICE); 1461 1462 desc->callback = sci_dma_tx_complete; 1463 desc->callback_param = s; 1464 s->cookie_tx = dmaengine_submit(desc); 1465 if (dma_submit_error(s->cookie_tx)) { 1466 uart_port_unlock_irq(port); 1467 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1468 goto switch_to_pio; 1469 } 1470 1471 uart_port_unlock_irq(port); 1472 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1473 __func__, xmit->buf, tail, head, s->cookie_tx); 1474 1475 dma_async_issue_pending(chan); 1476 return; 1477 1478switch_to_pio: 1479 uart_port_lock_irqsave(port, &flags); 1480 s->chan_tx = NULL; 1481 sci_start_tx(port); 1482 uart_port_unlock_irqrestore(port, flags); 1483 return; 1484} 1485 1486static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1487{ 1488 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1489 struct dma_chan *chan = s->chan_rx; 1490 struct uart_port *port = &s->port; 1491 struct dma_tx_state state; 1492 enum dma_status status; 1493 unsigned long flags; 1494 unsigned int read; 1495 int active, count; 1496 1497 dev_dbg(port->dev, "DMA Rx timed out\n"); 1498 1499 uart_port_lock_irqsave(port, &flags); 1500 1501 active = sci_dma_rx_find_active(s); 1502 if (active < 0) { 1503 uart_port_unlock_irqrestore(port, flags); 1504 return HRTIMER_NORESTART; 1505 } 1506 1507 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1508 if (status == DMA_COMPLETE) { 1509 uart_port_unlock_irqrestore(port, flags); 1510 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1511 s->active_rx, active); 1512 1513 /* Let packet complete handler take care of the packet */ 1514 return HRTIMER_NORESTART; 1515 } 1516 1517 dmaengine_pause(chan); 1518 1519 /* 1520 * sometimes DMA transfer doesn't stop even if it is stopped and 1521 * data keeps on coming until transaction is complete so check 1522 * for DMA_COMPLETE again 1523 * Let packet complete handler take care of the packet 1524 */ 1525 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1526 if (status == DMA_COMPLETE) { 1527 uart_port_unlock_irqrestore(port, flags); 1528 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1529 return HRTIMER_NORESTART; 1530 } 1531 1532 /* Handle incomplete DMA receive */ 1533 dmaengine_terminate_async(s->chan_rx); 1534 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1535 1536 if (read) { 1537 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1538 if (count) 1539 tty_flip_buffer_push(&port->state->port); 1540 } 1541 1542 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1543 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1544 sci_dma_rx_submit(s, true); 1545 1546 sci_dma_rx_reenable_irq(s); 1547 1548 uart_port_unlock_irqrestore(port, flags); 1549 1550 return HRTIMER_NORESTART; 1551} 1552 1553static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1554 enum dma_transfer_direction dir) 1555{ 1556 struct dma_chan *chan; 1557 struct dma_slave_config cfg; 1558 int ret; 1559 1560 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1561 if (IS_ERR(chan)) { 1562 dev_dbg(port->dev, "dma_request_chan failed\n"); 1563 return NULL; 1564 } 1565 1566 memset(&cfg, 0, sizeof(cfg)); 1567 cfg.direction = dir; 1568 cfg.dst_addr = port->mapbase + 1569 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1570 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1571 cfg.src_addr = port->mapbase + 1572 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1573 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1574 1575 ret = dmaengine_slave_config(chan, &cfg); 1576 if (ret) { 1577 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1578 dma_release_channel(chan); 1579 return NULL; 1580 } 1581 1582 return chan; 1583} 1584 1585static void sci_request_dma(struct uart_port *port) 1586{ 1587 struct sci_port *s = to_sci_port(port); 1588 struct dma_chan *chan; 1589 1590 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1591 1592 /* 1593 * DMA on console may interfere with Kernel log messages which use 1594 * plain putchar(). So, simply don't use it with a console. 1595 */ 1596 if (uart_console(port)) 1597 return; 1598 1599 if (!port->dev->of_node) 1600 return; 1601 1602 s->cookie_tx = -EINVAL; 1603 1604 /* 1605 * Don't request a dma channel if no channel was specified 1606 * in the device tree. 1607 */ 1608 if (!of_property_present(port->dev->of_node, "dmas")) 1609 return; 1610 1611 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1612 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1613 if (chan) { 1614 /* UART circular tx buffer is an aligned page. */ 1615 s->tx_dma_addr = dma_map_single(chan->device->dev, 1616 port->state->xmit.buf, 1617 UART_XMIT_SIZE, 1618 DMA_TO_DEVICE); 1619 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1620 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1621 dma_release_channel(chan); 1622 } else { 1623 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1624 __func__, UART_XMIT_SIZE, 1625 port->state->xmit.buf, &s->tx_dma_addr); 1626 1627 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1628 s->chan_tx_saved = s->chan_tx = chan; 1629 } 1630 } 1631 1632 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1633 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1634 if (chan) { 1635 unsigned int i; 1636 dma_addr_t dma; 1637 void *buf; 1638 1639 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1640 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1641 &dma, GFP_KERNEL); 1642 if (!buf) { 1643 dev_warn(port->dev, 1644 "Failed to allocate Rx dma buffer, using PIO\n"); 1645 dma_release_channel(chan); 1646 return; 1647 } 1648 1649 for (i = 0; i < 2; i++) { 1650 struct scatterlist *sg = &s->sg_rx[i]; 1651 1652 sg_init_table(sg, 1); 1653 s->rx_buf[i] = buf; 1654 sg_dma_address(sg) = dma; 1655 sg_dma_len(sg) = s->buf_len_rx; 1656 1657 buf += s->buf_len_rx; 1658 dma += s->buf_len_rx; 1659 } 1660 1661 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1662 s->rx_timer.function = sci_dma_rx_timer_fn; 1663 1664 s->chan_rx_saved = s->chan_rx = chan; 1665 1666 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1667 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1668 sci_dma_rx_submit(s, false); 1669 } 1670} 1671 1672static void sci_free_dma(struct uart_port *port) 1673{ 1674 struct sci_port *s = to_sci_port(port); 1675 1676 if (s->chan_tx_saved) 1677 sci_dma_tx_release(s); 1678 if (s->chan_rx_saved) 1679 sci_dma_rx_release(s); 1680} 1681 1682static void sci_flush_buffer(struct uart_port *port) 1683{ 1684 struct sci_port *s = to_sci_port(port); 1685 1686 /* 1687 * In uart_flush_buffer(), the xmit circular buffer has just been 1688 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1689 * pending transfers 1690 */ 1691 s->tx_dma_len = 0; 1692 if (s->chan_tx) { 1693 dmaengine_terminate_async(s->chan_tx); 1694 s->cookie_tx = -EINVAL; 1695 } 1696} 1697#else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1698static inline void sci_request_dma(struct uart_port *port) 1699{ 1700} 1701 1702static inline void sci_free_dma(struct uart_port *port) 1703{ 1704} 1705 1706#define sci_flush_buffer NULL 1707#endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1708 1709static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1710{ 1711 struct uart_port *port = ptr; 1712 struct sci_port *s = to_sci_port(port); 1713 1714#ifdef CONFIG_SERIAL_SH_SCI_DMA 1715 if (s->chan_rx) { 1716 u16 scr = sci_serial_in(port, SCSCR); 1717 u16 ssr = sci_serial_in(port, SCxSR); 1718 1719 /* Disable future Rx interrupts */ 1720 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1721 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1722 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); 1723 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1724 scif_set_rtrg(port, 1); 1725 scr |= SCSCR_RIE; 1726 } else { 1727 scr |= SCSCR_RDRQE; 1728 } 1729 } else { 1730 if (sci_dma_rx_submit(s, false) < 0) 1731 goto handle_pio; 1732 1733 scr &= ~SCSCR_RIE; 1734 } 1735 sci_serial_out(port, SCSCR, scr); 1736 /* Clear current interrupt */ 1737 sci_serial_out(port, SCxSR, 1738 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1739 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1740 jiffies, s->rx_timeout); 1741 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1742 1743 return IRQ_HANDLED; 1744 } 1745 1746handle_pio: 1747#endif 1748 1749 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1750 if (!scif_rtrg_enabled(port)) 1751 scif_set_rtrg(port, s->rx_trigger); 1752 1753 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1754 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1755 } 1756 1757 /* I think sci_receive_chars has to be called irrespective 1758 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1759 * to be disabled? 1760 */ 1761 sci_receive_chars(port); 1762 1763 return IRQ_HANDLED; 1764} 1765 1766static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1767{ 1768 struct uart_port *port = ptr; 1769 unsigned long flags; 1770 1771 uart_port_lock_irqsave(port, &flags); 1772 sci_transmit_chars(port); 1773 uart_port_unlock_irqrestore(port, flags); 1774 1775 return IRQ_HANDLED; 1776} 1777 1778static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) 1779{ 1780 struct uart_port *port = ptr; 1781 unsigned long flags; 1782 unsigned short ctrl; 1783 1784 if (port->type != PORT_SCI) 1785 return sci_tx_interrupt(irq, ptr); 1786 1787 uart_port_lock_irqsave(port, &flags); 1788 ctrl = sci_serial_in(port, SCSCR); 1789 ctrl &= ~(SCSCR_TE | SCSCR_TEIE); 1790 sci_serial_out(port, SCSCR, ctrl); 1791 uart_port_unlock_irqrestore(port, flags); 1792 1793 return IRQ_HANDLED; 1794} 1795 1796static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1797{ 1798 struct uart_port *port = ptr; 1799 1800 /* Handle BREAKs */ 1801 sci_handle_breaks(port); 1802 1803 /* drop invalid character received before break was detected */ 1804 sci_serial_in(port, SCxRDR); 1805 1806 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1807 1808 return IRQ_HANDLED; 1809} 1810 1811static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1812{ 1813 struct uart_port *port = ptr; 1814 struct sci_port *s = to_sci_port(port); 1815 1816 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1817 /* Break and Error interrupts are muxed */ 1818 unsigned short ssr_status = sci_serial_in(port, SCxSR); 1819 1820 /* Break Interrupt */ 1821 if (ssr_status & SCxSR_BRK(port)) 1822 sci_br_interrupt(irq, ptr); 1823 1824 /* Break only? */ 1825 if (!(ssr_status & SCxSR_ERRORS(port))) 1826 return IRQ_HANDLED; 1827 } 1828 1829 /* Handle errors */ 1830 if (port->type == PORT_SCI) { 1831 if (sci_handle_errors(port)) { 1832 /* discard character in rx buffer */ 1833 sci_serial_in(port, SCxSR); 1834 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1835 } 1836 } else { 1837 sci_handle_fifo_overrun(port); 1838 if (!s->chan_rx) 1839 sci_receive_chars(port); 1840 } 1841 1842 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1843 1844 /* Kick the transmission */ 1845 if (!s->chan_tx) 1846 sci_tx_interrupt(irq, ptr); 1847 1848 return IRQ_HANDLED; 1849} 1850 1851static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1852{ 1853 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1854 struct uart_port *port = ptr; 1855 struct sci_port *s = to_sci_port(port); 1856 irqreturn_t ret = IRQ_NONE; 1857 1858 ssr_status = sci_serial_in(port, SCxSR); 1859 scr_status = sci_serial_in(port, SCSCR); 1860 if (s->params->overrun_reg == SCxSR) 1861 orer_status = ssr_status; 1862 else if (sci_getreg(port, s->params->overrun_reg)->size) 1863 orer_status = sci_serial_in(port, s->params->overrun_reg); 1864 1865 err_enabled = scr_status & port_rx_irq_mask(port); 1866 1867 /* Tx Interrupt */ 1868 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1869 !s->chan_tx) 1870 ret = sci_tx_interrupt(irq, ptr); 1871 1872 /* 1873 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1874 * DR flags 1875 */ 1876 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1877 (scr_status & SCSCR_RIE)) 1878 ret = sci_rx_interrupt(irq, ptr); 1879 1880 /* Error Interrupt */ 1881 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1882 ret = sci_er_interrupt(irq, ptr); 1883 1884 /* Break Interrupt */ 1885 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 1886 (ssr_status & SCxSR_BRK(port)) && err_enabled) 1887 ret = sci_br_interrupt(irq, ptr); 1888 1889 /* Overrun Interrupt */ 1890 if (orer_status & s->params->overrun_mask) { 1891 sci_handle_fifo_overrun(port); 1892 ret = IRQ_HANDLED; 1893 } 1894 1895 return ret; 1896} 1897 1898static const struct sci_irq_desc { 1899 const char *desc; 1900 irq_handler_t handler; 1901} sci_irq_desc[] = { 1902 /* 1903 * Split out handlers, the default case. 1904 */ 1905 [SCIx_ERI_IRQ] = { 1906 .desc = "rx err", 1907 .handler = sci_er_interrupt, 1908 }, 1909 1910 [SCIx_RXI_IRQ] = { 1911 .desc = "rx full", 1912 .handler = sci_rx_interrupt, 1913 }, 1914 1915 [SCIx_TXI_IRQ] = { 1916 .desc = "tx empty", 1917 .handler = sci_tx_interrupt, 1918 }, 1919 1920 [SCIx_BRI_IRQ] = { 1921 .desc = "break", 1922 .handler = sci_br_interrupt, 1923 }, 1924 1925 [SCIx_DRI_IRQ] = { 1926 .desc = "rx ready", 1927 .handler = sci_rx_interrupt, 1928 }, 1929 1930 [SCIx_TEI_IRQ] = { 1931 .desc = "tx end", 1932 .handler = sci_tx_end_interrupt, 1933 }, 1934 1935 /* 1936 * Special muxed handler. 1937 */ 1938 [SCIx_MUX_IRQ] = { 1939 .desc = "mux", 1940 .handler = sci_mpxed_interrupt, 1941 }, 1942}; 1943 1944static int sci_request_irq(struct sci_port *port) 1945{ 1946 struct uart_port *up = &port->port; 1947 int i, j, w, ret = 0; 1948 1949 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1950 const struct sci_irq_desc *desc; 1951 int irq; 1952 1953 /* Check if already registered (muxed) */ 1954 for (w = 0; w < i; w++) 1955 if (port->irqs[w] == port->irqs[i]) 1956 w = i + 1; 1957 if (w > i) 1958 continue; 1959 1960 if (SCIx_IRQ_IS_MUXED(port)) { 1961 i = SCIx_MUX_IRQ; 1962 irq = up->irq; 1963 } else { 1964 irq = port->irqs[i]; 1965 1966 /* 1967 * Certain port types won't support all of the 1968 * available interrupt sources. 1969 */ 1970 if (unlikely(irq < 0)) 1971 continue; 1972 } 1973 1974 desc = sci_irq_desc + i; 1975 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1976 dev_name(up->dev), desc->desc); 1977 if (!port->irqstr[j]) { 1978 ret = -ENOMEM; 1979 goto out_nomem; 1980 } 1981 1982 ret = request_irq(irq, desc->handler, up->irqflags, 1983 port->irqstr[j], port); 1984 if (unlikely(ret)) { 1985 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1986 goto out_noirq; 1987 } 1988 } 1989 1990 return 0; 1991 1992out_noirq: 1993 while (--i >= 0) 1994 free_irq(port->irqs[i], port); 1995 1996out_nomem: 1997 while (--j >= 0) 1998 kfree(port->irqstr[j]); 1999 2000 return ret; 2001} 2002 2003static void sci_free_irq(struct sci_port *port) 2004{ 2005 int i, j; 2006 2007 /* 2008 * Intentionally in reverse order so we iterate over the muxed 2009 * IRQ first. 2010 */ 2011 for (i = 0; i < SCIx_NR_IRQS; i++) { 2012 int irq = port->irqs[i]; 2013 2014 /* 2015 * Certain port types won't support all of the available 2016 * interrupt sources. 2017 */ 2018 if (unlikely(irq < 0)) 2019 continue; 2020 2021 /* Check if already freed (irq was muxed) */ 2022 for (j = 0; j < i; j++) 2023 if (port->irqs[j] == irq) 2024 j = i + 1; 2025 if (j > i) 2026 continue; 2027 2028 free_irq(port->irqs[i], port); 2029 kfree(port->irqstr[i]); 2030 2031 if (SCIx_IRQ_IS_MUXED(port)) { 2032 /* If there's only one IRQ, we're done. */ 2033 return; 2034 } 2035 } 2036} 2037 2038static unsigned int sci_tx_empty(struct uart_port *port) 2039{ 2040 unsigned short status = sci_serial_in(port, SCxSR); 2041 unsigned short in_tx_fifo = sci_txfill(port); 2042 2043 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 2044} 2045 2046static void sci_set_rts(struct uart_port *port, bool state) 2047{ 2048 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2049 u16 data = sci_serial_in(port, SCPDR); 2050 2051 /* Active low */ 2052 if (state) 2053 data &= ~SCPDR_RTSD; 2054 else 2055 data |= SCPDR_RTSD; 2056 sci_serial_out(port, SCPDR, data); 2057 2058 /* RTS# is output */ 2059 sci_serial_out(port, SCPCR, 2060 sci_serial_in(port, SCPCR) | SCPCR_RTSC); 2061 } else if (sci_getreg(port, SCSPTR)->size) { 2062 u16 ctrl = sci_serial_in(port, SCSPTR); 2063 2064 /* Active low */ 2065 if (state) 2066 ctrl &= ~SCSPTR_RTSDT; 2067 else 2068 ctrl |= SCSPTR_RTSDT; 2069 sci_serial_out(port, SCSPTR, ctrl); 2070 } 2071} 2072 2073static bool sci_get_cts(struct uart_port *port) 2074{ 2075 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2076 /* Active low */ 2077 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD); 2078 } else if (sci_getreg(port, SCSPTR)->size) { 2079 /* Active low */ 2080 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT); 2081 } 2082 2083 return true; 2084} 2085 2086/* 2087 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2088 * CTS/RTS is supported in hardware by at least one port and controlled 2089 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2090 * handled via the ->init_pins() op, which is a bit of a one-way street, 2091 * lacking any ability to defer pin control -- this will later be 2092 * converted over to the GPIO framework). 2093 * 2094 * Other modes (such as loopback) are supported generically on certain 2095 * port types, but not others. For these it's sufficient to test for the 2096 * existence of the support register and simply ignore the port type. 2097 */ 2098static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2099{ 2100 struct sci_port *s = to_sci_port(port); 2101 2102 if (mctrl & TIOCM_LOOP) { 2103 const struct plat_sci_reg *reg; 2104 2105 /* 2106 * Standard loopback mode for SCFCR ports. 2107 */ 2108 reg = sci_getreg(port, SCFCR); 2109 if (reg->size) 2110 sci_serial_out(port, SCFCR, 2111 sci_serial_in(port, SCFCR) | SCFCR_LOOP); 2112 } 2113 2114 mctrl_gpio_set(s->gpios, mctrl); 2115 2116 if (!s->has_rtscts) 2117 return; 2118 2119 if (!(mctrl & TIOCM_RTS)) { 2120 /* Disable Auto RTS */ 2121 sci_serial_out(port, SCFCR, 2122 sci_serial_in(port, SCFCR) & ~SCFCR_MCE); 2123 2124 /* Clear RTS */ 2125 sci_set_rts(port, 0); 2126 } else if (s->autorts) { 2127 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2128 /* Enable RTS# pin function */ 2129 sci_serial_out(port, SCPCR, 2130 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC); 2131 } 2132 2133 /* Enable Auto RTS */ 2134 sci_serial_out(port, SCFCR, 2135 sci_serial_in(port, SCFCR) | SCFCR_MCE); 2136 } else { 2137 /* Set RTS */ 2138 sci_set_rts(port, 1); 2139 } 2140} 2141 2142static unsigned int sci_get_mctrl(struct uart_port *port) 2143{ 2144 struct sci_port *s = to_sci_port(port); 2145 struct mctrl_gpios *gpios = s->gpios; 2146 unsigned int mctrl = 0; 2147 2148 mctrl_gpio_get(gpios, &mctrl); 2149 2150 /* 2151 * CTS/RTS is handled in hardware when supported, while nothing 2152 * else is wired up. 2153 */ 2154 if (s->autorts) { 2155 if (sci_get_cts(port)) 2156 mctrl |= TIOCM_CTS; 2157 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2158 mctrl |= TIOCM_CTS; 2159 } 2160 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2161 mctrl |= TIOCM_DSR; 2162 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2163 mctrl |= TIOCM_CAR; 2164 2165 return mctrl; 2166} 2167 2168static void sci_enable_ms(struct uart_port *port) 2169{ 2170 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2171} 2172 2173static void sci_break_ctl(struct uart_port *port, int break_state) 2174{ 2175 unsigned short scscr, scsptr; 2176 unsigned long flags; 2177 2178 /* check whether the port has SCSPTR */ 2179 if (!sci_getreg(port, SCSPTR)->size) { 2180 /* 2181 * Not supported by hardware. Most parts couple break and rx 2182 * interrupts together, with break detection always enabled. 2183 */ 2184 return; 2185 } 2186 2187 uart_port_lock_irqsave(port, &flags); 2188 scsptr = sci_serial_in(port, SCSPTR); 2189 scscr = sci_serial_in(port, SCSCR); 2190 2191 if (break_state == -1) { 2192 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2193 scscr &= ~SCSCR_TE; 2194 } else { 2195 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2196 scscr |= SCSCR_TE; 2197 } 2198 2199 sci_serial_out(port, SCSPTR, scsptr); 2200 sci_serial_out(port, SCSCR, scscr); 2201 uart_port_unlock_irqrestore(port, flags); 2202} 2203 2204static int sci_startup(struct uart_port *port) 2205{ 2206 struct sci_port *s = to_sci_port(port); 2207 int ret; 2208 2209 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2210 2211 sci_request_dma(port); 2212 2213 ret = sci_request_irq(s); 2214 if (unlikely(ret < 0)) { 2215 sci_free_dma(port); 2216 return ret; 2217 } 2218 2219 return 0; 2220} 2221 2222static void sci_shutdown(struct uart_port *port) 2223{ 2224 struct sci_port *s = to_sci_port(port); 2225 unsigned long flags; 2226 u16 scr; 2227 2228 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2229 2230 s->autorts = false; 2231 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2232 2233 uart_port_lock_irqsave(port, &flags); 2234 sci_stop_rx(port); 2235 sci_stop_tx(port); 2236 /* 2237 * Stop RX and TX, disable related interrupts, keep clock source 2238 * and HSCIF TOT bits 2239 */ 2240 scr = sci_serial_in(port, SCSCR); 2241 sci_serial_out(port, SCSCR, 2242 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2243 uart_port_unlock_irqrestore(port, flags); 2244 2245#ifdef CONFIG_SERIAL_SH_SCI_DMA 2246 if (s->chan_rx_saved) { 2247 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2248 port->line); 2249 hrtimer_cancel(&s->rx_timer); 2250 } 2251#endif 2252 2253 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2254 del_timer_sync(&s->rx_fifo_timer); 2255 sci_free_irq(s); 2256 sci_free_dma(port); 2257} 2258 2259static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2260 unsigned int *srr) 2261{ 2262 unsigned long freq = s->clk_rates[SCI_SCK]; 2263 int err, min_err = INT_MAX; 2264 unsigned int sr; 2265 2266 if (s->port.type != PORT_HSCIF) 2267 freq *= 2; 2268 2269 for_each_sr(sr, s) { 2270 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2271 if (abs(err) >= abs(min_err)) 2272 continue; 2273 2274 min_err = err; 2275 *srr = sr - 1; 2276 2277 if (!err) 2278 break; 2279 } 2280 2281 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2282 *srr + 1); 2283 return min_err; 2284} 2285 2286static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2287 unsigned long freq, unsigned int *dlr, 2288 unsigned int *srr) 2289{ 2290 int err, min_err = INT_MAX; 2291 unsigned int sr, dl; 2292 2293 if (s->port.type != PORT_HSCIF) 2294 freq *= 2; 2295 2296 for_each_sr(sr, s) { 2297 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2298 dl = clamp(dl, 1U, 65535U); 2299 2300 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2301 if (abs(err) >= abs(min_err)) 2302 continue; 2303 2304 min_err = err; 2305 *dlr = dl; 2306 *srr = sr - 1; 2307 2308 if (!err) 2309 break; 2310 } 2311 2312 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2313 min_err, *dlr, *srr + 1); 2314 return min_err; 2315} 2316 2317/* calculate sample rate, BRR, and clock select */ 2318static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2319 unsigned int *brr, unsigned int *srr, 2320 unsigned int *cks) 2321{ 2322 unsigned long freq = s->clk_rates[SCI_FCK]; 2323 unsigned int sr, br, prediv, scrate, c; 2324 int err, min_err = INT_MAX; 2325 2326 if (s->port.type != PORT_HSCIF) 2327 freq *= 2; 2328 2329 /* 2330 * Find the combination of sample rate and clock select with the 2331 * smallest deviation from the desired baud rate. 2332 * Prefer high sample rates to maximise the receive margin. 2333 * 2334 * M: Receive margin (%) 2335 * N: Ratio of bit rate to clock (N = sampling rate) 2336 * D: Clock duty (D = 0 to 1.0) 2337 * L: Frame length (L = 9 to 12) 2338 * F: Absolute value of clock frequency deviation 2339 * 2340 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2341 * (|D - 0.5| / N * (1 + F))| 2342 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2343 */ 2344 for_each_sr(sr, s) { 2345 for (c = 0; c <= 3; c++) { 2346 /* integerized formulas from HSCIF documentation */ 2347 prediv = sr << (2 * c + 1); 2348 2349 /* 2350 * We need to calculate: 2351 * 2352 * br = freq / (prediv * bps) clamped to [1..256] 2353 * err = freq / (br * prediv) - bps 2354 * 2355 * Watch out for overflow when calculating the desired 2356 * sampling clock rate! 2357 */ 2358 if (bps > UINT_MAX / prediv) 2359 break; 2360 2361 scrate = prediv * bps; 2362 br = DIV_ROUND_CLOSEST(freq, scrate); 2363 br = clamp(br, 1U, 256U); 2364 2365 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2366 if (abs(err) >= abs(min_err)) 2367 continue; 2368 2369 min_err = err; 2370 *brr = br - 1; 2371 *srr = sr - 1; 2372 *cks = c; 2373 2374 if (!err) 2375 goto found; 2376 } 2377 } 2378 2379found: 2380 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2381 min_err, *brr, *srr + 1, *cks); 2382 return min_err; 2383} 2384 2385static void sci_reset(struct uart_port *port) 2386{ 2387 const struct plat_sci_reg *reg; 2388 unsigned int status; 2389 struct sci_port *s = to_sci_port(port); 2390 2391 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2392 2393 reg = sci_getreg(port, SCFCR); 2394 if (reg->size) 2395 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2396 2397 sci_clear_SCxSR(port, 2398 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2399 SCxSR_BREAK_CLEAR(port)); 2400 if (sci_getreg(port, SCLSR)->size) { 2401 status = sci_serial_in(port, SCLSR); 2402 status &= ~(SCLSR_TO | SCLSR_ORER); 2403 sci_serial_out(port, SCLSR, status); 2404 } 2405 2406 if (s->rx_trigger > 1) { 2407 if (s->rx_fifo_timeout) { 2408 scif_set_rtrg(port, 1); 2409 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2410 } else { 2411 if (port->type == PORT_SCIFA || 2412 port->type == PORT_SCIFB) 2413 scif_set_rtrg(port, 1); 2414 else 2415 scif_set_rtrg(port, s->rx_trigger); 2416 } 2417 } 2418} 2419 2420static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2421 const struct ktermios *old) 2422{ 2423 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2424 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2425 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2426 struct sci_port *s = to_sci_port(port); 2427 const struct plat_sci_reg *reg; 2428 int min_err = INT_MAX, err; 2429 unsigned long max_freq = 0; 2430 int best_clk = -1; 2431 unsigned long flags; 2432 2433 if ((termios->c_cflag & CSIZE) == CS7) { 2434 smr_val |= SCSMR_CHR; 2435 } else { 2436 termios->c_cflag &= ~CSIZE; 2437 termios->c_cflag |= CS8; 2438 } 2439 if (termios->c_cflag & PARENB) 2440 smr_val |= SCSMR_PE; 2441 if (termios->c_cflag & PARODD) 2442 smr_val |= SCSMR_PE | SCSMR_ODD; 2443 if (termios->c_cflag & CSTOPB) 2444 smr_val |= SCSMR_STOP; 2445 2446 /* 2447 * earlyprintk comes here early on with port->uartclk set to zero. 2448 * the clock framework is not up and running at this point so here 2449 * we assume that 115200 is the maximum baud rate. please note that 2450 * the baud rate is not programmed during earlyprintk - it is assumed 2451 * that the previous boot loader has enabled required clocks and 2452 * setup the baud rate generator hardware for us already. 2453 */ 2454 if (!port->uartclk) { 2455 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2456 goto done; 2457 } 2458 2459 for (i = 0; i < SCI_NUM_CLKS; i++) 2460 max_freq = max(max_freq, s->clk_rates[i]); 2461 2462 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2463 if (!baud) 2464 goto done; 2465 2466 /* 2467 * There can be multiple sources for the sampling clock. Find the one 2468 * that gives us the smallest deviation from the desired baud rate. 2469 */ 2470 2471 /* Optional Undivided External Clock */ 2472 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2473 port->type != PORT_SCIFB) { 2474 err = sci_sck_calc(s, baud, &srr1); 2475 if (abs(err) < abs(min_err)) { 2476 best_clk = SCI_SCK; 2477 scr_val = SCSCR_CKE1; 2478 sccks = SCCKS_CKS; 2479 min_err = err; 2480 srr = srr1; 2481 if (!err) 2482 goto done; 2483 } 2484 } 2485 2486 /* Optional BRG Frequency Divided External Clock */ 2487 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2488 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2489 &srr1); 2490 if (abs(err) < abs(min_err)) { 2491 best_clk = SCI_SCIF_CLK; 2492 scr_val = SCSCR_CKE1; 2493 sccks = 0; 2494 min_err = err; 2495 dl = dl1; 2496 srr = srr1; 2497 if (!err) 2498 goto done; 2499 } 2500 } 2501 2502 /* Optional BRG Frequency Divided Internal Clock */ 2503 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2504 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2505 &srr1); 2506 if (abs(err) < abs(min_err)) { 2507 best_clk = SCI_BRG_INT; 2508 scr_val = SCSCR_CKE1; 2509 sccks = SCCKS_XIN; 2510 min_err = err; 2511 dl = dl1; 2512 srr = srr1; 2513 if (!min_err) 2514 goto done; 2515 } 2516 } 2517 2518 /* Divided Functional Clock using standard Bit Rate Register */ 2519 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2520 if (abs(err) < abs(min_err)) { 2521 best_clk = SCI_FCK; 2522 scr_val = 0; 2523 min_err = err; 2524 brr = brr1; 2525 srr = srr1; 2526 cks = cks1; 2527 } 2528 2529done: 2530 if (best_clk >= 0) 2531 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2532 s->clks[best_clk], baud, min_err); 2533 2534 sci_port_enable(s); 2535 2536 /* 2537 * Program the optional External Baud Rate Generator (BRG) first. 2538 * It controls the mux to select (H)SCK or frequency divided clock. 2539 */ 2540 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2541 sci_serial_out(port, SCDL, dl); 2542 sci_serial_out(port, SCCKS, sccks); 2543 } 2544 2545 uart_port_lock_irqsave(port, &flags); 2546 2547 sci_reset(port); 2548 2549 uart_update_timeout(port, termios->c_cflag, baud); 2550 2551 /* byte size and parity */ 2552 bits = tty_get_frame_size(termios->c_cflag); 2553 2554 if (sci_getreg(port, SEMR)->size) 2555 sci_serial_out(port, SEMR, 0); 2556 2557 if (best_clk >= 0) { 2558 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2559 switch (srr + 1) { 2560 case 5: smr_val |= SCSMR_SRC_5; break; 2561 case 7: smr_val |= SCSMR_SRC_7; break; 2562 case 11: smr_val |= SCSMR_SRC_11; break; 2563 case 13: smr_val |= SCSMR_SRC_13; break; 2564 case 16: smr_val |= SCSMR_SRC_16; break; 2565 case 17: smr_val |= SCSMR_SRC_17; break; 2566 case 19: smr_val |= SCSMR_SRC_19; break; 2567 case 27: smr_val |= SCSMR_SRC_27; break; 2568 } 2569 smr_val |= cks; 2570 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2571 sci_serial_out(port, SCSMR, smr_val); 2572 sci_serial_out(port, SCBRR, brr); 2573 if (sci_getreg(port, HSSRR)->size) { 2574 unsigned int hssrr = srr | HSCIF_SRE; 2575 /* Calculate deviation from intended rate at the 2576 * center of the last stop bit in sampling clocks. 2577 */ 2578 int last_stop = bits * 2 - 1; 2579 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2580 (int)(srr + 1), 2581 2 * (int)baud); 2582 2583 if (abs(deviation) >= 2) { 2584 /* At least two sampling clocks off at the 2585 * last stop bit; we can increase the error 2586 * margin by shifting the sampling point. 2587 */ 2588 int shift = clamp(deviation / 2, -8, 7); 2589 2590 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2591 HSCIF_SRHP_MASK; 2592 hssrr |= HSCIF_SRDE; 2593 } 2594 sci_serial_out(port, HSSRR, hssrr); 2595 } 2596 2597 /* Wait one bit interval */ 2598 udelay((1000000 + (baud - 1)) / baud); 2599 } else { 2600 /* Don't touch the bit rate configuration */ 2601 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2602 smr_val |= sci_serial_in(port, SCSMR) & 2603 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2604 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2605 sci_serial_out(port, SCSMR, smr_val); 2606 } 2607 2608 sci_init_pins(port, termios->c_cflag); 2609 2610 port->status &= ~UPSTAT_AUTOCTS; 2611 s->autorts = false; 2612 reg = sci_getreg(port, SCFCR); 2613 if (reg->size) { 2614 unsigned short ctrl = sci_serial_in(port, SCFCR); 2615 2616 if ((port->flags & UPF_HARD_FLOW) && 2617 (termios->c_cflag & CRTSCTS)) { 2618 /* There is no CTS interrupt to restart the hardware */ 2619 port->status |= UPSTAT_AUTOCTS; 2620 /* MCE is enabled when RTS is raised */ 2621 s->autorts = true; 2622 } 2623 2624 /* 2625 * As we've done a sci_reset() above, ensure we don't 2626 * interfere with the FIFOs while toggling MCE. As the 2627 * reset values could still be set, simply mask them out. 2628 */ 2629 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2630 2631 sci_serial_out(port, SCFCR, ctrl); 2632 } 2633 if (port->flags & UPF_HARD_FLOW) { 2634 /* Refresh (Auto) RTS */ 2635 sci_set_mctrl(port, port->mctrl); 2636 } 2637 2638 /* 2639 * For SCI, TE (transmit enable) must be set after setting TIE 2640 * (transmit interrupt enable) or in the same instruction to 2641 * start the transmitting process. So skip setting TE here for SCI. 2642 */ 2643 if (port->type != PORT_SCI) 2644 scr_val |= SCSCR_TE; 2645 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2646 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); 2647 if ((srr + 1 == 5) && 2648 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2649 /* 2650 * In asynchronous mode, when the sampling rate is 1/5, first 2651 * received data may become invalid on some SCIFA and SCIFB. 2652 * To avoid this problem wait more than 1 serial data time (1 2653 * bit time x serial data number) after setting SCSCR.RE = 1. 2654 */ 2655 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2656 } 2657 2658 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2659 s->rx_frame = (10000 * bits) / (baud / 100); 2660#ifdef CONFIG_SERIAL_SH_SCI_DMA 2661 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2662#endif 2663 2664 if ((termios->c_cflag & CREAD) != 0) 2665 sci_start_rx(port); 2666 2667 uart_port_unlock_irqrestore(port, flags); 2668 2669 sci_port_disable(s); 2670 2671 if (UART_ENABLE_MS(port, termios->c_cflag)) 2672 sci_enable_ms(port); 2673} 2674 2675static void sci_pm(struct uart_port *port, unsigned int state, 2676 unsigned int oldstate) 2677{ 2678 struct sci_port *sci_port = to_sci_port(port); 2679 2680 switch (state) { 2681 case UART_PM_STATE_OFF: 2682 sci_port_disable(sci_port); 2683 break; 2684 default: 2685 sci_port_enable(sci_port); 2686 break; 2687 } 2688} 2689 2690static const char *sci_type(struct uart_port *port) 2691{ 2692 switch (port->type) { 2693 case PORT_IRDA: 2694 return "irda"; 2695 case PORT_SCI: 2696 return "sci"; 2697 case PORT_SCIF: 2698 return "scif"; 2699 case PORT_SCIFA: 2700 return "scifa"; 2701 case PORT_SCIFB: 2702 return "scifb"; 2703 case PORT_HSCIF: 2704 return "hscif"; 2705 } 2706 2707 return NULL; 2708} 2709 2710static int sci_remap_port(struct uart_port *port) 2711{ 2712 struct sci_port *sport = to_sci_port(port); 2713 2714 /* 2715 * Nothing to do if there's already an established membase. 2716 */ 2717 if (port->membase) 2718 return 0; 2719 2720 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2721 port->membase = ioremap(port->mapbase, sport->reg_size); 2722 if (unlikely(!port->membase)) { 2723 dev_err(port->dev, "can't remap port#%d\n", port->line); 2724 return -ENXIO; 2725 } 2726 } else { 2727 /* 2728 * For the simple (and majority of) cases where we don't 2729 * need to do any remapping, just cast the cookie 2730 * directly. 2731 */ 2732 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2733 } 2734 2735 return 0; 2736} 2737 2738static void sci_release_port(struct uart_port *port) 2739{ 2740 struct sci_port *sport = to_sci_port(port); 2741 2742 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2743 iounmap(port->membase); 2744 port->membase = NULL; 2745 } 2746 2747 release_mem_region(port->mapbase, sport->reg_size); 2748} 2749 2750static int sci_request_port(struct uart_port *port) 2751{ 2752 struct resource *res; 2753 struct sci_port *sport = to_sci_port(port); 2754 int ret; 2755 2756 res = request_mem_region(port->mapbase, sport->reg_size, 2757 dev_name(port->dev)); 2758 if (unlikely(res == NULL)) { 2759 dev_err(port->dev, "request_mem_region failed."); 2760 return -EBUSY; 2761 } 2762 2763 ret = sci_remap_port(port); 2764 if (unlikely(ret != 0)) { 2765 release_resource(res); 2766 return ret; 2767 } 2768 2769 return 0; 2770} 2771 2772static void sci_config_port(struct uart_port *port, int flags) 2773{ 2774 if (flags & UART_CONFIG_TYPE) { 2775 struct sci_port *sport = to_sci_port(port); 2776 2777 port->type = sport->cfg->type; 2778 sci_request_port(port); 2779 } 2780} 2781 2782static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2783{ 2784 if (ser->baud_base < 2400) 2785 /* No paper tape reader for Mitch.. */ 2786 return -EINVAL; 2787 2788 return 0; 2789} 2790 2791static const struct uart_ops sci_uart_ops = { 2792 .tx_empty = sci_tx_empty, 2793 .set_mctrl = sci_set_mctrl, 2794 .get_mctrl = sci_get_mctrl, 2795 .start_tx = sci_start_tx, 2796 .stop_tx = sci_stop_tx, 2797 .stop_rx = sci_stop_rx, 2798 .enable_ms = sci_enable_ms, 2799 .break_ctl = sci_break_ctl, 2800 .startup = sci_startup, 2801 .shutdown = sci_shutdown, 2802 .flush_buffer = sci_flush_buffer, 2803 .set_termios = sci_set_termios, 2804 .pm = sci_pm, 2805 .type = sci_type, 2806 .release_port = sci_release_port, 2807 .request_port = sci_request_port, 2808 .config_port = sci_config_port, 2809 .verify_port = sci_verify_port, 2810#ifdef CONFIG_CONSOLE_POLL 2811 .poll_get_char = sci_poll_get_char, 2812 .poll_put_char = sci_poll_put_char, 2813#endif 2814}; 2815 2816static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2817{ 2818 const char *clk_names[] = { 2819 [SCI_FCK] = "fck", 2820 [SCI_SCK] = "sck", 2821 [SCI_BRG_INT] = "brg_int", 2822 [SCI_SCIF_CLK] = "scif_clk", 2823 }; 2824 struct clk *clk; 2825 unsigned int i; 2826 2827 if (sci_port->cfg->type == PORT_HSCIF) 2828 clk_names[SCI_SCK] = "hsck"; 2829 2830 for (i = 0; i < SCI_NUM_CLKS; i++) { 2831 clk = devm_clk_get_optional(dev, clk_names[i]); 2832 if (IS_ERR(clk)) 2833 return PTR_ERR(clk); 2834 2835 if (!clk && i == SCI_FCK) { 2836 /* 2837 * Not all SH platforms declare a clock lookup entry 2838 * for SCI devices, in which case we need to get the 2839 * global "peripheral_clk" clock. 2840 */ 2841 clk = devm_clk_get(dev, "peripheral_clk"); 2842 if (IS_ERR(clk)) 2843 return dev_err_probe(dev, PTR_ERR(clk), 2844 "failed to get %s\n", 2845 clk_names[i]); 2846 } 2847 2848 if (!clk) 2849 dev_dbg(dev, "failed to get %s\n", clk_names[i]); 2850 else 2851 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2852 clk, clk_get_rate(clk)); 2853 sci_port->clks[i] = clk; 2854 } 2855 return 0; 2856} 2857 2858static const struct sci_port_params * 2859sci_probe_regmap(const struct plat_sci_port *cfg) 2860{ 2861 unsigned int regtype; 2862 2863 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2864 return &sci_port_params[cfg->regtype]; 2865 2866 switch (cfg->type) { 2867 case PORT_SCI: 2868 regtype = SCIx_SCI_REGTYPE; 2869 break; 2870 case PORT_IRDA: 2871 regtype = SCIx_IRDA_REGTYPE; 2872 break; 2873 case PORT_SCIFA: 2874 regtype = SCIx_SCIFA_REGTYPE; 2875 break; 2876 case PORT_SCIFB: 2877 regtype = SCIx_SCIFB_REGTYPE; 2878 break; 2879 case PORT_SCIF: 2880 /* 2881 * The SH-4 is a bit of a misnomer here, although that's 2882 * where this particular port layout originated. This 2883 * configuration (or some slight variation thereof) 2884 * remains the dominant model for all SCIFs. 2885 */ 2886 regtype = SCIx_SH4_SCIF_REGTYPE; 2887 break; 2888 case PORT_HSCIF: 2889 regtype = SCIx_HSCIF_REGTYPE; 2890 break; 2891 default: 2892 pr_err("Can't probe register map for given port\n"); 2893 return NULL; 2894 } 2895 2896 return &sci_port_params[regtype]; 2897} 2898 2899static int sci_init_single(struct platform_device *dev, 2900 struct sci_port *sci_port, unsigned int index, 2901 const struct plat_sci_port *p, bool early) 2902{ 2903 struct uart_port *port = &sci_port->port; 2904 const struct resource *res; 2905 unsigned int i; 2906 int ret; 2907 2908 sci_port->cfg = p; 2909 2910 port->ops = &sci_uart_ops; 2911 port->iotype = UPIO_MEM; 2912 port->line = index; 2913 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2914 2915 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2916 if (res == NULL) 2917 return -ENOMEM; 2918 2919 port->mapbase = res->start; 2920 sci_port->reg_size = resource_size(res); 2921 2922 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2923 if (i) 2924 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2925 else 2926 sci_port->irqs[i] = platform_get_irq(dev, i); 2927 } 2928 2929 /* 2930 * The fourth interrupt on SCI port is transmit end interrupt, so 2931 * shuffle the interrupts. 2932 */ 2933 if (p->type == PORT_SCI) 2934 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); 2935 2936 /* The SCI generates several interrupts. They can be muxed together or 2937 * connected to different interrupt lines. In the muxed case only one 2938 * interrupt resource is specified as there is only one interrupt ID. 2939 * In the non-muxed case, up to 6 interrupt signals might be generated 2940 * from the SCI, however those signals might have their own individual 2941 * interrupt ID numbers, or muxed together with another interrupt. 2942 */ 2943 if (sci_port->irqs[0] < 0) 2944 return -ENXIO; 2945 2946 if (sci_port->irqs[1] < 0) 2947 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2948 sci_port->irqs[i] = sci_port->irqs[0]; 2949 2950 sci_port->params = sci_probe_regmap(p); 2951 if (unlikely(sci_port->params == NULL)) 2952 return -EINVAL; 2953 2954 switch (p->type) { 2955 case PORT_SCIFB: 2956 sci_port->rx_trigger = 48; 2957 break; 2958 case PORT_HSCIF: 2959 sci_port->rx_trigger = 64; 2960 break; 2961 case PORT_SCIFA: 2962 sci_port->rx_trigger = 32; 2963 break; 2964 case PORT_SCIF: 2965 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2966 /* RX triggering not implemented for this IP */ 2967 sci_port->rx_trigger = 1; 2968 else 2969 sci_port->rx_trigger = 8; 2970 break; 2971 default: 2972 sci_port->rx_trigger = 1; 2973 break; 2974 } 2975 2976 sci_port->rx_fifo_timeout = 0; 2977 sci_port->hscif_tot = 0; 2978 2979 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2980 * match the SoC datasheet, this should be investigated. Let platform 2981 * data override the sampling rate for now. 2982 */ 2983 sci_port->sampling_rate_mask = p->sampling_rate 2984 ? SCI_SR(p->sampling_rate) 2985 : sci_port->params->sampling_rate_mask; 2986 2987 if (!early) { 2988 ret = sci_init_clocks(sci_port, &dev->dev); 2989 if (ret < 0) 2990 return ret; 2991 2992 port->dev = &dev->dev; 2993 2994 pm_runtime_enable(&dev->dev); 2995 } 2996 2997 port->type = p->type; 2998 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2999 port->fifosize = sci_port->params->fifosize; 3000 3001 if (port->type == PORT_SCI && !dev->dev.of_node) { 3002 if (sci_port->reg_size >= 0x20) 3003 port->regshift = 2; 3004 else 3005 port->regshift = 1; 3006 } 3007 3008 /* 3009 * The UART port needs an IRQ value, so we peg this to the RX IRQ 3010 * for the multi-IRQ ports, which is where we are primarily 3011 * concerned with the shutdown path synchronization. 3012 * 3013 * For the muxed case there's nothing more to do. 3014 */ 3015 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 3016 port->irqflags = 0; 3017 3018 return 0; 3019} 3020 3021static void sci_cleanup_single(struct sci_port *port) 3022{ 3023 pm_runtime_disable(port->port.dev); 3024} 3025 3026#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3027 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3028static void serial_console_putchar(struct uart_port *port, unsigned char ch) 3029{ 3030 sci_poll_put_char(port, ch); 3031} 3032 3033/* 3034 * Print a string to the serial port trying not to disturb 3035 * any possible real use of the port... 3036 */ 3037static void serial_console_write(struct console *co, const char *s, 3038 unsigned count) 3039{ 3040 struct sci_port *sci_port = &sci_ports[co->index]; 3041 struct uart_port *port = &sci_port->port; 3042 unsigned short bits, ctrl, ctrl_temp; 3043 unsigned long flags; 3044 int locked = 1; 3045 3046 if (port->sysrq) 3047 locked = 0; 3048 else if (oops_in_progress) 3049 locked = uart_port_trylock_irqsave(port, &flags); 3050 else 3051 uart_port_lock_irqsave(port, &flags); 3052 3053 /* first save SCSCR then disable interrupts, keep clock source */ 3054 ctrl = sci_serial_in(port, SCSCR); 3055 ctrl_temp = SCSCR_RE | SCSCR_TE | 3056 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3057 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3058 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3059 3060 uart_console_write(port, s, count, serial_console_putchar); 3061 3062 /* wait until fifo is empty and last bit has been transmitted */ 3063 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3064 while ((sci_serial_in(port, SCxSR) & bits) != bits) 3065 cpu_relax(); 3066 3067 /* restore the SCSCR */ 3068 sci_serial_out(port, SCSCR, ctrl); 3069 3070 if (locked) 3071 uart_port_unlock_irqrestore(port, flags); 3072} 3073 3074static int serial_console_setup(struct console *co, char *options) 3075{ 3076 struct sci_port *sci_port; 3077 struct uart_port *port; 3078 int baud = 115200; 3079 int bits = 8; 3080 int parity = 'n'; 3081 int flow = 'n'; 3082 int ret; 3083 3084 /* 3085 * Refuse to handle any bogus ports. 3086 */ 3087 if (co->index < 0 || co->index >= SCI_NPORTS) 3088 return -ENODEV; 3089 3090 sci_port = &sci_ports[co->index]; 3091 port = &sci_port->port; 3092 3093 /* 3094 * Refuse to handle uninitialized ports. 3095 */ 3096 if (!port->ops) 3097 return -ENODEV; 3098 3099 ret = sci_remap_port(port); 3100 if (unlikely(ret != 0)) 3101 return ret; 3102 3103 if (options) 3104 uart_parse_options(options, &baud, &parity, &bits, &flow); 3105 3106 return uart_set_options(port, co, baud, parity, bits, flow); 3107} 3108 3109static struct console serial_console = { 3110 .name = "ttySC", 3111 .device = uart_console_device, 3112 .write = serial_console_write, 3113 .setup = serial_console_setup, 3114 .flags = CON_PRINTBUFFER, 3115 .index = -1, 3116 .data = &sci_uart_driver, 3117}; 3118 3119#ifdef CONFIG_SUPERH 3120static char early_serial_buf[32]; 3121 3122static int early_serial_console_setup(struct console *co, char *options) 3123{ 3124 /* 3125 * This early console is always registered using the earlyprintk= 3126 * parameter, which does not call add_preferred_console(). Thus 3127 * @options is always NULL and the options for this early console 3128 * are passed using a custom buffer. 3129 */ 3130 WARN_ON(options); 3131 3132 return serial_console_setup(co, early_serial_buf); 3133} 3134 3135static struct console early_serial_console = { 3136 .name = "early_ttySC", 3137 .write = serial_console_write, 3138 .setup = early_serial_console_setup, 3139 .flags = CON_PRINTBUFFER, 3140 .index = -1, 3141}; 3142 3143static int sci_probe_earlyprintk(struct platform_device *pdev) 3144{ 3145 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3146 3147 if (early_serial_console.data) 3148 return -EEXIST; 3149 3150 early_serial_console.index = pdev->id; 3151 3152 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3153 3154 if (!strstr(early_serial_buf, "keep")) 3155 early_serial_console.flags |= CON_BOOT; 3156 3157 register_console(&early_serial_console); 3158 return 0; 3159} 3160#endif 3161 3162#define SCI_CONSOLE (&serial_console) 3163 3164#else 3165static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3166{ 3167 return -EINVAL; 3168} 3169 3170#define SCI_CONSOLE NULL 3171 3172#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3173 3174static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3175 3176static DEFINE_MUTEX(sci_uart_registration_lock); 3177static struct uart_driver sci_uart_driver = { 3178 .owner = THIS_MODULE, 3179 .driver_name = "sci", 3180 .dev_name = "ttySC", 3181 .major = SCI_MAJOR, 3182 .minor = SCI_MINOR_START, 3183 .nr = SCI_NPORTS, 3184 .cons = SCI_CONSOLE, 3185}; 3186 3187static void sci_remove(struct platform_device *dev) 3188{ 3189 struct sci_port *port = platform_get_drvdata(dev); 3190 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3191 3192 sci_ports_in_use &= ~BIT(port->port.line); 3193 uart_remove_one_port(&sci_uart_driver, &port->port); 3194 3195 sci_cleanup_single(port); 3196 3197 if (port->port.fifosize > 1) 3198 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3199 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3200 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3201} 3202 3203 3204#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3205#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3206#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3207 3208static const struct of_device_id of_sci_match[] __maybe_unused = { 3209 /* SoC-specific types */ 3210 { 3211 .compatible = "renesas,scif-r7s72100", 3212 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3213 }, 3214 { 3215 .compatible = "renesas,scif-r7s9210", 3216 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3217 }, 3218 { 3219 .compatible = "renesas,scif-r9a07g044", 3220 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3221 }, 3222 /* Family-specific types */ 3223 { 3224 .compatible = "renesas,rcar-gen1-scif", 3225 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3226 }, { 3227 .compatible = "renesas,rcar-gen2-scif", 3228 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3229 }, { 3230 .compatible = "renesas,rcar-gen3-scif", 3231 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3232 }, { 3233 .compatible = "renesas,rcar-gen4-scif", 3234 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3235 }, 3236 /* Generic types */ 3237 { 3238 .compatible = "renesas,scif", 3239 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3240 }, { 3241 .compatible = "renesas,scifa", 3242 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3243 }, { 3244 .compatible = "renesas,scifb", 3245 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3246 }, { 3247 .compatible = "renesas,hscif", 3248 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3249 }, { 3250 .compatible = "renesas,sci", 3251 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3252 }, { 3253 /* Terminator */ 3254 }, 3255}; 3256MODULE_DEVICE_TABLE(of, of_sci_match); 3257 3258static void sci_reset_control_assert(void *data) 3259{ 3260 reset_control_assert(data); 3261} 3262 3263static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3264 unsigned int *dev_id) 3265{ 3266 struct device_node *np = pdev->dev.of_node; 3267 struct reset_control *rstc; 3268 struct plat_sci_port *p; 3269 struct sci_port *sp; 3270 const void *data; 3271 int id, ret; 3272 3273 if (!IS_ENABLED(CONFIG_OF) || !np) 3274 return ERR_PTR(-EINVAL); 3275 3276 data = of_device_get_match_data(&pdev->dev); 3277 3278 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3279 if (IS_ERR(rstc)) 3280 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3281 "failed to get reset ctrl\n")); 3282 3283 ret = reset_control_deassert(rstc); 3284 if (ret) { 3285 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3286 return ERR_PTR(ret); 3287 } 3288 3289 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3290 if (ret) { 3291 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3292 ret); 3293 return ERR_PTR(ret); 3294 } 3295 3296 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3297 if (!p) 3298 return ERR_PTR(-ENOMEM); 3299 3300 /* Get the line number from the aliases node. */ 3301 id = of_alias_get_id(np, "serial"); 3302 if (id < 0 && ~sci_ports_in_use) 3303 id = ffz(sci_ports_in_use); 3304 if (id < 0) { 3305 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3306 return ERR_PTR(-EINVAL); 3307 } 3308 if (id >= ARRAY_SIZE(sci_ports)) { 3309 dev_err(&pdev->dev, "serial%d out of range\n", id); 3310 return ERR_PTR(-EINVAL); 3311 } 3312 3313 sp = &sci_ports[id]; 3314 *dev_id = id; 3315 3316 p->type = SCI_OF_TYPE(data); 3317 p->regtype = SCI_OF_REGTYPE(data); 3318 3319 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3320 3321 return p; 3322} 3323 3324static int sci_probe_single(struct platform_device *dev, 3325 unsigned int index, 3326 struct plat_sci_port *p, 3327 struct sci_port *sciport) 3328{ 3329 int ret; 3330 3331 /* Sanity check */ 3332 if (unlikely(index >= SCI_NPORTS)) { 3333 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3334 index+1, SCI_NPORTS); 3335 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3336 return -EINVAL; 3337 } 3338 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3339 if (sci_ports_in_use & BIT(index)) 3340 return -EBUSY; 3341 3342 mutex_lock(&sci_uart_registration_lock); 3343 if (!sci_uart_driver.state) { 3344 ret = uart_register_driver(&sci_uart_driver); 3345 if (ret) { 3346 mutex_unlock(&sci_uart_registration_lock); 3347 return ret; 3348 } 3349 } 3350 mutex_unlock(&sci_uart_registration_lock); 3351 3352 ret = sci_init_single(dev, sciport, index, p, false); 3353 if (ret) 3354 return ret; 3355 3356 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3357 if (IS_ERR(sciport->gpios)) 3358 return PTR_ERR(sciport->gpios); 3359 3360 if (sciport->has_rtscts) { 3361 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3362 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3363 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3364 return -EINVAL; 3365 } 3366 sciport->port.flags |= UPF_HARD_FLOW; 3367 } 3368 3369 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3370 if (ret) { 3371 sci_cleanup_single(sciport); 3372 return ret; 3373 } 3374 3375 return 0; 3376} 3377 3378static int sci_probe(struct platform_device *dev) 3379{ 3380 struct plat_sci_port *p; 3381 struct sci_port *sp; 3382 unsigned int dev_id; 3383 int ret; 3384 3385 /* 3386 * If we've come here via earlyprintk initialization, head off to 3387 * the special early probe. We don't have sufficient device state 3388 * to make it beyond this yet. 3389 */ 3390#ifdef CONFIG_SUPERH 3391 if (is_sh_early_platform_device(dev)) 3392 return sci_probe_earlyprintk(dev); 3393#endif 3394 3395 if (dev->dev.of_node) { 3396 p = sci_parse_dt(dev, &dev_id); 3397 if (IS_ERR(p)) 3398 return PTR_ERR(p); 3399 } else { 3400 p = dev->dev.platform_data; 3401 if (p == NULL) { 3402 dev_err(&dev->dev, "no platform data supplied\n"); 3403 return -EINVAL; 3404 } 3405 3406 dev_id = dev->id; 3407 } 3408 3409 sp = &sci_ports[dev_id]; 3410 platform_set_drvdata(dev, sp); 3411 3412 ret = sci_probe_single(dev, dev_id, p, sp); 3413 if (ret) 3414 return ret; 3415 3416 if (sp->port.fifosize > 1) { 3417 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3418 if (ret) 3419 return ret; 3420 } 3421 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3422 sp->port.type == PORT_HSCIF) { 3423 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3424 if (ret) { 3425 if (sp->port.fifosize > 1) { 3426 device_remove_file(&dev->dev, 3427 &dev_attr_rx_fifo_trigger); 3428 } 3429 return ret; 3430 } 3431 } 3432 3433#ifdef CONFIG_SH_STANDARD_BIOS 3434 sh_bios_gdb_detach(); 3435#endif 3436 3437 sci_ports_in_use |= BIT(dev_id); 3438 return 0; 3439} 3440 3441static __maybe_unused int sci_suspend(struct device *dev) 3442{ 3443 struct sci_port *sport = dev_get_drvdata(dev); 3444 3445 if (sport) 3446 uart_suspend_port(&sci_uart_driver, &sport->port); 3447 3448 return 0; 3449} 3450 3451static __maybe_unused int sci_resume(struct device *dev) 3452{ 3453 struct sci_port *sport = dev_get_drvdata(dev); 3454 3455 if (sport) 3456 uart_resume_port(&sci_uart_driver, &sport->port); 3457 3458 return 0; 3459} 3460 3461static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3462 3463static struct platform_driver sci_driver = { 3464 .probe = sci_probe, 3465 .remove_new = sci_remove, 3466 .driver = { 3467 .name = "sh-sci", 3468 .pm = &sci_dev_pm_ops, 3469 .of_match_table = of_match_ptr(of_sci_match), 3470 }, 3471}; 3472 3473static int __init sci_init(void) 3474{ 3475 pr_info("%s\n", banner); 3476 3477 return platform_driver_register(&sci_driver); 3478} 3479 3480static void __exit sci_exit(void) 3481{ 3482 platform_driver_unregister(&sci_driver); 3483 3484 if (sci_uart_driver.state) 3485 uart_unregister_driver(&sci_uart_driver); 3486} 3487 3488#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3489sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3490 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3491#endif 3492#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3493static struct plat_sci_port port_cfg __initdata; 3494 3495static int __init early_console_setup(struct earlycon_device *device, 3496 int type) 3497{ 3498 if (!device->port.membase) 3499 return -ENODEV; 3500 3501 device->port.type = type; 3502 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3503 port_cfg.type = type; 3504 sci_ports[0].cfg = &port_cfg; 3505 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3506 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3507 sci_serial_out(&sci_ports[0].port, SCSCR, 3508 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3509 3510 device->con->write = serial_console_write; 3511 return 0; 3512} 3513static int __init sci_early_console_setup(struct earlycon_device *device, 3514 const char *opt) 3515{ 3516 return early_console_setup(device, PORT_SCI); 3517} 3518static int __init scif_early_console_setup(struct earlycon_device *device, 3519 const char *opt) 3520{ 3521 return early_console_setup(device, PORT_SCIF); 3522} 3523static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3524 const char *opt) 3525{ 3526 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3527 return early_console_setup(device, PORT_SCIF); 3528} 3529 3530static int __init scifa_early_console_setup(struct earlycon_device *device, 3531 const char *opt) 3532{ 3533 return early_console_setup(device, PORT_SCIFA); 3534} 3535static int __init scifb_early_console_setup(struct earlycon_device *device, 3536 const char *opt) 3537{ 3538 return early_console_setup(device, PORT_SCIFB); 3539} 3540static int __init hscif_early_console_setup(struct earlycon_device *device, 3541 const char *opt) 3542{ 3543 return early_console_setup(device, PORT_HSCIF); 3544} 3545 3546OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3547OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3548OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3549OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3550OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3551OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3552OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3553#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3554 3555module_init(sci_init); 3556module_exit(sci_exit); 3557 3558MODULE_LICENSE("GPL"); 3559MODULE_ALIAS("platform:sh-sci"); 3560MODULE_AUTHOR("Paul Mundt"); 3561MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3562